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TEXAS INSTRUMENTS INC.HIGH PERFORMANCE ANALOG
HIGH SPEED AMPLIFIERS
Design Guide
Considerations for High-Gain MultistageDesigns
Pavol Balaz
Contents
1 Introduction 1
2 Signal-Chain Considerations 12.1 First Stage - Input Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3 Following Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Output Offset Voltage and Stability Considerations 33.1 Output Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.2 Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . . 4
4 Simulations 5
5 Circuit Implementation and Board Design 6
6 Evaluation 11
7 Conclusion 11
References 14
ii
List of Figures
2.1 Simplified Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1 Operational Amplifier Emitter Output Stage . . . . . . . . . . . . . . . . . . . 43.2 Impedance vs. Frequency for a 100 nF multilayer ceramic chip capacitor [TDK13] 5
4.1 Final Simulation Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Simulated Frequency Response, CAC−GAIN = 10nF . . . . . . . . . . . . . . . 74.3 Simulated Frequency Response, CAC−GAIN = 10µF . . . . . . . . . . . . . . . 74.4 Simulated SNR, CAC−GAIN = 10µF . . . . . . . . . . . . . . . . . . . . . . . . 74.5 Schematic of the implemented High-Gain, High-Bandwidth Circuit . . . . . . . 85.1 PCB - Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105.2 PCB - Mid Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105.3 PCB - Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1 Measured Output Signal, Sine Input, fIN = 1MHz, VIN = 20µVP P ,CAC−GAIN = 10µF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 Measured Output Signal, Sine Input, fIN = 5MHz, VIN = 20µVP P ,CAC−GAIN = 10µF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.3 Measured Output Signal, Sine Input, fIN = 10MHz, VIN = 20µVP P ,CAC−GAIN = 10µF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.4 Measured Frequency Response, 10kHz-100MHz, CAC−GAIN = 10nF . . . . . . 136.5 Measured Frequency Response, 10kHz-100MHz, CAC−GAIN = 10µF . . . . . . 13
List of Tables
2.1 Devices combining high GBWP and low input noise . . . . . . . . . . . . . . . 12.2 Current Feedback OP-Amps combining high gain with high BW . . . . . . . . 3
iii
1 Introduction
Amplifying a voltage signal by more than 100 VV using a single operational amplifier while
maintaining several MHz, or even tens of MHz of bandwidth, can prove difficult to both designand to implement. The goal of this paper is to describe the development and the physicalimplementation of a high-gain, multi-stage design featuring a voltage gain well above 100 V
V .The first part of the paper discusses the general factors to be considered during the designphase while the second part focuses on physical implementation.
2 Signal-Chain Considerations
2.1 First Stage - Input Noise
Since the noise of the first stage is the limiting factor from a noise perspective, input noiseis one of the most important factors to be considered when selecting the amplifier for thefirst stage. Another key factor is the available bandwidth. Starting with the traditional gain-bandwidth product (GBWP) where the product of the gain and the bandwidth is constantfor a voltage-feedback amplifier (see 2.1), a quick survey of non-unity gain stable amplifierscombining the highest possible GBWP and low noise yields the results as shown in table 2.1.
Gain×Bandwidth = GBWP (2.1)
Table 2.1: Devices combining high GBWP and low input noise
Part Number Input Voltage Noise Density [nV/√Hz] GBWP [MHz]
OPA847 0.85 3900OPA846 1.1 1800LMH6629 0.69 3900
Note that FET input devices have not been considered here because the input voltage noisetends to be high, while input current noise is low. Because low value resistors are used to
1
2 Signal-Chain Considerations
minimize noise contribution, the low input bias current of a FET amplifier is not needed here.Only relatively low input impedance voltage sources are considered.
2.2 Noise Considerations
Consider using a non-inverting amplifier architecture, allowing its input impedance to bematched to any source impedance as well as minimizing system noise. Also, at high gain,the output voltage noise density can be approximated as shown in equation 2.2.
eo∼= (en +
√4kTRS)×
(1 + RF
RG
)(2.2)
where
• k = 1.3806488 ×10−23 m2kgs−2K−1
• T = temperature in Kelvins
Note that in this model, both the current noise and the resistor noise are considered to benegligible.
Figure 2.1: Simplified Noise Model
I
RF
RG
RS
eo
en
( )4 1F
o n S
G
Re e kTR
R
æ ö@ + ´ +ç ÷
è ø
Gain Bandwidth GBWP´ =
Signal-Chain Considerations www.ti.com
1 Signal-Chain Considerations
1.1 Input Noise
Starting with the traditional gain-bandwidth product (GBWP), where the product of the gain and thebandwidth is constant for a voltage-feedback amplifier (as shown in Equation 1), a quick survey ofnonunity gain stable amplifiers that achieve the highest possible GBWP and low noise yields the resultsshown in Table 1.
(1)
Table 1. High GBWP Product and Low-Noise Devices
Part Number Input Voltage Noise Density (nV/√Hz) GBWP (MHz)
OPA847 0.85 3900
OPA846 1.1 1800
LMH6629 0.69 3900
Note that FET input devices have not been considered here because the input voltage noise tends to behigh, while input current noise is low. Because low value resistors are used to minimize noise contribution,the low input bias current of a FET amplifier is not needed here; only relatively low input impedancevoltage sources are considered.
1.2 Noise Considerations
Consider using a noninverting amplifier architecture, allowing its input impedance to be matched to anysource impedance as well as minimizing system noise. Also at high-gain, the output voltage noise densitycan be approximated as shown in Equation 2:
where• k = 1.380658 × 10–23
• T = temperature in kelvins (2)
Note that in this model, both the current noise and the resistor noise are considered negligible.
Figure 1. Simplified Noise Model
2 Considerations for High-Gain Multistage Designs SBOA135–May 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
The SNR for a such a configuration is shown in equation 2.3.
SNR(dB) = 20× log(
Vorms
eo ×√NPWB
)(2.3)
where NPBW = the noise power bandwidth of the stage. Each stage amplifies the noise fromthe previous stage and adds its own noise. For two stages, the result is shown in equation2.4.
e2o = e2
o1 +(e2
o1 ×G22
)+ e2
o2 (2.4)
e2o = e2
o1 × (1 +G22) + e2
o2 (2.5)
2
where eo, eo1 and eo2 are the output voltage noise densities in nV√Hz
of the total system, thefirst stage and the second stage, respectively.
Also, in order to maximize SNR, additional RC filters can be added between the stages.
The total gain equals the sum (in dB) or product (in VV ) of the gain of each stage as shown
in
Gtot
[V
V
]= G1
[V
V
]×G2
[V
V
]× ...×Gn
[V
V
](2.6)
Gtot [dB] = G1 [dB] +G2 [dB] + ...+Gn [dB] (2.7)
2.3 Following Stages
Since the noise of the first stage is the limiting factor from a noise perspective, any stage otherthan the first stage does not require very low noise. The entire current-feedback amplifierportfolio is now available for selection. Table 2.2 provides a selection of amplifiers suited forboth high gain and high bandwidth applications.
Table 2.2: Current Feedback OP-Amps combining high gain with high BW
Part Number Gain at BW [V/V] BW [MHz] CommentOPA683 100 35 Lowest power solutionOPA684 100 70 Highest equivalent GBWPOPA695 16 350 Highest BW solution
Note that either inverting or non-inverting gain circuits can be considered, depending on theamplifier and the desired bandwidth. The OPA695 achieves lower noise in an inverting configu-ration whereas the OPA683 and OPA684 achieve lower noise in the non-inverting configuration.Because we are set to achieve high gain on a single stage, the gain resistor can be as low as10 Ω. In an inverting topology, this setting can place an additional constraint on the drivingstage. In practice, keep the gain resistor between 10 Ω and 50 Ω and do not exceed 1.5 kΩfor the feedback resistor. Remember that the frequency response is limited by the feedbackresistor (RF ) and the feedback capacitor (CF ) pole - there always will be a parasitic capacitoras a result of the component layout, and so forth.
The following sections of this design guide focus on output offset voltage and stability issues.
3
3 Output Offset Voltage and Stability Considerations
3 Output Offset Voltage and StabilityConsiderations
In the previous sections, this design guide discussed signal chain considerations to matchrequired gain and bandwidth while maintaining sufficient SNR. Two issues remain to makethis circuit easily implementable:
1. DC accuracy requirements
2. Amplifier power supply rejection ratio (PSRR)
3.1 Output Offset Voltage
Since very high gains are targeted, any DC error in the first or even the second stage can provefatal to any implementation. The simplest way to circumvent the output offset voltage is tomake sure that the DC gain of each stage is unity. Adding an AC coupling capacitor in serieswith the gain resistor solves this issue. Care must be taken when specifying the capacitorvalue. This will be discussed later in the simulation section.
3.2 Power Supply Rejection Ratio (PSRR)
Figure 3.1: Operational Amplifier Emitter Output Stage+V
S
-VS
Out
Implementation and Stability Considerations www.ti.com
2 Implementation and Stability Considerations
In the first section, this application report discussed signal-chain considerations to match required gainand bandwidth while maintaining sufficient SNR. Two issues remain to make this circuit easilyimplementable: the dc accuracy requirements and amplifier power-supply rejection ratio (PSRR).
2.1 Output Offset Voltage
The gain can be very large; therefore, any dc error in the first or even the second stage can prove fatal toany implementation. Care must be taken to make sure that the output offset voltage of the multistageamplifier is sufficient. AC-coupling, or making sure that the dc gain is in unity, is the simplest approach.(Implementing a dc-feedback loop is another option, but is beyond the scope of this discussion.)
2.2 Power-Supply Rejection Ratio (PSRR)
As a result of the high gain, the signal in the load creates some disturbance in the power supply, asshown in Figure 2. However, this disturbance does not appear in the simulation unless the line regulationof a nonideal power supply is implemented.
Figure 2. Operational Amplifier Emitter Output Stage
Such disturbance is seen by the first stage, and if the PSRR of the first amplifier is insufficient at thefrequency of interest, the disturbance finds its way into the signal path, resulting in oscillations.
Preventing these oscillations requires careful planning in regards to the power supply. The power supply isconnected directly to the last amplifier of the high-gain signal chain. From this last amplifier to the previousone, an inductor is placed in series in the power supply path. This inductor combined with the local bypasscapacitor forms a low-pass filter and attenuates the disturbance. In the implementation shown, inductorsare placed only in the positive supply.
A positive feedback loop created in the supply can happen on both positive and negative supplies;therefore, it may be necessary to implement this scheme on both supplies.
Additionally, a single operational amplifier must be used; oscillation occurs when using dual, triple, or quadamplifiers because they share the power supplies internally.
4 Considerations for High-Gain Multistage Designs SBOA135–May 2013Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
The output current flows through the output stage transistor and is originating from the powersupply, as expected. If the supply is ideal and has constant low impedance over frequency,
4
Figure 3.2: Impedance vs. Frequency for a 100 nF multilayer ceramic chip capacitor [TDK13]
Commercial Grade ( General (Up to 50V) )
C1608 [EIA CC0603]
L 1.60mm +/-0.1mmW 0.80mm +/-0.1mmT 0.80mm +/-0.1mmB 0.20mm Min.G 0.30mm Min.
X7R (-55 to 125 degC +/-15%)
1E (25Vdc)
100nF
K (+/-10%)
3% Max.
5Gohm Min.
Not Applicable
All specifications are subject to change without notice. September 28, 2013
C1608X7R1E104K080AATDK Item Description : C1608X7R1E104KT****
Cap. vs. Freq. Characteristic
1
10
100
1000
0.001 0.01 0.1 1 10 100 1000
Frequency/MHz
Cap.
/nF
|Z|, ESR vs. Freq. Characteristics
0.01
0.1
1
10
100
1000
10000
100000
0.001 0.01 0.1 1 10 100 1000
Frequency/MHz
|Z|,
ESR
/ohm
|Z| ESR
DC Bias Characteristic
-25
-20
-15
-10
-5
0
5
0 5 10 15 20 25 30
DC Bias/V
Cap.
Cha
nge/
%
Temperature Characteristic
-90-80-70-60-50-40-30-20-10
01020
-80 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature/degC
Cap.
Cha
nge/
%
Temp.Chara. TCBias(1/2Rated)
Ripple Temperature Rise Characteristic
0
5
10
15
20
25
0 0.2 0.4 0.6 0.8 1 1.2
Current/Arms
Tem
pera
ture
Rise
/deg
C
100kHz 500kHz 1MHz
Application & Main Feature
Series
Dimensions
Temperature Characteristic
Rated Voltage
Capacitance
Capacitance Tolerance
Dissipation Factor
Insulation Resitance
AEC-Q200
Cha
ract
eriza
tion
Shee
t ( M
ultil
aye
r Cer
am
ic C
hip
Ca
pa
cito
rs )
no disturbance will appear. However, the impedance of the supply will vary over frequency,either due to the limited bandwidth of a supply such as a LDO or due to the limitations ofthe bypass capacitor maintaining constant impedance over frequency. Figure 3.2 shows theimpedance over frequency plot for a 100 nF multilayer ceramic chip capacitor.
It is possible to minimize such effect over frequency by putting capacitors of different technologyand values in parallel. However, no matter how good the power supply regulator or thebypassing implementation, the impedance of the supply will have ripples upon which the loadcurrent will create a small signal riding on the power supply. This signal is referred to asdisturbance in the following discussion.
However, this disturbance does not appear in the simulation unless the line regulation of anon-ideal power supply is implemented.
Such disturbance is seen by the first stage and if the PSRR of the first amplifier is insufficientat the frequency of interest, the disturbance finds its way into the signal path and will beamplified by the high gain of the following stages, eventually resulting in oscillations.
Preventing these oscillations requires careful planning in regards to the power supply. Thepower supply is connected directly to the last amplifier of the high gain signal chain. Fromthis last amplifier to the previous one, an inductor is placed in series in the power supply path.This inductor combined with the local bypass capacitor forms a low pass filter that attenuatesthe disturbance. A positive feedback loop created in the supply can happen on both positiveand negative supplies. Therefore, this needs to be implemented on both supplies.
Additionally, a single operational amplifier package must be used. Since dual, triple or quadamplifier packages share the power supplies internally, oscillations may occur since no filteringcan be done externally.
5
4 Simulations
The schematic shown in figure 4.1 reflects all the items discussed in the previous sections andshows a possible implementation for a +5V single supply, providing a voltage gain of approx.120,000 V/V. Please note that a single +5V supply was used in simulation, therefore noinductors are present on the negative supply side.
Following is a short summary of the items discussed in the previous sections:
• Very low input voltage noise density amplifier on the first stage (LMH6629)
• High gain, high bandwidth amplifiers on the following stages (OPA684)
• AC coupling capacitors in series with the gain resistors to ensure DC gain equals unity(C1,C2,C3)
• Inductors in the power supply line between the stages to implement LC filters using thebypass capacitor, creating low pass filters to attenuate the disturbances in the powersupply line
• RC filters between the stages to increase SNR
Figure 4.1: Final Simulation Schematic
Vcc
Vcc
Vcc
Vcc
Stg_2_Out
Stg_1_OutStg_3_Out
V1 5
L2 1mL1 1m
R10 100R9 100
R8
100
R7 100
R6 27 R5 20,5 R4 24,9 R3 1,3kR2 1,3kR1 1k
C10
106
p
C9
106p
C8
20p
C6
100n
C5
100n
C4
100n
C3 10uC2 10uC1 10u
+ VG1
-
+ +
U3 OPA684
-
+ +
U2 OPA684
-
+ +
U1 LMH6629
Figures 4.2 and 4.3 show simulated frequency responses with different gain AC coupling ca-pacitor values. To ensure that the flat band is as wide as possible, select high capacitor values.On the stages featuring the current feedback OPA684 amplifier, the gain resistor shields thecapacitor from the low impedance non-inverting input of the amplifier.
Figure 4.4 shows the simulated SNR.
6
5 Circuit Implementation and Board Design
Figure 4.2: Simulated Frequency Response, CAC−GAIN = 10nF
Stg_1_Out
Stg_2_Out
Stg_3_Out
Frequency (Hz)10.00 100.00 1.00k 10.00k 100.00k 1.00M 10.00M 100.00M 1.00G
Gai
n (d
B)
-200.00
-100.00
0.00
100.00
200.00
Stg_1_Out
Stg_2_Out
Stg_3_Out
Figure 4.3: Simulated Frequency Response, CAC−GAIN = 10µF
Stg_1_Out
Stg_2_Out
Stg_3_Out
Frequency (Hz)10.00 100.00 1.00k 10.00k 100.00k 1.00M 10.00M 100.00M 1.00G
Gai
n (d
B)
-200.00
-100.00
0.00
100.00
200.00
Stg_1_Out
Stg_2_Out
Stg_3_Out
Figure 4.4: Simulated SNR, CAC−GAIN = 10µF
Stg_1_Out
Stg_2_Out
Stg_3_Out
Frequency (Hz)100k 1M 10M 100M
Sig
nal t
o N
oise
[dB
]
0.00
50.00
100.00
150.00
200.00
Stg_3_Out
Stg_2_Out
Stg_1_Out
7
5 Circuit Implementation and Board Design
Figure 4.5: Schematic of the implemented High-Gain, High-Bandwidth Circuit
1 1
2 2
3 3
4 4
DD
CC
BB
AA
1
HSSC-TU
CTEXA
S INSTRU
MEN
TS5411 E. W
illiams Blvd
Tucson, AZ 85711
U.S.A
.1
HIG
H G
AIN PC
BPR2043
A03.10.2013
16:29:13C:\Tem
p\ToDo\Tucson\H
ighGainM
ultistage\Altium
\_new\Tri_PPTX.SchD
oc
Title
Size:Num
ber:
Date:
File:
Revision:
Sheetof
Time:
ATI
-Vcc
+Vcc
22
11
33
P1
R21ΚΩ
R127Ω
C20.1uF
C30.1uF
R51.3ΚΩ
C60.1uF
C70.1uF
-Vcc
R3100Ω
C5106pFJ1 VG
1J2
Sig3_Out
-In4
+In3
+V 6-V2
NC5 Vout1
U1
LMH6629
-In2
+In3
+V s 7-V s4
NC1
NC5
Vout6
/DIS 8U2
OPA
684ID
R420.5Ω
C410uF
C110uF
R81.3ΚΩ
R724.9Ω
C810uF
R9100Ω
C9106pF
C100.1uF
+Vcc
-In2
+In3
+V s 7-V s4
NC1
NC5
Vout6
/DIS 8U3
OPA
684ID
R12100Ω
R11100Ω
C1220pF
21
L41uH
C110.1uF
21
L31uH 2
1L1
1uH2
1L2
1uH
R649.9ΩR1049.9
C1310uF
C1410uF
+2.5Vdc
R1349.9Ω
Open
Open
Open
+2.35V
-2.35V
8
5 Circuit Implementation and Board Design
5 Circuit Implementation and Board Design
Simulations are only proof of concepts and should be considered with caution. Therefore, adedicated board for this circuit was designed to verify functionality.
The board circuit is shown in figure 4.5. Note there are two principal distinctions between theschematic simulated and its implementation:
1. The power supplies are bipolar
2. The inductors on the negative supply are explicitly shown here
The layout has three layers. The top layer has most of the circuitry, the middle layer containsthe power supplies and the bottom layer is used for the ground plane as well as componentplacement.
In order to minimize stray capacitance, no plane was present on the inverting input pins of anyamplifier or at the output. The OPA684, a current feedback amplifier with very low outputimpedance on its inverting pin, is very sensitive to stray capacitance on that node.
The figures 5.1 through 5.3 show the three layers of the board.
9
5 Circuit Implementation and Board Design
Figure 5.1: PCB - Top Layer
Figure 5.2: PCB - Mid Layer
PAC102
PAC101
COC1
PAC201
PAC202
COC2
PAC301
PAC302
COC3PAC402
PAC401
COC4
PAC502
PAC501COC5
PAC601
PAC602
COC6
PAC702
PAC701COC7
PAC801
PAC802
COC8
PAC902
PAC901
COC9
PAC1001
PAC1002
COC10
PAC1101
PAC1102
COC11
PAC1202
PAC1201
COC12
PAC1301PAC1302 COC13
PAC1402PAC1401
COC14
COHIGH GAIN
PAJ102PAJ101
PAJ103
COJ1
PAJ202PAJ201
PAJ203COJ2PAL102
PAL101COL1
PAL202PAL201COL2
PAL301PAL302
COL3PAL402
PAL401 COL4PAP102PAP101
PAP103COP1
PAR101
PAR102
COR1
PAR202PAR201
COR2PAR302
PAR301
COR3
PAR401
PAR402
COR4
PAR501
PAR502COR5 PAR602
PAR601COR6
PAR701
PAR702
COR7
PAR802
PAR801 COR8PAR901
PAR902
COR9
PAR1002
PAR1001
COR10PAR1101
PAR1102
COR11
PAR1202PAR1201
COR12
PAR1301
PAR1302
COR13PAU105
PAU103PAU104
PAU101PAU106
PAU102COU1
PAU205
PAU206
PAU207
PAU208
PAU204
PAU203
PAU202
PAU201COU2PAU305
PAU306
PAU307
PAU308
PAU304
PAU303
PAU302
PAU301COU3
PAC1002
PAC1301
PAL202
PAP103
PAU307
PAC1101
PAC1402
PAL402
PAP101
PAU304
PAC101
PAC202
PAC301
PAC401
PAC501
PAC601
PAC702
PAC801
PAC901
PAC1001
PAC1102
PAC1201
PAC1302PAC1401
PAJ101
PAJ103PAJ201
PAJ203
PAP102 PAR601PAR1001
PAR1102PAR1301PAC102
PAR101
PAC201PAL101
PAU106
PAC302PAL301
PAU102
PAC402
PAR402
PAC502PAR301
PAU203
PAC602
PAL102PAL201
PAU207
PAC701
PAL302
PAL401
PAU204
PAC802
PAR702
PAC902PAR901
PAU303PAC1202PAJ202
PAR1202PAJ102
PAR1302 PAU103PAR102
PAR202PAU104
PAR201PAR302
PAU101PAR401
PAR502PAU202
PAR501PAR902
PAU206
PAR602PAU208
PAR701PAR802
PAU302
PAR801PAR1101PAR1201
PAU306
PAR1002PAU308
Figure 5.3: PCB - Bottom Layer
PAC102
PAC101
COC1
PAC201
PAC202
COC2
PAC301
PAC302
COC3
PAC402
PAC401
COC4
PAC502
PAC501
COC5
PAC601
PAC602
COC6
PAC702
PAC701
COC7
PAC801
PAC802
COC8
PAC902
PAC901
COC9
PAC1001
PAC1002
COC10
PAC1101
PAC1102
COC11
PAC1202
PAC1201
COC12
PAC1301
PAC1302 CO
C13
PAC1402PAC1401
COC14
COHIGH GAIN
PAJ102
PAJ101
PAJ103
COJ1
PAJ202
PAJ201
PAJ203CO
J2
PAL102
PAL101CO
L1
PAL202
PAL201CO
L2
PAL301PAL302
COL3
PAL402
PAL401 CO
L4PAP102
PAP101
PAP103
COP1
PAR101
PAR102
COR1
PAR202PAR201
COR2
PAR302PAR301
COR3
PAR401 PAR4
02COR4
PAR501
PAR502COR
5 PAR602
PAR601
COR6
PAR701
PAR702
COR7
PAR802
PAR801COR8
PAR901
PAR902CO
R9
PAR1002
PAR1001
COR10PAR1
101PAR1102
COR11
PAR1202
PAR1201 CO
R12
PAR1301
PAR1302COR13
PAU105PAU103PAU104PAU101PAU106PAU102
COU1
PAU205
PAU206
PAU207
PAU208
PAU204
PAU203
PAU202
PAU201
COU2
PAU305
PAU306
PAU307
PAU308
PAU304
PAU303
PAU302
PAU301
COU3
PAC1002
PAC1301
PAL202
PAP103
PAU307
PAC1101
PAC1402
PAL402
PAP101
PAU304
PAC101
PAC202
PAC301
PAC401
PAC501
PAC601
PAC702
PAC801
PAC901
PAC1001
PAC1102
PAC1201
PAC1302
PAC1401
PAJ101
PAJ103
PAJ201
PAJ203
PAP102 PAR6
01
PAR1001
PAR1102
PAR1301
PAC102
PAR101
PAC201PAL101
PAU106PAC302
PAL301
PAU102
PAC402
PAR402
PAC502
PAR301
PAU203
PAC602
PAL102
PAL201
PAU207
PAC701
PAL302
PAL401
PAU204
PAC802
PAR702
PAC902
PAR901
PAU303
PAC1202PAJ202
PAR1202
PAJ102PAR1302PAU103PAR1
02 PAR202PAU104PAR201
PAR302
PAU101
PAR401
PAR502
PAU202
PAR501
PAR902
PAU206
PAR602
PAU208
PAR701
PAR802
PAU302
PAR801
PAR1101PAR1201
PAU306
PAR1002
PAU308
10
6 Evaluation
Evaluating the board required finding an arbitrary waveform generator (ARB) with sufficientlylow signal amplitude control and noise (please keep in mind the very high voltage gain of120,000 V/V). A suitable ARB could not be found in the lab. Therefore, a steep band-passfilter eighth order) was connected to the ARB followed by two 40-dB attenuation pads toachieve the desired 20 µVP P signal generation.
The output was evaluated using a standard oscilloscope. Averaging was used to extract thesignal from the noise floor. Figures 6.1 through 6.3 show the output signal for a 1, 5 and 10 MHzsine wave input, respectively. The input signal amplitude was 20 µVP P for all measurements.Looking at the 1MHz output signal plot, one can clearly see the distortion, whereas the 5 MHzand 10 MHz output plots look much cleaner. This can be explained by looking at the frequencyresponse (figure 6.5). For the 1 MHz signal, HD2 and HD3 are still within the flat band. For 5and 10 MHz, HD2 and HD3 are attenuated by the frequency response of the circuit and thusfiltered out.
Please also note that equipment limitations due to signal generation (ARB) as well as signalevaluation (scope, network analyser) were experienced during evaluation. Noise issues in com-bination with the 20 µVP P input signal and the very high gain (120,000 V/V) represented themain difficulty. Extracting the output signal from the noise floor presented a challenge to thescope’s ADC-s, especially in respect to resolution. Please take the amplitude values in the fol-lowing figures with a grain of salt. When it comes to amplitude values, the frequency responsemeasured by the network analyser should be more accurate (see figures 6.4 and 6.5). However,even though averaging was used on the network analyser too, noise was still an issue.
The frequency response was measured using a network analyser. Using its internal attenuator,it was possible to set the test signal amplitude to a suitable level (no clipping / compressionat the output). Figures 6.4 and 6.5 show the frequency response for 10 nF and 10 µF gainAC-coupling caps, respectively.
7 Conclusion
This design guide described the process and factors of developing a very high voltage gain,multi-stage design and explained its functionality and limitations. Knowing the importantfactors and the limitations, it should be possible to adjust this circuit to a given applicationwhile keeping in mind the limitations (especially the limited SNR).
11
7 Conclusion
Figure 6.1: Measured Output Signal, Sine Input, fIN = 1MHz, VIN = 20µVP P , CAC−GAIN =10µF
−1.5
−1
−0.5
0
0.5
1
1.5
Time (200ns/div)
VO
UT [V
]
NEW 1MHz 200mVpp 10uF
Figure 6.2: Measured Output Signal, Sine Input, fIN = 5MHz, VIN = 20µVP P , CAC−GAIN =10µF
−1.5
−1
−0.5
0
0.5
1
1.5
Time (50ns/div)
VO
UT [V
]
NEW 5MHz 200mVpp 10uF
Figure 6.3: Measured Output Signal, Sine Input, fIN = 10MHz, VIN = 20µVP P ,CAC−GAIN = 10µF
−1.5
−1
−0.5
0
0.5
1
1.5
Time (20ns/div)
VO
UT [V
]
NEW 10MHz 200mVpp 10uF
12
7 Conclusion
Figure 6.4: Measured Frequency Response, 10kHz-100MHz, CAC−GAIN = 10nF
104
105
106
107
108
10
20
30
40
50
60
70
80
90
100
Freq [Hz]
Gai
n [d
B]
Figure 6.5: Measured Frequency Response, 10kHz-100MHz, CAC−GAIN = 10µF
104
105
106
107
108
10
20
30
40
50
60
70
80
90
100
Freq [Hz]
Gai
n [d
B]
13
References
[TDK13] TDK: C1608X7R1E104K080AA 100 nF, 0603, Multi-layer Ceramic Chip Capacitor Datasheet. September 2013.http://product.tdk.com/capacitor/mlcc/en/documents/C1608X7R1E104K080AA.pdf.
14
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