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STT-RAM Circuit Design. Max I WRITE (Recap), MTJ Sharing Paper. Cell Sizing. Max I WRITE for I-STT (IBM65). I-STT MTJ Specs (Jianping). For 1ns switching: R P ≈ 500 Ω TMR ≈ 120% AP→P: 380-460 μ A P→AP: 600-800 μ A I WRITE(P→AP) /I WRITE(AP→P) : 1.5-2 I READ,MAX : - PowerPoint PPT Presentation
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STT-RAM Circuit Design
Max IWRITE (Recap),MTJ Sharing Paper
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Cell Sizing
Max IWRITE for I-STT (IBM65)
I-STT MTJ Specs (Jianping)
For 1ns switching:– RP ≈ 500Ω
– TMR ≈ 120%– AP→P: 380-460μA– P→AP: 600-800μA– IWRITE(P→AP)/IWRITE(AP→P): 1.5-2
IREAD,MAX:
– If both the read and write pulses are on the order of a few ns, then IREAD/IWRITE ≈ 2/3.
● We can share access transistors! (MAYBE)– Limiting factor in MTJ sharing is TMR degradation
3
Minimum Cell Size (NN Corner)
VBS = -0.25V
– Nominal● 37–45.5F2
– LVT● 33–40F2
VBS = 0.00V
– Nominal● 36–44F2
– LVT● 32.5–39.5F2
4
Maximum Write Currents
2 Cases:– VDD = 1V, WL = 1V
● Nominal voltages specified in documentation
– VDD & VWL is boosted (while keeping VDS, VGS < 1V)● Different VBL & VSL used to write “1” & “0”
● IWRITE(P→AP)/IWRITE(AP→P): 1.5-2
● Example:– VWL = 1.10V
– VBL<1> = 0.00V
– VSL<1> = 1.10V
– VBL<2> = 0.10V
– VSL<2> = 1.40V
– IWRITE: » AP→P = 335μA» P→AP = 670μA
5
RAP
WL<N>
SL<1>
BL<1>
IWRITE (AP→P)
RP
WL<N>
BL<2>
SL<2>
IWRITE (P→AP)
Simulation Results (P→AP)
MTJ Specs:– RP = 500Ω
– TMR = 120% IWRITE (P->AP) [μA]
NOMINAL VT– 25F2: VWL = 1.00V, VSL = 0.00V, VBL = 1.20V
– 35F2: VWL = 1.10V, VSL = 0.10V, VBL = 1.35V
– 50F2: VWL = 1.25V, VSL = 0.25V, VBL = 1.65V
LOW VT– 25F2: VWL = 1.00V, VSL = 0.00V, VBL = 1.20V
– 35F2: VWL = 1.10V, VSL = 0.10V, VBL = 1.40V
– 50F2: VWL = 1.30V, VSL = 0.30V, VBL = 1.80V 6
SL/BL = 1V WL = 1V SL/BL | (VDS < 1V) WL | (VGS < 1V)
NOMINAL VT LOW VT NOMINAL VT LOW VT SS NN FF SS NN FF SS NN FF SS NN FF
25F2 280.2 327.2 380.3 333.9 378.5 427.4 294.5 345.4 404.3 350.0 398.6 453.3
35F2 473.4 537.3 607.4 561.0 621.2 684.7 495.9 569.0 653.2 599.2 670.0 748.8
50F2 739.7 820.5 906.0 867.4 940.9 1015 787.8 894.1 1018 964.4 1068 1183
Simulation Results (AP→P)
MTJ Specs:– RP = 500Ω
– TMR = 120% IWRITE (AP->P) [μA]
NOMINAL VT– 25F2: VWL = 1.00V, VSL = 1.00V, VBL = 0.00V
– 35F2: VWL = 1.10V, VSL = 1.10V, VBL = 0.00V
– 50F2: VWL = 1.25V, VSL = 1.25V, VBL = 0.00V
LOW VT– 25F2: VWL = 1.00V, VSL = 1.00V, VBL = 0.00V
– 35F2: VWL = 1.10V, VSL = 1.10V, VBL = 0.00V
– 50F2: VWL = 1.30V, VSL = 1.30V, VBL = 0.00V 7
SL/BL = 1V WL = 1V SL/BL | (VDS < 1V) WL | (VGS < 1V)
NOMINAL VT LOW VT NOMINAL VT LOW VT SS NN FF SS NN FF SS NN FF SS NN FF
25F2 164.3 187.1 212.7 197.8 219.8 243.2 164.3 187.1 212.7 197.8 219.8 243.2
35F2 217.1 240.8 267.3 260.6 283.4 307.1 263.5 289.2 318.2 308.7 333.2 358.9
50F2 264 287.9 315.2 315.2 338.0 361.9 402.6 431.2 464.5 488.5 515.9 545.2
Summary
Maximum IWRITE (LVT, FF) (P→AP) :
– 25F2: 453.3μA– 35F2: 748.8μA– 50F2: 1183μA
Maximum IWRITE (LVT, FF) (AP→P) :
– 25F2: 243.2μA– 35F2: 358.9μA– 50F2: 545.2μA
35F2 LVT cell almost meets I-STT specs for 1ns switching– AP→P current a little weak (can be adjusted a little higher)– 38-40F2 LVT cell w/ boosted voltages can safely meet
Jianping’s spec for 1ns switching8
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MTJ Sharing
TMR Degradation(Reading)
TMR Degradation
Parallel Resistance (R||)
degrades TMR
10
MTJ1,1
WL<1>
MTJ1,2
MTJ1,M
SL
BL<1>
BL<2>
BL<M>
MTJ2,1
WL<2>
MTJ2,2
MTJ2,M
MTJN,1
WL<N>
MTJN,2
MTJN,M
Parasitic Parallel Resistance
||
1, all P
1 1
11 , all AP
1 1
P
P
N MR
N MR
N MTMR R
N M
Effective RP and RAP
Worst case TMR’: largest RP’ and smallest RAP’
Largest RP’:
Smallest RAP’
11
||
1 1' || || 1 1
1 1 1P P P P P
N M N MR R R R TMR R TMR R
N M NM N M TMR
||
1 1' || 1 || 1
1 1 1 1AP AP P P P
N M N MR R R TMR R R TMR R
N M NM N M TMR
Effective TMR (1)
Putting it all together:
Example 1kbit Arrays: TMR = 120%, M = 2, N = 16, 32-bit words: TMR’ = 4.8% TMR = 120%, M = 2, N = 8, 64-bit words: TMR’ = 9.8% TMR = 120%, M = 2, N = 4, 128-bit words: TMR’ =
20.7%12
' ''
'
1 11 1
1 1 11
11
2 1
1 1
AP P
P
P P
P
R RTMR
R
N M N MTMR R TMR R
NM N M TMR NM N M TMRN M
TMR RNM N M TMR
N M NMTMR
NM N M TMR
TMR’ vs. N for 1T-2MTJ (M = 2)
13
2 4 6 8 10 12 14 160
10
20
30
40
50
60
70T
MR
[%
]
N
TMR = 50%TMR = 100%TMR = 150%TMR = 200%
TMR’ vs. N for 1T-3MTJ (M = 3)
14
2 4 6 8 10 12 14 16-30
-20
-10
0
10
20
30
40T
MR
[%
]
N
TMR = 50%TMR = 100%TMR = 150%TMR = 200%
Monte Carlo Simulations (1)
Limited to M = 2
Theoretical TMR’ is overly pessimistic– With error correction we
can let the extreme cases fail.
– Example:● Bit read error = 0.1%● Word length = 64● # error correcting bits = 4● Probability of a word error:
1 in 137,763,712 reads
M = 2, N = 4 TMR = 120%, RP = 500Ω 25k Simulations Worst Case TMR’
– Theoretical = 20.7%– Simulation = 46.2%
15
300 400 500 600 700 800 900 10000
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Resistance [ ]
PR
OB
RP
RAP
Monte Carlo Simulations (2)
M = 2, N = 8 TMR = 120%, RP = 500Ω 25k Simulations Worst Case TMR’
– Theoretical = 9.8%– Simulation = 20.7%
M = 2, N = 16 TMR = 120%, RP = 500Ω 25k Simulations Worst Case TMR’
– Theoretical = 4.8%– Simulation = 10.1%
16
250 300 350 400 450 500 550 600 650 700 7500
0.05
0.1
0.15
0.2
0.25
Resistance [ ]
PR
OB
RP
RAP
250 300 350 400 450 500 550 600 6500
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
Resistance [ ]
PR
OB
RP
RAP
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MTJ Sharing
Device IREAD/IWRITE Requirements(Writing)
Defining IREAD,MAX & IWRITE,MIN
IREAD,MAX: The maximum read current such that the probability of flipping the MTJ is less than some ε (i.e. ε = 0.1% → IREAD,MAX = 200μA)
IWRITE,MIN: The minimum write current such that the probability of failing to flip the MTJ is less than some ξ (i.e. ξ = 0.1% → IWRITE,MIN = 600μA)
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0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
PR
OB
(WR
ITE
)
IWRITE
,READ AP P MAXI
,WRITE AP P MINI
,READ P AP MAXI
,WRITE P AP MINI
IREAD/IWRITE for 1T-2MTJ (1)
Limited to 1T-2MTJ architecture
19
WL<1> WL<2>
BL<1>
BL<2>
IWRITE,MIN
α∙IREAD,MAX
, ,
, ,
READ P AP MAX WRITE P AP MIN
READ AP P MAX WRITE AP P MIN
I I
I I
IREAD/IWRITE for 1T-2MTJ (2)
RP Case 1: RAP Case 1:
RP Case 2: RAP Case 2:
20
“1” “0”RP RP
RP RP
“1” “0”RAP RP
RAP RP
“1” “0”RAP RAP
RAP RP
“1” “0”RP RP
RP RAP
, , ,
,
,
2
12
P P PWRITE MIN P AP READ MAX P AP READ MAX P AP
READ MAX P AP
WRITE MIN P AP
R I R I R I
I
I
, , , ,
, , , ,
,
,
1
1
11
1
P WRITE MIN P AP P READ MAX P AP P READ MAX P AP P READ MAX AP P
P WRITE MIN P AP P READ MAX P AP P READ MAX P AP P READ MAX P AP
READ MAX P AP
WRITE MIN P AP
R I R I R I R TMR I
TMRR I R I R I R I
I
I TMR
, , , ,
, , , ,
,
,
1 1 1
1 1 1
1
1
P WRITE MIN AP P P READ MAX AP P P READ MAX P AP P READ MAX AP P
P WRITE MIN AP P P READ MAX AP P P READ MAX AP P P READ MAX AP P
READ MAX P AP
WRITE MIN P AP
R TMR I R TMR I R I R TMR I
R TMR I R TMR I R I R TMR I
I
I
1
TMR
, , ,
, , ,
,
,
1 1 2
1 1 2
1
21
P WRITE MIN AP P P READ MAX AP P P READ MAX P AP
P WRITE MIN AP P P READ MAX AP P P READ MAX AP P
READ MAX P AP
WRITE MIN P AP
R TMR I R TMR I R I
R TMR I R TMR I R I
I
ITMR
IREAD/IWRITE vs. TMR
21
0 50 100 150 200 2500.25
0.3
0.35
0.4
0.45
0.5
0.55
I RE
AD/I W
RIT
E
TMR [%]
= 1.5 (P AP) = 1.5 (AP P) = 2.0 (P AP) = 2.0 (AP P)
SUMMARY
Cell Sizing: 35-40F2
TMR Degradation: M = 2 (READING)– Word length should be greater than 64– Serious TMR degradation for N > 8– Ideally:
● RP = 500Ω, TMR = 120%
– M = 2, N = 4 → 1kbit arrays of 128-bit words– TMR’ = 20.7%
» Reality: TMR’ ≈ 45% (ignoring worst case)
– Need less than 8 error correcting bits
IREAD/IWRITE (WRITING)
– For TMR = 120%, χ = 1.5-2: IREAD/IWRITE > 0.36-0.43
22
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