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Spartan-II™ 200 PCI Development Board
User’s Guide
Version 1.0
April 2002
PN# DS-MANUAL-SPARTANII-200PCI
Spartan-II 200 PCI Development Kit Owners Certificate Thank you for purchasing the Spartan-II 200 PCI Development Kit. As an owner of this kit, you can register for access to the Reference Design Center. In the Reference Design Center, you may download reference design examples for the Spartan-II 200 PCI kit, along with source code, and application notes. As more reference designs are added, you will be notified via e-mail. Visit the Reference Design Center today at:
www.insight-electronics.com/solutions/reference/xilinx Your kit serial number is: For technical assistance, find the location of your nearest Memec office at: http://www.insight-electronics.com and select “Locations” or send an e-mail to : rdc@ins.memec.com
WARRANTY AND LIABILITY DISCLAIMER
Notwithstanding any additional, different or conflicting terms or conditions contained in the purchaser’s ordering document or other document, to the maximum extent permitted by applicable law, Memec, LLC and its subsidiaries (“Insight” and “Impact”) expressly disclaim all warranties, conditions, or representations, express, implied, statutory or otherwise, regarding this product or any other services provided by Memec in connection with this product, all of which are provided “as is”, and this disclaimer shall apply to any implied warranties or conditions of merchantability, satisfactory or merchantable quality and fitness for a particular purpose, or those arising from a course of dealing or usage of trade.
Under no circumstances (to the maximum extent permitted by applicable law), shall Memec be liable to the purchaser or to any third party, for a claim of any kind arising as a result of, or related to the product, whether in contract, in tort (including negligence or strict liability), under any warranty, or otherwise. This limitation of liability shall apply notwithstanding the fact that a claim brought by the purchaser or any third party is for indirect, special or consequential damages (including lost profits), even if Memec has been advised of the possibility of such damages, or for warranties granted by the purchaser to any third party.
The purchaser acknowledges and agrees that the price for this product is based in part upon these limitations, and further agrees that these limitations shall apply notwithstanding any failure of essential purpose of any limited remedy.
April 1, 2002 i
Table of Contents
1 OVERVIEW ....................................................................................................................1
2 THE SPARTAN-II DEVELOPMENT BOARD ...................................................................1 3 SPARTAN-II DEVELOPMENT BOARD FEATURES ........................................................2
3.1 SDRAM MEMORY ....................................................................................................2
3.2 CLOCK GENERATION .................................................................................................4 3.3 RESET CIRCUIT ........................................................................................................4 3.4 USER 7-SEGMENT DISPLAY........................................................................................5
3.4.1 7-Segment Display Signal Description..................................................................5 3.5 USER LED...............................................................................................................6 3.6 USER PUSH BUTTON SWITCH (SW5) ...........................................................................6
3.6.1 User Push Button Switch Signal Assignment ........................................................6 3.7 PROGRAM SWITCH (SW2) .........................................................................................6 3.8 USER DIP SWITCH (SW4) .........................................................................................6
3.8.1 User DIP Switch Interface ...................................................................................7 3.8.2 User DIP Switch Signal Assignments ...................................................................7
3.9 RS232 PORT...........................................................................................................7
3.9.1 RS232 Interface..................................................................................................7 3.9.2 RS232 Signal Descriptions ..................................................................................8
3.10 JTAG PORT ............................................................................................................8
3.10.1 JTAG Connector .............................................................................................8 3.10.2 JTAG Signal Descriptions ................................................................................8 3.10.3 JTAG Chain ...................................................................................................9 3.10.4 JTAG Chain Jumper Settings ..........................................................................9
3.11 SLAVE PARALLEL/SLAVE SERIAL PORT.......................................................................10 3.11.1 Slave Parallel ...............................................................................................10
3.12 SLAVE SERIAL PORT ...............................................................................................11
3.13 BANK I/O VOLTAGE.................................................................................................11 3.13.1 Bank I/O Voltage Jumper Settings .................................................................11
3.14 ISP PROM ...........................................................................................................12
3.15 PCI INTERFACE......................................................................................................12 3.15.1 PCI Interface Signal Descriptions ...................................................................12
3.16 VOLTAGE REGULATORS ...........................................................................................14
3.16.1 Voltage Regulators Jumper Settings ..............................................................14 3.17 SPARTAN-II CONFIGURATION MODE SELECT...............................................................14
April 1, 2002 ii
3.18 P160 EXPANSION MODULE ......................................................................................15 3.18.1 Expansion Module Signal Assignments ..........................................................15
4 DESIGN DOWNLOAD..................................................................................................18 4.1 JTAG INTERFACE...................................................................................................18
4.1.1 Configuring the Spartan-II FPGA .......................................................................18 4.1.2 Programming the XC18V02 ISP PROM..............................................................18
4.2 SLAVE SERIAL INTERFACE........................................................................................19 4.3 SLAVE PARALLEL ....................................................................................................19
REVISION HISTORY............................................................................................................20 APPENDIX A - SPARTAN-II 200 PCI BOARD SCHEMATICS ...............................................21
April 1, 2002 iii
Figures
FIGURE 1 – SPARTAN-II DEVELOPMENT BOARD.............................................................................1 FIGURE 2 - SPARTAN-II 200 PCI DEVELOPMENT BOARD BLOCK DIAGRAM ........................................2 FIGURE 3 – SDRAM INTERFACE.................................................................................................3 FIGURE 4 – RESET CIRCUIT .......................................................................................................5 FIGURE 5 - 7-SEGMENT LED DISPLAY INTERFACE .........................................................................5 FIGURE 6 – USER DIP SWITCH INTERFACE...................................................................................7 FIGURE 7 – RS232 INTERFACE ..................................................................................................8 FIGURE 8 – JTAG CONNECTOR..................................................................................................8 FIGURE 9 – SPARTAN-II DEVELOPMENT BOARD JTAG CHAIN..........................................................9 FIGURE 10 – SLAVE PARALLEL/SLAVE SERIAL CONNECTOR ..........................................................10 FIGURE 11 – SLAVE PARALLEL MODE CONFIGURATION ................................................................10 FIGURE 12 – SLAVE SERIAL MODE CONFIGURATION ....................................................................11 FIGURE 13 – ISP PROM INTERFACE ........................................................................................12 FIGURE 14 – SPARTAN-II DEVELOPMENT BOARD VOLTAGE REGULATORS .......................................14 FIGURE 15 – DOWNLOAD SETUP...............................................................................................18
April 1, 2002 iv
Tables TABLE 1 – SDRAM INTERFACE S IGNAL DESCRIPTION ....................................................................3 TABLE 2 - SPARTAN-II DEVELOPMENT BOARD MASTER CLOCKS ......................................................4 TABLE 3 - 7-SEGMENT DISPLAY SIGNAL DESCRIPTIONS ..................................................................6 TABLE 4 - USER PUSH BUTTON SWITCH S IGNAL ASSIGNMENTS .......................................................6 TABLE 5 - USER DIP SWITCH S IGNAL ASSIGNMENTS......................................................................7 TABLE 6 - RS232 S IGNAL DESCRIPTIONS .....................................................................................8 TABLE 7 - JTAG SIGNAL DESCRIPTIONS ......................................................................................9 TABLE 8 - JTAG CHAIN JUMPER SETTINGS ..................................................................................9 TABLE 9 - BANK I/O VOLTAGE JUMPER SETTINGS ........................................................................11 TABLE 10 – PCI INTERFACE S IGNAL DESCRIPTIONS .....................................................................12 TABLE 11 - VOLTAGE REGULATORS JUMPER SETTINGS ................................................................14 TABLE 12 - SPARTAN-II CONFIGURATION MODE SELECT...............................................................15 TABLE 13 – JX1 USER I/O CONNECTOR ....................................................................................16 TABLE 14 – JX2 USER I/O CONNECTOR ....................................................................................17
April 1, 2002 1
1 Overview
The Spartan-II 200 PCI Development Kit provides a complete solution for developing designs and applications based on the Xilinx Spartan-II FPGA family. The kit bundles an expandable Spartan-II based system board with a power supply, user guide and reference designs. Also available from Memec Design, optional P160 expansion modules enable further application specific prototyping and testing. Xilinx ISE software and a JTAG cable are available as kit options. The Spartan-II system board utilizes the 200,000 gate Xilinx Spartan-II device (XC2S200-6FG456C) in the 456 fine-pitch ball grid array package. The high gate density and large number of user I/Os allows complete system solutions to be implemented in the low cost FPGA. The system board includes two clock sources, a 32-bit PCI edge connector, 8MB SDRAM memory, an RS-232 port, LED displays, switches and additional user support circuits. The board supports the Memec Design P160 expansion module standard, which allows application-specific expansion modules to be easily added. The Spartan-II FPGA family has the advanced features needed to fit the most demanding, high volume applications. The Spartan-II 200 PCI Development Kit provides an excellent platform to explore these features so that you can quickly and effectively meet your time-to-market requirements.
2 The Spartan-II Development Board
The Spartan-II Development Board provides the FPGA, PCI edge connector, support circuits and the P160 expansion slot for a complete system-level design. Figure 1 shows a picture of the board and its features.
Figure 1 – Spartan-II Development Board
April 1, 2002 2
3 Spartan-II Development Board Features
A high-level block diagram of the Spartan-II 200 PCI development board is shown in Figure 2 followed by a brief description of each sub-section.
3.3VRegulator
2.5VRegulator
User7-SegmentDisplay (2)
RS232Port
JTAG Port
ISP PROM(XC18V02)
UserSwitches
UserLEDs
SlaveSerial/Slave Parallel
Clock Generator(100 & 24Mhz)
Spartan-II FPGAXC2S200(FG456)
ResetCircuit
80-P
in C
on
nec
tor
80-P
in C
on
nec
tor
P160 Module
32-bitPCI Interface Voltage
Regulators
SDRAM2Mx32
Figure 2 - Spartan-II 200 PCI Development Board Block Diagram
3.1 SDRAM Memory The Spartan-II 200 PCI development board provides 8MB of SDRAM memory. This memory is implemented using the Toshiba TC59S6432CFT 2Mx32 SDRAM (or a compatible) device. A high-level block diagram of the SDRAM interface is shown below followed by a table describing the SDRAM memory interface signals.
April 1, 2002 3
Spartan-IIFPGA
2M x 32 SDRAM(TC59S6432CFT)
Addr[10:0]
Data[31:0]
BS[1:0]
DQM[3:0]
CSn
RASn
CASn
WEn
CLK
CLKE
OSC100Mhz
clk_in
reset
Figure 3 – SDRAM Interface
Table 1 – SDRAM Interface Signal Description
Signal Name Description FPGA Pin # SDRAM Pin # A0 Address 0 M18 25 A1 Address 1 L18 26 A2 Address 2 L20 27 A3 Address 3 J21 60 A4 Address 4 J22 61 A5 Address 5 K21 62 A6 Address 6 K22 63 A7 Address 7 L21 64 A8 Address 8 L22 65 A9 Address 9 M22 66 A10 Address 10 M19 24 DQ0 Data 0 T18 2 DQ1 Data 1 W22 4 DQ2 Data 2 R18 5 DQ3 Data 3 P18 7 DQ4 Data 4 V20 8 DQ5 Data 5 U19 10 DQ6 Data 6 U20 11 DQ7 Data 7 T19 13 DQ8 Data 8 P22 74 DQ9 Data 9 P21 76 DQ10 Data 10 R22 77 DQ11 Data 11 T21 79 DQ12 Data 12 U22 80 DQ13 Data 13 U21 82 DQ14 Data 14 V22 83 DQ15 Data 15 V21 85
April 1, 2002 4
DQ16 Data 16 J20 31 DQ17 Data 17 J19 33 DQ18 Data 18 H19 34 DQ19 Data 19 G20 36 DQ20 Data 20 G19 37 DQ21 Data 21 F20 39 DQ22 Data 22 F19 40 DQ23 Data 23 E20 42 DQ24 Data 24 C22 45 DQ25 Data 25 D21 47 DQ26 Data 26 D22 48 DQ27 Data 27 E21 50 DQ28 Data 28 E22 51 DQ29 Data 29 F21 53 DQ30 Data 30 F22 54 DQ31 Data 31 G21 56 BS0 Bank Select 0 N20 22 BS1 Bank Select 1 M20 23 DQM0 Write Mask T20 16 DQM1 Write Mask N21 71 DQM2 Write Mask K19 28 DQM3 Write Mask H21 59 CSn Chip Select N19 20 RASn Row Address Strobe P20 19 CASn Column Address Strobe P19 18 WEn Write Enable R19 17 CLK Clock N18 68 CKE Clock Enable N22 67
3.2 Clock Generation The Spartan-II development board provides three master clock inputs to the Spartan-II FPGA. The following table provides a brief description of these clock signals.
Table 2 - Spartan-II Development Board Master Clocks Signal Name Spartan-II Pin # Direction Description CLK.CAN2 Y11 Input On-board 100 MHz Oscillator CLK.CAN1 W12 Input On-board 24 MHz Oscillator User Clock A11 Input User Clock Input via JP30 The Spartan-II development board provides two on-board oscillators running at 100Mhz (CLK.CAN1) and 24Mhz (CLK.CAN2). The 100Mhz oscillator is enabled when the JP24 jumper is open, while leaving the JP32 jumper open will enable the 24Mhz oscillator. In addition to these oscillators, a jumper is provides (JP30) for a User supplied clock input to the FPGA. JP30 is provided as an external clock input jumper, connecting to the global clock pin on A11 of the FPGA. Pin 1 of JP30 connects to A11 and pin 2 of JP30 connects to ground. The PCI clock from the PCI edge connector connects to the global clock pin on C11 of the FPGA.
3.3 Reset Circuit The Spartan-II development board uses the TI TPS3125 voltage supervisory device to monitor the Spartan-II FPGA core voltage (2.5V). This circuit asserts a reset signal (RESETn_FPGA, Pin
April 1, 2002 5
B10) to the Spartan-II device when the 2.5V core voltage falls below its minimum specifications (V). The reset signal to the FPGA is a fixed 100ms active low pulse. In addition to monitoring the core voltage, this circuit can be used to generate a reset pulse by activating the Master Reset (MRn) signal to the TPS3125 device via the on-board push-button switch (SW3). The following figure shows the reset circuit on the Spartan-II development board.
SW3
RESETn
MRn
VDD
TPS3125
FPGA_RESETn
2.5V
Figure 4 – Reset Circuit
3.4 User 7-Segment Display The Spartan-II development board utilizes two common-cathode 7-segment LED displays that can be used during the test and debugging phase of a design. The user can turn a given segment on by driving the associated signal high. The following figure shows the user 7-segment display interface to the Spartan-II FPGA.
A1
B 1
C 1
D 1
E1
F 1G1
A2
B 2
C 2
D 2
E2
F 2G2
DISPLAY.1F
DISPLAY.1G
DISPLAY.1E
DISPLAY.1D
DISPLAY.1C
DISPLAY.1B
DISPLAY.1A
DISPLAY.2F
DISPLAY.2G
DISPLAY.2E
DISPLAY.2D
DISPLAY.2C
DISPLAY.2B
DISPLAY.2A
Figure 5 - 7-Segment LED Display Interface
3.4.1 7-Segment Display Signal Description The following table shows the 7-Segment LED display pin descriptions.
April 1, 2002 6
Table 3 - 7-Segment Display Signal Descriptions
Signal Name Spartan-II Pin # Description DISPLAY.1A E10 7-Segment LED Display1, Segment A DISPLAY.1B E9 7-Segment LED Display1, Segment B DISPLAY.1C E8 7-Segment LED Display1, Segment C DISPLAY.1D E6 7-Segment LED Display1, Segment D DISPLAY.1E E7 7-Segment LED Display1, Segment E DISPLAY.1F F11 7-Segment LED Display1, Segment F DISPLAY.1G E11 7-Segment LED Display1, Segment G DISPLAY.2A D6 7-Segment LED Display2, Segment A DISPLAY.2B C5 7-Segment LED Display2, Segment B DISPLAY.2C D5 7-Segment LED Display2, Segment C DISPLAY.2D C7 7-Segment LED Display2, Segment D DISPLAY.2E D7 7-Segment LED Display2, Segment E DISPLAY.2F C6 7-Segment LED Display2, Segment F DISPLAY.2G A8 7-Segment LED Display2, Segment G
3.5 User LED The Spartan-II development board provides a single user LED. Pin A10 of the Spartan-II FPGA is used to drive this active low signal.
3.6 User Push Button Switch (SW5)
The Spartan-II development board design provides a user push button switch input to the Spartan-II FPGA. The push button switch can be used to generate an active low signal.
3.6.1 User Push Button Switch Signal Assignment
The following table shows the pin assignment for the user push button switch.
Table 4 - User Push Button Switch Signal Assignments
Signal Name Spartan-II Pin # Description PUSH.USER1 B1 User Push Button Switch Input 1 (SW5)
3.7 Program Switch (SW2)
The Spartan-II development board provides a push button switch for initiating the configuration of the Spartan-II FPGA. This switch is used when the XC18V02 ISP PROM configures the Spartan-II FPGA. After programming of the XC18V02 ISP PROM, this switch can assert the PROGn signal. Upon activation of the PROGn signal, the XC18V02 ISP PROM initiates the configuration of the Spartan-II FPGA.
3.8 User DIP Switch (SW4) The Spartan-II development board provides 8 user switch inputs. These switches can be statically set to a low or high logic level.
April 1, 2002 7
3.8.1 User DIP Switch Interface The following figure shows the user DIP Switch interface to the Spartan-II FPGA.
54321
678
1213141516
1110
9
S W 4Swi tch
DIP8
DIP7
DIP6
DIP5
DIP4
DIP3
DIP2
DIP1
Figure 6 – User DIP Switch Interface
3.8.2 User DIP Switch Signal Assignments The following table shows the user switch pin assignments.
Table 5 - User DIP Switch Signal Assignments
Signal Name Spartan-II Pin # Description DIP8 E4 User Switch Input 8 DIP7 F3 User Switch Input 7 DIP6 E3 User Switch Input 6 DIP5 F5 User Switch Input 5 DIP4 G5 User Switch Input 4 DIP3 F4 User Switch Input 3 DIP2 C1 User Switch Input 2 DIP1 D2 User Switch Input 1
3.9 RS232 Port
The Spartan-II development board provides an RS232 port that can be driven by the Spartan-II FPGA. A subset of the RS232 signals is used on the Spartan-II development board to implement this interface (RD and TD signals).
3.9.1 RS232 Interface The Spartan-II development board provides a DB-9 connection for a simple RS232 port. This board utilizes the TI MAX3221 RS232 driver for driving the RD and TD signals. The user provides the RS232 UART code, which resides in the Spartan-II FPGA.
April 1, 2002 8
RS232Drivers
MAX3221
RXD
TXD
RD
TD
2
3
JDR1Connector
Rout
Din
Rin
Dout
Figure 7 – RS232 Interface
3.9.2 RS232 Signal Descriptions The following table shows the RS232 signals and their pin assignments to the Spartan-II FPGA.
Table 6 - RS232 Signal Descriptions
Signal Name Spartan-II Pin # Description RXD B9 Received Data, RD TXD A9 Transmit Data, TD
3.10 JTAG Port The Spartan-II development board design provides a JTAG port that can be used to configure and/or program various devices on the board and JTAG devices located on the P160 module.
3.10.1 JTAG Connector The Spartan-II development board provides a JTAG connector that can be used to program the on-board ISP PROM, configure the Spartan-II FPGA, and program and/or configure JTAG devices located on the P160 module. The following figure shows the pin assignments for the JTAG connector on the Spartan-II development board.
3.3VGND
T C KTDOTDIT M S
J2J T A G
C o n n e c t o r
12
4
67
3
5
Figure 8 – JTAG Connector
3.10.2 JTAG Signal Descriptions The following table provides a brief description of the JTAG signals and their pin assignments to the Spartan-II FPGA.
April 1, 2002 9
Table 7 - JTAG Signal Descriptions
Signal Name Description TDI JTAG Data Input TCK JTAG Clock Input TMS JTAG Test Mode Input TDO JTAG Data Output
3.10.3 JTAG Chain The following figure shows the JTAG chain on the Spartan-II development board. If any of the devices in the chain are not populated, its associated jumper must be closed in order to maintain the chain integrity. If the P160 module is not present, then jumper JP25 must be closed in order to connect the P160 module TDI pin to its TDO pin.
XC18V02ISP
PROM
Spartan-IIFPGA
P160ModuleTDI T D O T D OTDI TDI
JP22
TDI
T D O
Jumper
T D O
JP17
Jumper
T M S
TCK
T M S
TCK
T M S T M S
TCK TCK
JP25
Jumper
Figure 9 – Spartan-II Development Board JTAG Chain
3.10.4 JTAG Chain Jumper Settings The following table shows the JTAG chain jumper setting on the Spartan-II development board.
Table 8 - JTAG Chain Jumper Settings
Jumper Setting Description Open XC18V02 ISP PROM is present JP22
Closed XC18V02 ISP PROM is not present Open Spartan-II FPGA is present JP17
Closed Spartan-II FPGA is not present Open P160 module is present JP25
Closed P160 module is not present
April 1, 2002 10
3.11 Slave Parallel/Slave Serial Port In addition to the JTAG mode, the Spartan-II FPGA on the Spartan-II development board can be configured using the Slave Serial or the Slave Parallel mode of configuration. The following figure shows the connector pin assignments for the Slave Serial/Slave Parallel port.
C C L K
D O N E
CSn
INITn
J3Slave Parallel/Slave Serial
Connector
1 2
4
6
7
9
3
5
8
11
13
15
10
12
14
16
PROGRAMn
R D / W n
DOUT/BUSY
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
Figure 10 – Slave Parallel/Slave Serial Connector
3.11.1 Slave Parallel In the Slave Parallel configuration mode, a byte of configuration data is loaded into the Spartan-II FPGA during each CCLK clock cycle. In this mode, an external source drives the CCLK clock and the data bus containing the configuration data. The following figure shows the Slave Parallel configuration mode interface to the Spartan-II FPGA. The JP12 jumper must be installed in position 1-2 for this mode of configuration.
Spartan-IIFPGA
CCLK
DONE
CSn
INITn
PROGRAMn
RD/Wn
DOUT/BUSY
D[0:7]D[0:7]
DONE
CCLK
INIT_B
PROG_B
RDWR_B
BUSY
CS_B
Figure 11 – Slave Parallel Mode Configuration
April 1, 2002 11
3.12 Slave Serial Port In the Slave Serial configuration mode, a bit of configuration data is loaded into the FPGA during each CCLK clock cycle. In this mode, an external source places the most significant bit of each byte on the DIN pin first and then drives the CCLK clock to store data into the FPGA. The following figure shows the Slave Serial configuration mode interface to the Spartan-II FPGA. The JP12 jumper must be installed in position 1-2 for this mode of configuration.
S p a r t a n - I I E
F P G A
C C L K
D O N E
I N I T n
P R O G R A M n
D 0DIN
D O N E
C C L K
IN IT_B
P R O G _ B
Figure 12 – Slave Serial Mode Configuration
3.13 Bank I/O Voltage The Spartan-II development board allows the Spartan-II I/O pins to be configured for 2.5V or 3.3V operation. All Spartan-II user I/O pins are grouped in 8 different banks. Each bank of I/O pins on the board can be configured to operate in the 2.5V or the 3.3V mode.
3.13.1 Bank I/O Voltage Jumper Settings
The following table shows the jumper settings for the Spartan-II bank I/O voltage (VCCO) selection. Each bank can be set to 2.5V or 3.3V.
Table 9 - Bank I/O Voltage Jumper Settings
Bank # Jumper I/O Voltage
JP35 1-2 2-3
Closed Open 3.3V
0 Open Closed 2.5V
JP26 1-2 2-3
Closed Open 3.3V
1 Open Closed 2.5V 2 FIXED 3.3V 3 FIXED 3.3V
JP19 1-2 2-3
Closed Open 3.3V
4 Open Closed 2.5V
JP34 1-2 2-3
Closed Open 3.3V
5 Open Closed 2.5V 6 FIXED 3.3V 7 FIXED 3.3V
April 1, 2002 12
3.14 ISP PROM The Spartan-II development board utilizes the Xilinx XC18V02 ISP PROM, allowing FPGA designers to quickly download revisions of a design and verify the design changes in order to meet the final system-level design requirements. The XC18V02 ISP PROM uses two interfaces to accomplish the configuration of the Spartan-II FPGA. The JTAG port on the XC18V02 device is used to program the PROM with the design bit file. Once the XC18V02 has been programmed, the user can configure the Spartan-II device in the Master Serial mode. The configuration of the Spartan-II device is initiated by asserting the PROGn signal. Upon activation of the PROGn signal (by pressing the SW2 switch), the XC18V02 device will use its FPGA Configuration Port to configure the Spartan-II FPGA.
CCLK
DONE
INIT_B
PROG_B
D0
CF
CE
RESET/OE
CCLK
D0
Spartan-II FPGAXC18V02 ISP PROM
TDI
TMS
TCK
TDO
JTAGPort
Figure 13 – ISP PROM Interface
3.15 PCI Interface The Spartan-II 200 PCI development board provides a 32-bit PCI interface edge connector for prototyping PCI-based designs. The Xilinx PCI32 core can be used to implement this interface.
3.15.1 PCI Interface Signal Descriptions The following table shows the PCI interface signals and their assignments to the Spartan-II FPGA.
Table 10 – PCI Interface Signal Descriptions
FPGA Pin # JE1 Signal
Name
JE1 Pin # JE1 Signal
Name FPGA Pin #
A1 B1 -12V +12V A2 B2 A3 B3 GND TDI A4 B4 TDO +5V A5 B5 +5V
M3 INITAn A6 B6 +5V A7 B7
April 1, 2002 13
+5V A8 B8 A9 B9 A10 B10 A11 B11 A12 B12 A13 B13 A14 B14
E2 RSTn A15 B15 GND A16 B16 PCI.CLK C11
L5 GNTn A17 B17 GND GND A18 B18 REQn K2 A19 B19
G4 AD30 A20 B20 AD31 E1 A21 B21 AD29 G3
H5 AD28 A22 B22 GND F1 AD26 A23 B23 AD27 F2
GND A24 B24 AD25 H4 G1 AD24 A25 B25 L6 IDSEL A26 B26 C/BE3n N2
A27 B27 AD23 H3 H2 AD22 A28 B28 GND H1 AD20 A29 B29 AD21 J4
GND A30 B30 AD19 J5 J2 AD18 A31 B31 J1 AD16 A32 B32 AD17 J3 A33 B33 C/BE2n N3
M6 FRAMEn A34 B34 GND GND A35 B35 IRDYn L3
M1 TRDYn A36 B36 GND A37 B37 DEVSELn L1
L4 STOPn A38 B38 GND A39 B39 A40 B40 PERRn N5 A41 B41 GND A42 B42 SERRn M4
P2 PAR A43 B43 K5 AD15 A44 B44 C/BE1n N4
A45 B45 AD14 K1 K3 AD13 A46 B46 GND P4 AD11 A47 B47 AD12 K4
GND A48 B48 AD10 R1 P5 AD09 A49 B49 GND
A50 B50 A51 B51
P1 C/BE0n A52 B52 AD08 P3 A53 B53 AD07 R2
T1 AD06 A54 B54 T2 AD04 A55 B55 AD05 R4
GND A56 B56 AD03 U1 R5 AD02 A57 B57 GND T5 AD00 A58 B58 AD01 V1
A59 B59 A60 B60 +5V A61 B61 +5V +5V A62 B62 +5V
April 1, 2002 14
3.16 Voltage Regulators The following figure shows the voltage regulators that are used on the Spartan-II development board to provide various on-board voltage sources. As shown in the figure, JP1 connector is used to provide the main 5.0V voltage to the board. This voltage source is provided to all on-board regulators to generate the 2.5V, and 3.3V voltages.
JP9Jumper
JP6Jumper
3.3V 2.5V
JP102.5V
Connector
JP73.3V
Connector
JP15.0V
Connector
3.3VReg
2.5VReg
Figure 14 – Spartan-II Development Board Voltage Regulators
For any one of the on-board voltages (2.5V, and 3.3V), if the current provided by the on-board regulator is not sufficient for some applications, the user can directly drive the voltage source and bypass the on-board regulators. This can be accomplished by removing jumpers JP6 and JP9 for 3.3V and 2.5V voltages respectively.
3.16.1 Voltage Regulators Jumper Settings The following table shows the jumper setting for the 3.3V and 2.5V supply voltages on the Spartan-II PCI development board.
Table 11 - Voltage Regulators Jumper Settings Jumper Jumper
Setting 3.3V Source 2.5V Source
Open External 3.3V supply via JP7 connector
NA JP6
Closed On-board 3.3V regulator NA Open NA External 2.5V supply via JP10
connector JP9
Closed NA On-board 2.5V regulator
3.17 Spartan-II Configuration Mode Select The following table shows the Spartan-II Configuration Mode Select jumper settings.
April 1, 2002 15
Table 12 - Spartan-II Configuration Mode Select
J1 Mode PC Pull-up 1-2 (M0) 3-4 (M1) 5-6 (M2)
Master Serial No Closed Closed Closed Master Serial Yes Closed Closed Open Slave Serial No Open Open Open Slave Serial Yes Open Open Closed Slave Parallel No Closed Open Open Slave Parallel Yes Closed Open Closed JTAG No Open Closed Open JTAG Yes Open Closed Closed
3.18 P160 Expansion Module
A versatile expansion slot is implemented on the Spartan-II board, allowing application specific cards or modules to be easily interfaced with the Spartan-II FPGA. The P160 Expansion Slot is made up of two 80-pin connectors yielding 110 user I/O signals to an add-on module.
3.18.1 Expansion Module Signal Assignments The following tables show the Spartan-II pin assignments to the P160 Expansion Module connectors (JX1 & JX2) located on the Spartan-II development board.
April 1, 2002 16
Table 13 – JX1 User I/O Connector
FPGA Pin #
I/O Connector Signal Name
JX1 Pin #
I/O Connector
Signal Name
FPGA Pin #
TCK A1 B1 FPGA.BITSTREAM NA GND A2 B2 SM.DOUT/BUSY
TMS A3 B3 FPGA.CCLK NA Vin A4 B4 DONE NA TDI A5 B5 INITn NA GND A6 B6 PROGRAMn NA TDO A7 B7 NC NA 3.3V A8 B8 LIOB8 B19 E16 LIOA9 A9 B9 LIOB9 A19 NA GND A10 B10 LIOB10 B18 E15 LIOA11 A11 B11 LIOB11 A18 NA 2.5V A12 B12 LIOB12 B17 E14 LIOA13 A13 B13 LIOB13 A17 NA GND A14 B14 LIOB14 A16 F12 LIOA15 A15 B15 LIOB15 B15 NA Vin A16 B16 LIOB16 A15 C10 LIOA17 A17 B17 LIOB17 B14 NA GND A18 B18 LIOB18 A14 D10 LIOA19 A19 B19 LIOB19 B13 NA 3.3V A20 B20 LIOB20 A13 B8 LIOA21 A21 B21 LIOB21 B12 NA GND A22 B22 LIOB22 C18 A7 LIOA23 A23 B23 LIOB23 D17 NA 2.5V A24 B24 LIOB24 C17 B7 LIOA25 A25 B25 LIOB25 D16 NA GND A26 B26 LIOB26 C16 B6 LIOA27 A27 B27 LIOB27 D15 NA Vin A28 B28 LIOB28 C15 A5 LIOA29 A29 B29 LIOB29 D14 NA GND A30 B30 LIOB30 C14 B5 LIOA31 A31 B31 LIOB31 D13 NA 3.3V A32 B32 LIOB32 C13 A4 LIOA33 A33 B33 LIOB33 E13 NA GND A34 B34 LIOB34 C12 B4 LIOA35 A35 B35 LIOB35 D12 NA 2.5V A36 B36 LIOB36 E12 A3 LIOA37 A37 B37 LIOB37 C9 NA GND A38 B38 LIOB38 D9 B3 LIOA39 A39 B39 LIOB39 C8 NA Vin A40 B40 LIOB40 D8
April 1, 2002 17
Table 14 – JX2 User I/O Connector
FPGA Pin #
I/O Connector
Signal Name
JX2 Pin #
I/O Connector Signal
Name
FPGA Pin #
V14 RIOA1 A1 B1 GND NA Y14 RIOA2 A2 B2 RIOB2 W18 W13 RIOA3 A3 B3 Vin NA Y18 RIOA4 A4 B4 RIOB4 W17 Y13 RIOA5 A5 B5 GND NA Y17 RIOA6 A6 B6 RIOB6 W16 V13 RIOA7 A7 B7 3.3V NA Y16 RIOA8 A8 B8 RIOB8 W15 Y12 RIOA9 A9 B9 GND NA Y15 RIOA10 A10 B10 RIOB10 W14 V12 RIOA11 A11 B11 2.5V NA
AB20 RIOA12 A12 B12 RIOB12 AA20 V11 RIOA13 A13 B13 GND NA
AA19 RIOA14 A14 B14 RIOB14 AA18 W11 RIOA15 A15 B15 Vin NA AB18 RIOA16 A16 B16 RIOB16 AA17 V10 RIOA17 A17 B17 GND NA
AB17 RIOA18 A18 B18 RIOB18 AB16 Y10 RIOA19 A19 B19 3.3V NA
AA15 RIOA20 A20 B20 RIOB20 AB15 W10 RIOA21 A21 B21 GND NA AA14 RIOA22 A22 B22 RIOB22 AB14
Y9 RIOA23 A23 B23 2.5V NA AA13 RIOA24 A24 B24 RIOB24 AB13 W9 RIOA25 A25 B25 GND NA
AA12 RIOA26 A26 B26 RIOB26 AB11 Y8 RIOA27 A27 B27 Vin NA
AB10 RIOA28 A28 B28 RIOB28 AA10 W8 RIOA29 A29 B29 GND NA AB9 RIOA30 A30 B30 RIOB30 AA9 Y7 RIOA31 A31 B31 3.3V NA
AB8 RIOA32 A32 B32 RIOB32 AA8 W7 RIOA33 A33 B33 GND NA AA7 RIOA34 A34 B34 RIOB34 AB6 Y6 RIOA35 A35 B35 2.5V NA
AA6 RIOA36 A36 B36 RIOB36 AB5 W6 RIOA37 A37 B37 GND NA AA5 RIOA38 A38 B38 RIOB38 AB4 W5 RIOA39 A39 B39 Vin NA AA4 RIOA40 A40 B40 RIOB40 AB3
April 1, 2002 18
4 Design Download
The Spartan-II development board supports multiple methods of configuring the Spartan-II FPGA. The JTAG port on the Spartan-II development board can be used to directly configure the Spartan-II FPGA, or to program the on-board XC18V02 ISP PROM. Once the ISP PROM is programmed, it can be used to configure the Spartan-II FPGA. The Slave Parallel/Slave Serial port on this development board can also be used to configure the Spartan-II FPGA. The following figure shows the setup for all Spartan-II FPGA configuration modes that are support ed on the Spartan-II development board.
PC
JTAGCable
Spartan-II™Development
Board
J2
JP
1
AC
/DC
Ad
apte
r
ParallelPort
J3
Slave Serial/Slave Parallel
Figure 15 – Download Setup
4.1 JTAG Interface The J2 JTAG connector on the Spartan-II development board can be used to configure the Spartan-II or to program the on-board XC18V02 ISP PROM. The Memec Design JTAG cable is connected to the Spartan-II development board via J2 at one end and to the PC parallel port at the other end.
4.1.1 Configuring the Spartan-II FPGA
When the JTAG port is used to configure the Spartan-II FPGA, the following steps must be taken: • Using Table 13 set the Configuration Mode of the Spartan-II FPGA to JTAG Mode. • Install the JP25 jumper if the P160 module is not present • Install JP12 in position 2-3. • Use the Xilinx JTAG programmer (iMPACT) utility to load the design bit file into the
Spartan-II FPGA. You will need to associate the ISP PROM with either a dummy .mcs file, or a .bsd file to allow the JTAG programming software to pass data through the ISP PROM.
4.1.2 Programming the XC18V02 ISP PROM When the JTAG port is used to program the ISP PROM, the following steps must be taken:
• Using Table 13 set the Configuration Mode of the Spartan-II FPGA to Master Serial Mode.
• Install the JP25 jumper if the P160 module is not present • Install JP12 in position 2-3.
April 1, 2002 19
• Use the Xilinx JTAG programmer utility (iMPACT) to load the design mcs file into the ISP PROM. You will need to associate the FPGA with either a dummy .bit file or a .bsd file to allow the JTAG programming software to pass data through the FPGA.
• Upon programming of the 18V02 ISP PROM, the on-board PROGn push button switch (SW2) is used to initiate the Spartan-II FPGA configuration.
4.2 Slave Serial Interface
In this mode, an external source provides the configuration bit stream and the configuration clock (CCLK) to the Spartan-II FPGA. Refer to Table 13 for setting up the Configuration Mode pins. The JP12 jumper must be installed in position 1-2 for this mode of configuration.
4.3 Slave Parallel In this mode, an external source provides the configuration bit stream and the configuration clock (CCLK) to the Spartan-II FPGA. Refer to Table 13 for setting up the Configuration Mode pins. The JP12 jumper must be installed (position 1-2) for this mode of configuration.
April 1, 2002 20
Revision History
V1.0 Initial Release 4/1/02
April 1, 2002 21
Appendix A - Spartan-II 200 PCI Board Schematics
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
VOLTAGE INPUT JACK REGULATION LED
VIN
3.3V 1X2Header
2.5V 1X2Header
TEST LOOP
I = P/V = 2.5/(5-2.5) = =2.5/2.5 = 1A
Pmax = (Tj-Ta)/Rth = (125 - 50) / 30°C/W = 2.5W
(5V) 1X2Header
Pmax = (Tj-Ta)/Rth = (125 - 50) / 25°C/W = 3W
I = P/V = 3/(5-3.3) = 3/1.7 = 1765mA
STANDALONEON/OFF SWITCH
SP
AR
TA
N-I
I P
CI
: D
S-B
D-2
S20
0PC
I
RUBBER FEET
GROUND TEST LOOPS
MOUNTING HOLES
BRACKET
<OrgAddr4>
Spartan II PCI 32 Development Board
MemecBoardWednesday, January 23, 2002
1 8
C<OrgAddr1><OrgAddr2><OrgAddr3>
1
Jim Elliott
POWER
Size Rev
Sheetof
Last Modified
Designer
HS2
HS3
3.3V
2.5V
5V
2.5V
2.5V
5V
3.3V
5V
3.3V
2.5V
5VJACK
5VJACK
3.3V
5V
5VJACK
5V
NE7 Mounting Hole (.125)
JP9
1X2
12JP10
1X2
12
NE1 SHUNT-LO-CL
JP11
Test Point Loop - Red
TP1
C12.2u
NE12 Little Rubber Feet
NE14 Mounting Hole (.125)
5A
U1 TPS75533KTT
3
1
45
26GND
EN
OUTPUTFB/PG
INHS
C32.2u
R2330
JP1
Barrel Jack SMT
12
JP8
Test Point Loop - Red
JP3
Test Point Loop - Red
NE9 Little Rubber Feet
NE10 Little Rubber Feet
C42.2u
NE11 Little Rubber Feet
SW1
SPDT Slide 6A
1
2
3
NE2 Mounting Hole (.125)
TP2
DS3LST670-HK
JP6
1X2
12
JP2
Test Point Loop - Black
+ C2150u
JP4
1X2
12
R3130
NE3 Mounting Hole (.125)
NE13 SHUNT-LO-CL
R1750
JP5
Test Point Loop - Black
U2REG1117FA-2.5 DDPAK
1 2
3
4
VIN VOUT
GNDHS
NE20 PCI Bracket - rectangle
JP7
1X2
12
DS1LST670-HK
DS2LST670-HK
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
Slave Serial
1 2
1
Indicates jumper installed ('0')Indicates jumper removed ('1')
Master-serial
20
Boundary-scan
Mode
CONFIGURATION BLOCK
0
FPGA JTAG BYPASS
Populate when the FPGA is depopulated/disabled to maintain JTAG chain integrity
BANK 0 - USER IO & PCI CLK BANK 2 - SDRAM BANK 3 - SDRAM
BANK 4 - P160 HEADERS BANK 6 - PCI BANK 7 - PCI
POWER BLOCK
Pull-ups
Yes
Yes
YesNo
No
No
Slave Parallel
No
Yes
BANK 5 - P160 RIGHT HEADER
BANK 1 - P160 LEFT HEADER
<OrgAddr4>
Spartan II PCI 32 Development Board
MemecBoardWednesday, January 23, 2002
2 8
C<OrgAddr1><OrgAddr2><OrgAddr3>
1
Jim Elliott
FPGA
Size Rev
Sheetof
Last Modified
Designer
M1M0
M2
TDO.PROM.to.TDI.FPGATCK
TDO.FPGA.to.TDI.EXP
FPGA.BITSTREAM
TDO.PROM.to.TDI.FPGA TDO.FPGA.to.TDI.EXP
SM.DOUT/BUSY SM.D1
SM.D3
SM.D2
DONE
PROGRAMnFPGA.CCLK
TMS
AD18
FRAMEn
AD24
AD09
AD06
AD28
AD00
AD16
INTAnAD20
TRDYnAD04 AD22
C/BE0n RSTn
IDSEL
STOPnGNTn
AD11
AD13
AD02
AD15
AD26
PAR
AD03
AD10
AD25
AD29
C/BE2n
AD21
PERRn
AD01
DEVSELn AD27
AD31
AD14
AD08
AD05
SERRn
C/BE1n
AD17
AD12REQn
AD07
C/BE3n
IRDYn
AD23
AD19
CLK.CAN1
AD30
SM.D5SM.D6 INITn
SM.CSnSM.RDWRn
MEM.D29
MEM.D28
MEM.D25MEM.D24
MEM.D30
MEM.D27MEM.D26
MEM.D31
MEM.D13
MEM.D15
MEM.D14
MEM.D8
MEM.D9MEM.A6
MEM.A4
MEM.A9
MEM.A5
MEM.A7MEM.A8
MEM.A3
SM.D7
SM.D4
MEM.DQM1
MEM.DQM3
MEM.CLKE
MEM.D12
MEM.D10
MEM.D11
MEM.D20MEM.D19
MEM.D16
MEM.D17
MEM.D18
MEM.D22
MEM.D21
MEM.D23
MEM.D6
MEM.D7
MEM.CASn
MEM.D5
MEM.D4
MEM.DQM2
MEM.A2
MEM.A1
MEM.A0
MEM.RASn
MEM.A10
MEM.DQM0
LIO.B20
MEM.BS1
MEM.BS0
MEM.CSn
MEM.WEn
LIO.A37LIO.A35
LIO.A33
MEM.D0
MEM.D2
MEM.D3
MEM.D1MEM.CLK
RIO.B40
RIO.A40
RIO.A26
RIO.B34RIO.A36
RIO.A34
RIO.B38RIO.A30
RIO.A32
RIO.A38
RIO.A28RIO.B36
RIO.B20
RIO.B22
RIO.B32
RIO.B26
RIO.A22
RIO.B24
RIO.B28
RIO.B30
RIO.A24
RIO.A20
RIO.A16
RIO.A14
RIO.B18
RIO.B14
RIO.B16
RIO.A18
RIO.A29RIO.A27
RIO.A33
LIO.B18
RIO.A35
RIO.A31
RIO.A9
LIO.B30
LIO.B19
RIO.A3
RIO.A7
RIO.A39
RIO.A15
RIO.A11
RIO.A37
RIO.B2
RIO.A13
RIO.A5
RIO.A6
RIO.A4
RIO.B6
RIO.A23
RIO.A19
RIO.A10
RIO.B4
RIO.B10
RIO.A21
RIO.B8
RIO.A25
RIO.A8
RIO.A17
RIO.A12
RIO.B12
RIO.A1RIO.A2
LIO.B13
LIO.B14
LIO.B16
LIO.B11
LIO.B29
LIO.B10
LIO.B8
LIO.B15
LIO.B17
LIO.B9
LIO.B12
LIO.B27
LIO.B24LIO.A29
LIO.B26LIO.B21
LIO.B22
LIO.B25
LIO.B23
LIO.A31
LIO.A27
PCI.CLK
LIO.B36
LIO.B34LIO.B35
LIO.B33
LIO.B31
LIO.B32
LIO.A25
LIO.A21
LIO.A23
DIP2
DIP3
DIP1
DIP4
DIP6
DIP5
DIP7
DISPLAY.2G
DIP8
TXDRXD
LIO.A39
LIO.B40
LIO.A19
LIO.A9
LIO.A13
LIO.A15
LIO.A11
LIO.A17
LIO.B39
LIO.B37
LIO.B38
FPGA.RESETn
LED.USER
CLK.CAN2
DISPLAY.1F
DISPLAY.1D
DISPLAY.1B
DISPLAY.1C
DISPLAY.1E
DISPLAY.1G
DISPLAY.1A
PUSH.USER1
DISPLAY.2E
DISPLAY.2F
DISPLAY.2D
DISPLAY.2CDISPLAY.2B
DISPLAY.2A
LIO.B28
3.3V
VBANK1
VBANK5 3.3V 3.3VVBANK4
3.3V 3.3V
2.5V
3.3V
VBANK0
3.3V
R103.3k
JP30 1X2
12
NE6 SHUNT-LO-CL
Bank 1
*#* See Chart on Core Power Symbol.
U5B
XC2S200
G13
G12
F16
F15
F14
F13
C14
D12B12
B17
D11
C17
C13
D13
D14
D17
D15
F12
E12
B18
A16
C15
D16
A11
C16
B15
A15
E15
E16
C18
A17
C12
B19
B14
A13
A14
E13
C19
A18
E14
B13
A19
A20
VC
CO
_1V
CC
O_1
VC
CO
_1V
CC
O_1
VC
CO
_1V
CC
O_1
IO
IOIO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GCLKPAD2
IO
IO
IO*1*
*1*IO
*1*IO
*1*IO
*1*IO
IO*1*
*1*IO
IO*1*
IO*2*
IO*2*
IO*2*
IO_CS
IO_VREF_1
IO_VREF_1
IO_VREF_1
*3*IO_VREF_1
IO_WRITE
Bank 2
*#* See Chart on Core Power Symbol.
U5C
XC2S200
K17
J17
H17
G17
L16
K16
H19
F19
J22J18
E20
G18
E21
K22
F18F20
L17G21
L21
J21
G20 L22G19
J20
J19D21
E22
C22
L18
F22K19
H21
K18
H22H20
K20
D20C21
L20H18
K21F21
D22
VC
CO
_2V
CC
O_2
VC
CO
_2V
CC
O_2
VC
CO
_2V
CC
O_2
IO
IO
IOIO
IO
IO
IO
IO
IOIO
IOIO
IO
IO
IO IOIO*1*
*1*IO
*1*IOIO*1*
IO*1*
IO*1*
*1*IO
IO*1**2*IO
*2*IO
*2*IO
IO_D1IO_D2
IO_D3
IO_DIN_D0IO_DOUT_BUSY
IO_IRDYIO_VREF_2
IO_VREF_2IO_VREF_2
IO_VREF_2*3*
R7330
J1
2X3
12
34
56
R83.3k
Core Power
VCCINT = 2.5V
Notes:
2s200 2s150 2s100
*1*
*2*
*3*
IO IO
IO
IO IO
NC NC
NC
VREF
U5J
XC2S200
E5
E18
F6 F17
G7
G8
G9
G14
G15
G16
H7
H16
J7 J16
P7
P16
R7
R16
T7 T8 T9 T14
T15
T16
U6
U17
V5
V18
AB22AB1
AA21AA2Y20
Y3P14P13P12P11P10
P9N14N13N12N11N10
N9M14M13M12M11M10
M9L14
L13
L12
L11
L10
L9 K14
K13
K12
K11
K10
K9
J14
J13
J12
J11
J10
J9 C20
C3
B21
B2
A22
A2
A6
B11
A12
B16
E17
D18
E19G22
L19M21R20Y22U18AB21AA16AB12AA11AB7AA3AA1U3R3M2L2G2D1C2W19W4D19D4
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
NC
NC
NC
NC
NC
NC
NC
NCNC
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
Bank 5
*#* See Chart on Core Power Symbol.
U5F
XC2S200
U10
U9
U8
U7
T11
T10
AA7W11
V7
V11
AB11
AB10W10
W6
AA4
Y9AB9
Y8
Y7
AB5
AA8
Y11
AB6
W7
V9
W5
U11
AB4
AB3
W9
V8AA6
V10
AB8
AA9
AA10
W8
AA5
Y10
Y6
VC
CO
_5V
CC
O_5
VC
CO
_5V
CC
O_5
VC
CO
_5V
CC
O_5
IOIO
IO
IO
IO
IOIO
IO
IO
IOIO
IO
IO
IO
IO
GCLKPAD1
IO
IO
IO
*1*IO
IO*1*
*1*IO
*1*IO
IO*1*
*1*IO*1*IO
IO*1*
IO*2*
IO*2*
IO*2*
IO_VREF_5
IO_VREF_5
IO_VREF_5
*3*IO_VREF_5
Bank 3
*#* See Chart on Core Power Symbol.
U5D
XC2S200
T17
R17
P17
N17
N16
M16
R18T21
M20M19
T20
P18
W22
N20
N18
U19P20P21
U22
T18
W21P19
N19
M18
V21
T19V22
AA22V20
R22
M17
P22
N22
R21T22
Y21V19
M22
N21
R19
U21
U20
VC
CO
_3V
CC
O_3
VC
CO
_3V
CC
O_3
VC
CO
_3V
CC
O_3
IOIO
IOIO
IO
IO
IO
IO
IO
IOIOIO
IO
IO
IOIO*1*
IO*1*
IO*1*
*1*IO
*1*IO*1*IO
*1*IO*1*IO
IO*2*
IO*2*
IO*2*
IO_D4
IO_D5IO_D6
IO_D7IO_INIT
IO_TRDY
IO_VREF_3
IO_VREF_3
IO_VREF_3
*3*IO_VREF_3
Bank 4
*#* See Chart on Core Power Symbol.
U5E
XC2S200
U16
U15
U14
U13
T13
T12
AA20
V14AA14
AA19
W18
W17
Y13
V16Y17
AB15
AB18
Y12
Y15
Y16
U12
AB17
V13
AB13
W12
AA15
AA12V15
AA17
Y18V17
W14
AA18
Y14
V12
W16
W15
W13
AB14
AB16
AA13
AB19
AB20
VC
CO
_4V
CC
O_4
VC
CO
_4V
CC
O_4
VC
CO
_4V
CC
O_4
IO
IOIO
IO
IO
IO
IO
IOIO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GCLKPAD0
IO
IOIO
IO*1*
IO*1*IO*1*
*1*IO
IO*1*
*1*IO
IO*1*
IO*1*
*2*IO
*2*IO
*2*IO
IO_VREF_4
IO_VREF_4
IO_VREF_4
IO_VREF_4*3*
Bank 0
*#* See Chart on Core Power Symbol.
U5A
XC2S200
G11
G10
F10
F9 F8 F7
B10
C5
A3
D9E6
E10
E7
B5
C10
D6
D7
A10
D8C7
A7B7
C11
E9
B9
A8A4
D5
D10
B8
A5
B3
E11
B6
C9
C8
F11
C6
E8
A9
B4
VC
CO
_0V
CC
O_0
VC
CO
_0V
CC
O_0
VC
CO
_0V
CC
O_0
IO
IO
IO
IOIO
IO
IO
IO
IO
IO
IO
IO
IOIO
IOIO
GCLKPAD3
IO
IO
IOIO*1*
IO*1*
*1*IO
*1*IO
IO*1*
IO*1*
*1*IO
IO*1*
*2*IO
*2*IO
*2*IO
IO_VREF_0
IO_VREF_0
IO_VREF_0
IO_VREF_0*3*
R93.3k
JP17
1X2 RA
12
R123.3k Configuration
(Driven by VCCO_2)
(Driven by VCCO_3)
(Driven by VCCO_2)
U5I
XC2S200B22Y19
AB2U5Y4
W20
V6Y5
C4B20A21D3
CCLKDONE
M0M1M2
PROGRAM
PWDNSTATUS
TCKTDITDOTMS
Bank 7
*#* See Chart on Core Power Symbol.
U5H
XC2S200
L7 K7
K6
H6
G6
J6
F1L4
H5L1L6
E1K4
F3K1K5
E3
F2
J2J5
H2B1
G1
H3
F5
G5
H1
F4
G4
J3
G3
L5
E4C1
J1
J4
K2
L3
E2
K3
H4
D2
VC
CO
_7V
CC
O_7
VC
CO
_7V
CC
O_7
VC
CO
_7V
CC
O_7
IOIO
IOIOIO
IOIO
IOIOIO
IO
IO
IOIO
IOIO
IO
IO
IO
IO
IO*1*
*1*IO
*1*IO
IO*1*
*1*IO
IO*1*
*1*IO*1*IO
IO*2*
IO*2*
IO*2*
IO_IRDY
IO_VREF_7
IO_VREF_7
IO_VREF_7
*3*IO_VREF_7
Bank 6
*#* See Chart on Core Power Symbol.
U5G
XC2S200
N7
M7
T6 R6
P6
N6
W3Y2
M4
P4W2
U1
U4
N4W1T4
M5U2
R5M3
T2
P3
T1R2
P2
N3
V4
V2 N5
T5
R1
M6
V3
V1
P1
P5
N1
M1
T3
R4
N2
Y1
VC
CO
_6V
CC
O_6
VC
CO
_6V
CC
O_6
VC
CO
_6V
CC
O_6
IOIO
IO
IOIO
IO
IO
IOIOIO
IOIO
IOIO
IO
IO
IOIO
IO
IO
IO*1*
IO*1* *1*IO
IO*1*
*1*IO
*1*IO
IO*1*
IO*1*
*2*IO
*2*IO
*2*IO
IO_TRDY
IO_VREF_6
IO_VREF_6
IO_VREF_6
IO_VREF_6*3*
NE4 SHUNT-LO-CL
NE5 SHUNT-LO-CL
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
JTAG
PROGRAM PUSHBUTTONXC18 PROM
Populate when the XC18 PROM isdepopulated/disabled to maintain JTAG chainintegrity
JTAG PORT
FPGA POWER SELECT
DONE
PROGRAMMING DONE LED
CLOCK
FPGA RESET CIRCUITSELECTMAP PORT
PROM JTAG BYPASS
TDO.PROM.to.TDI.FPGA TDOTDITDI TDO
JTAG CHAIN DIAGRAM
EXP SOCKETFPGAPROM
TDI.PORT.to.TDI.PROM TDO
TDO.EXP.to.TDO.PORT
TDITDO.FPGA.to.TDI.EXP
JP22 JP17 JP25
SelectMAP/Slave Serial : 1-2PROM (Default): 2-3
<OrgAddr4>
Spartan II PCI 32 Development Board
MemecBoardWednesday, January 23, 2002
3 8
C<OrgAddr1><OrgAddr2><OrgAddr3>
1
Jim Elliott
FPGA PERIPHERALS
Size Rev
Sheetof
Last Modified
Designer
TDI.PORT.to.TDI.PROM
TCKTMS
TDI.PORT.to.TDI.PROM
DONE
TDO.PROM.to.TDI.FPGA
TCK
FPGA.BITSTREAM
PROGRAMn
TDO.PROM.to.TDI.FPGA
PROGRAMn
FPGA.CCLK
DONE
FPGA.BITSTREAMDONE
CLK.CAN2
SM.D1
SM.D3
SM.RDWRnSM.D7SM.D6
SM.D2
SM.CSn
SM.D5SM.D4
FPGA.CCLKINITn
PROGRAMn
SM.DOUT/BUSY
TDO.EXP.to.TDO.PORTTDI.PORT.to.TDI.PROMTMS
CLK.CAN1
INITn
FPGA.RESETn
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V
VBANK4
3.3V 2.5V
3.3V
3.3V
VBANK1
3.3V
VBANK0
VBANK5
2.5V2.5V 2.5V 2.5V
NE15 SHUNT-LO-CL
R14330
NE8 TL1105 CAP - RED
JP191X3
1
2
3
NE19 SHUNT-LO-CL
JP32
1X2
12Y4
100MHz
1
2 3
4EN
GND OUT
VCC
NE16 SHUNT-LO-CL
JP351X3
1
2
3
R163.3k1%
C12CAP-1009-X7R-2020-0603-006
J3
SelectMAP RA
1 23 45 67 89 10
11 1213 1415 16
CSn DIN/D0DONE D1CCLK D2INITn D3PROGRAMn D4NC D5RDWRn D6DOUT/BUSY D7
144
1112 22
23
3433
U6
XC18V02VQ44C
40
42
43
357
913
1415
18
1921
25
27
2931
8
1028 416
17 35 3816 26 36
D0/DATA
D2
CLK
TDITMSTCK
D4OE/RESET
D6CE
GN
D
D7CEO
D5
D3
D1TDO
VC
CO
CFG
ND
GN
D
GN
D
VC
CV
CC
VC
C
VC
CO
VC
CO
VC
CO
J2
JTAG7 RA
12
4567
3
VCCGND
TCKTDO
TDITMS
NC
R6910k1%
NE17 SHUNT-LO-CL
R15
01%
JP261X3
1
2
3
JP341X3
1
2
3
Y5
24MHz
1
2 3
4EN
GND OUT
VCC
SW3
Tl1105SP
A B
A' B'
C11CAP-1009-X7R-2020-0603-006 DS5
LST670-HK
R1
R2
Q2
BCR133
3
1
2
JP12 1X3
12
3
JP24
1X2
12
JP22
1X2 RA
1 2
R133.3k
U11
TPS3823
123 4
5RESETGNDMR WDI
VDD
NE18 SHUNT-LO-CL
SW2
Tl1105SP
A B
A' B'
C80.1u
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
LOCKING NOTSUPPORTED
-12V HEADER
PRSNT1# and PRSNT2# identify the powerrequirements of this card to the platform
POWER MANAGEMENT NOTSUPPORTED
POWER MANAGEMENT NOTSUPPORTED
CACHE NOTSUPPORTED
+12V HEADER
<OrgAddr4>
Spartan II PCI 32 Development Board
MemecBoardWednesday, January 23, 2002
4 8
C<OrgAddr1><OrgAddr2><OrgAddr3>
1
Jim Elliott
PCI 32 BIT EDGE
Size Rev
Sheetof
Last Modified
Designer
PCI.CLK
AD14
AD29
IRDYn
AD03
AD23
AD21
AD07
AD12
AD17
AD31
DEVSELn
AD01
SERRn
AD27
C/BE2n
C/BE3n
PERRn
AD08
REQn
AD19
AD25
AD10
C/BE1n
AD05
AD15
AD06
PAR
AD16
AD28
AD20
GNTn
FRAMEn
AD22
STOPn
AD30
AD13
INTAn
AD02
AD09
AD11
AD00
AD04
IDSEL
RSTn
AD18
AD24
TRDYn
C/BE0n
AD26
5V5V
C82CAP-0479-X7R-2020-0603-006
C86CAP-0109-X7R-2020-0603-006
C90CAP-0109-X7R-2020-0603-006
C97CAP-0479-X7R-2020-0603-006
C87CAP-0109-X7R-2020-0603-006
R23 0
C89CAP-0109-X7R-2020-0603-006
R26 0
C81CAP-0479-X7R-2020-0603-006
JP36
1X2
12
C85CAP-0109-X7R-2020-0603-006
C100CAP-0109-X7R-2020-0603-006
C84CAP-0109-X7R-2020-0603-006
JP37
1X2
1 2
C88CAP-0109-X7R-2020-0603-006
C91CAP-0109-X7R-2020-0603-006
JE1 PCI32
A62A61
A57A58A59A60
A40A41A42A43A44A45A46A47A48A49
A52A53A54A55A56
B52B53B54B55B56B57B58B59B60B61B62
B40B41B42B43B44B45B46B47B48B49
A30A31A32A33A34A35A36A37A38A39
B30B31B32B33B34B35B36B37B38B39
A20A21A22A23A24A25A26A27A28A29
B20B21B22B23B24B25B26B27B28B29
A10A11
A14A15A16A17A18A19
B10B11
B14B15B16B17B18B19
A1A2A3A4A5A6A7A8A9
B1B2B3B4B5B6B7B8B9
+5V+5V
AD02AD0+5V (I/O)REQ64
SDONESBOGNDPARAD15+3.3VAD13AD11GNDAD09
C/BE0+3.3VAD06AD04GND
AD08AD07+3.3VAD05AD03GND
AD01+5V (I/O)
ACK64+5V+5V
PERR+3.3VSERR+3.3VC/BE1AD14GND
AD12AD10GND
GNDAD18AD16+3.3VFRAMEGNDTRDYGNDSTOP+3.3V
AD19+3.3VAD17
C/BE2GNDIRDY
+3.3VDEVSEL
GNDLOCK
AD30+3.3VAD28AD26GNDAD24IDSEL+3.3VAD22AD20
AD31AD29GND
AD27AD25+3.3VC/BE3AD23GND
AD21
+5V (I/O)RSVD
+3.3VauxRST+5V (I/O)GNTGNDPME
RSVDPRSNT2
RSVDGNDCLKGNDREQ
+5V (I/O)
TRST+12VTMSTDI+5VINTAINTC+5VRSVD
-12VTCKGNDTDO+5V+5V
INTBINTD
PRSNT1
C93CAP-0109-X7R-2020-0603-006
C95CAP-0479-X7R-2020-0603-006
C102CAP-0479-X7R-2020-0603-006
C83CAP-0109-X7R-2020-0603-006
C92CAP-0109-X7R-2020-0603-006
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EXP SOCKET
JTAG BYPASS
T2E 7S8
Spartan II PCI 32 Development Board
MemecBoardWednesday, January 23, 2002
5 8
CSuite 540, 1212 31st Ave. NECalgary, AlbertaCanada
1
Jim Elliott
EXP SOCKET
Size Rev
Sheetof
Last Modified
Designer
TDO.EXP.to.TDO.PORTTDO.FPGA.to.TDI.EXP
RIO.A1RIO.A2RIO.A3RIO.A4
RIO.A7
RIO.A5RIO.A6
RIO.A8
RIO.A13
RIO.A11
RIO.A9RIO.A10
RIO.A12
RIO.A16
RIO.A14RIO.A15
RIO.A21
RIO.A19
RIO.A17RIO.A18
RIO.A20
RIO.A24
RIO.A22RIO.A23
RIO.A29
RIO.A27
RIO.A25RIO.A26
RIO.A28
RIO.A32
RIO.A30RIO.A31
RIO.A37
RIO.A35
RIO.A33RIO.A34
RIO.A36
RIO.A40
RIO.A38RIO.A39
RIO.B2
RIO.B4
RIO.B6
RIO.B8
RIO.B14
RIO.B12
RIO.B16
RIO.B10
RIO.B30
RIO.B28
RIO.B22
RIO.B26
RIO.B20
RIO.B24
RIO.B32
RIO.B18
RIO.B38
RIO.B36
RIO.B40
RIO.B34
LIO.B30
LIO.B27
TDO.EXP.to.TDO.PORT
LIO.A33
LIO.A31
LIO.B28
LIO.A25
LIO.A21
LIO.B15
LIO.B25
LIO.B17
LIO.B26
LIO.B36
LIO.A29
LIO.B37
LIO.A23
LIO.A19
LIO.B35
LIO.B20
LIO.B16
LIO.B31
LIO.B29
LIO.B19
LIO.A17
TMS
LIO.A37
LIO.B32
LIO.B21
TCK
LIO.B33
LIO.B40LIO.A39
LIO.B24LIO.B23LIO.B22
LIO.B38
LIO.A35
LIO.B18
LIO.B13LIO.B12
TDO.FPGA.to.TDI.EXP
LIO.B39
LIO.B34
LIO.A27
LIO.B14
FPGA.BITSTREAMSM.DOUT/BUSYFPGA.CCLK
PROGRAMnINITnDONE
LIO.B11LIO.B10
LIO.B8LIO.B9
LIO.A15
LIO.A13
LIO.A11
LIO.A9
3.3V2.5V 5V5V 3.3V 2.5V
JX2 P160 Right Header MB
B1A1B2A2B3A3B4A4B5A5B6A6B7A7B8A8B9A9B10A10B11A11B12A12B13A13B14A14B15A15B16A16B17A17B18A18B19A19B20A20B21A21B22A22B23A23B24A24B25A25B26A26B27A27B28A28B29A29B30A30B31A31B32A32B33A33B34A34B35A35B36A36B37A37B38A38B39A39B40A40
GNDIOIOIO
VINIOIOIO
GNDIOIOIO
3.3VIOIOIO
GNDIOIOIO
2.5VIOIOIO
GNDIOIOIO
VINIOIOIO
GNDIOIOIO
3.3VIOIOIO
GNDIOIOIO
2.5VIOIOIO
GNDIOIOIO
VINIOIOIO
GNDIOIOIO
3.3VIOIOIO
GNDIOIOIO
2.5VIOIOIO
GNDIOIOIO
VINIOIOIO
JX1 P160 Left Header MB
B1A1B2A2B3A3B4A4B5A5B6A6B7A7B8A8B9A9B10A10B11A11B12A12B13A13B14A14B15A15B16A16B17A17B18A18B19A19B20A20B21A21B22A22B23A23B24A24B25A25B26B27A27B28A28B29A29B30A30B31A31B32A32B33A33B34B35A35B36A36B37A37B38A38B39A39B40A40
A34
A26
DINTCKDOUTGNDCCLKTMSDONEVININITnTDI
PROGRAMnGNDNCTDOIO3.3VIOIOIOGNDIOIOIO2.5VIOIOIOGNDIOIOIOVINIOIOIOGNDIOIOIO3.3VIOIOIOGNDIOIOIO2.5VIOIOIOIOIOIOVINIOIOIOGNDIOIOIO3.3VIOIOIOIOIOIO2.5VIOIOIOGNDIOIOIOVIN
GND
GND
NE21 SHUNT-LO-CL
JP25
1X2 RA
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SERIAL PORT
PUSHBUTTONS
DIP SWITCH
LEDs SEVEN SEGMENT DISPLAYS
a
b
c
d
e
f
g
USE STANDARD STRAIGHT-THRUCABLE WHEN CONNECTING TO A PC
T2E 7S8
Spartan II PCI 32 Development Board
MemecBoardWednesday, January 23, 2002
6 8
CSuite 540, 1212 31st Ave. NECalgary, AlbertaCanada
1
Jim Elliott
USER IO
Size Rev
Sheetof
Last Modified
Designer
PUSH.USER1
TXDRXD
DISPLAY.1A
DISPLAY.1EDISPLAY.1F
DISPLAY.1C
DISPLAY.2C
DISPLAY.2A
DISPLAY.1D
DISPLAY.2F
DISPLAY.1G
DISPLAY.1B
DISPLAY.2G
DISPLAY.2E
DISPLAY.2B
DISPLAY.2D
DIP1
DIP5DIP6
DIP8DIP7
DIP4
DIP2DIP3
LED.USER
3.3V
3.3V
3.3V
3.3V
VBANK0
ABCDEFGDP
CC
DD2
RED CC
3
764211095
8
R573301%
R523301%
R493301%
ABCDEFGDP
CC
DD1
RED CC
3
764211095
8
R383.3k1%
C13.1u
C14.1u
C16.1u
SW5
Tl1105SP
A B
A' B'R583301%
R593301%
R373.3k1%
R503301%
R553301%
R403.3k1%
DS7
LST670-HK
R543301%
R483301%
C15.1u
U10
MAX3221
12345678
161514131211109
ENC1+V+C1-C2+C2-V-RIN
FORCEOFFVCCGND
DOUTFORCEON
DININVALID
ROUT
R393.3k1%
R443301%
R353.3k1%
R463301%
JDR1
DB9 RA
5
9
4
8
3
7
2
6
1
GND
RI
DTR
CTS
TD
RTS
RD
DSR
DCD
R513301%
C17.1u
R453301%
R343.3k1%
R423.3k1%
R473301%
R413.3k1%
R363.3k1%
R563301%
SW4
SWDIP08
12345678 9
10111213141516
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
T2E 7S8
Spartan II PCI 32 Development Board
MemecBoardWednesday, January 23, 2002
7 8
CSuite 540, 1212 31st Ave. NECalgary, AlbertaCanada
1
Jim Elliott
SDRAM
Size Rev
Sheetof
Last Modified
Designer
MEM.A10MEM.A9MEM.A8MEM.A7MEM.A6MEM.A5
MEM.A3MEM.A4
MEM.A2MEM.A1
MEM.D0
MEM.A0
MEM.CASnMEM.RASn
MEM.DQM0MEM.DQM1MEM.DQM2MEM.DQM3
MEM.WEnMEM.CSn
MEM.BS0MEM.BS1
MEM.CLKMEM.CLKE
MEM.D1MEM.D2MEM.D3
MEM.D5MEM.D6MEM.D7
MEM.D4
MEM.D9MEM.D10MEM.D11
MEM.D8
MEM.D16MEM.D17
MEM.D20
MEM.D23MEM.D22
MEM.D13
MEM.D21
MEM.D14MEM.D15
MEM.D12
MEM.D19MEM.D18
MEM.D28MEM.D29
MEM.D25MEM.D26MEM.D27
MEM.D24
MEM.D31MEM.D30
3.3V 3.3V
R71 11 U8
TC59S6432CFT-60
2
252627606162636465
44 58 72
1 29 43
4578101113747677798082838531333436373940424547485051535456
66
1819
20
24
16712859
2223
17
6867
3 9 35 41
6 12 32 38 46 52 78 8486
49 55 75 8115
14213057697073
DQ0
A0A1A2A3A4A5A6A7A8
GN
DG
ND
GN
D
VC
C
VC
CV
CC
DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9
DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31
A9
CASRAS
CS
A10/AP
DQM0DQM1DQM2DQM3
BS0BS1
WE
CLKCKE
VC
CIO
VC
CIO
VC
CIO
VC
CIO
GN
DIO
GN
DIO
GN
DIO
GN
DIO
GN
DIO
GN
DIO
GN
DIO
GN
DIO
GN
D
VC
CIO
VC
CIO
VC
CIO
VC
CIO
VC
C
NCNCNCNCNCNCNC
R70 11
R72 11
R73 11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
Bulk Capacitance
FPGA Core Decoupling
Bulk Capacitance
FPGA IO Decoupling
Bulk Capacitance
Bulk Capacitance
MemoryDecoupling
<OrgAddr4>
Spartan II PCI 32 Development Board
MemecBoardWednesday, January 23, 2002
8 8
C<OrgAddr1><OrgAddr2><OrgAddr3>
1
Jim Elliott
DECOUPLING
Size Rev
Sheetof
Last Modified
Designer
2.5V2.5V 2.5V
3.3V
2.5V
3.3V 3.3V 3.3V
3.3V3.3V 3.3V
VBANK1
VBANK0 VBANK0 VBANK0
VBANK1 VBANK1
VBANK5
VBANK4 VBANK4
VBANK5
VBANK4
VBANK5
5V
2.5V
2.5V
2.5V 2.5V
2.5V2.5V
2.5V
2.5V3.3V
3.3V
3.3V
3.3V3.3V
3.3V
3.3V
3.3V
3.3V 3.3V3.3V 3.3V
3.3V3.3V 3.3V
3.3V 3.3V3.3V
C121.1u
+ C44
CAP-1506-TAN-2020-7343-010
C35.1u
C112
CAP-1009-X7R-2020-0603-006
C18
CAP-0223-X7R-2020-0402-006
C24.1u
+ C43
CAP-1506-TAN-2020-7343-010
C109
CAP-1009-X7R-2020-0603-006
C65.1u
C116.1u
C103
CAP-1009-X7R-2020-0603-006
C117.1u
C57.1u
C23.1u
C29
CAP-0223-X7R-2020-0402-006
C119.1u
C67.1u
C42.1u
C111
CAP-1009-X7R-2020-0603-006
C22.1u
C110
CAP-1009-X7R-2020-0603-006
C31
CAP-0223-X7R-2020-0402-006
C34.1u
C51.1u
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C58.1u
C106
CAP-1009-X7R-2020-0603-006
C30
CAP-0223-X7R-2020-0402-006
C21
CAP-0223-X7R-2020-0402-006
C52.1u
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C50.1u
C40.1u
C105
CAP-1009-X7R-2020-0603-006
C108
CAP-1009-X7R-2020-0603-006
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CAP-0223-X7R-2020-0402-006
C114
CAP-1009-X7R-2020-0603-006
C104
CAP-1009-X7R-2020-0603-006
C20
CAP-0223-X7R-2020-0402-006
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C118.1u
C66.1u
C120.1u
C19
CAP-0223-X7R-2020-0402-006
C113
CAP-1009-X7R-2020-0603-006
C41.1u
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C33.1u
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CAP-1009-X7R-2020-0603-006
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