Shanna-Shaye Forbes sssf@eecs.berkeley *University of California, Berkeley

IEEE International Symposium on Distributed Simulation and Real-Time ApplicationsOctober 27, 2008Vancouver, British Columbia, Canada

Presented by

An Automated Mapping of Timed Functional Specification to A Precision Timed ArchitectureShanna-Shaye Forbes*, Hugo A. Andrade**, Hiren D. Patel* and Edward A. Lee*

Shanna-Shaye Forbessssf@eecs.berkeley.edu*University of California, Berkeley*National Instruments Corporation

Overview

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Programming languages generally abstract away the notion of timing at the software level. We overcome this shortcoming by combining an architecture which has repeatable timing with a model based programming model with temporal semantics.

PRET:Precision Timed Machines

• ISA extensions with timing instructions• Multithreaded architecture with

scratchpad memories and time-triggered access to main memory

• Simulator accepts programs in C with additional timing instructions.

• JOP(Vienna), SPEAR(Vienna), KEP(Kiel), REMIC (Auckland)

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Related Work

LabVIEW

• Actor oriented structured data flow programming language G

• C software synthesis backend to automatically generate code

• Has the ability to incorporate legacy C code into a model based design

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LabVIEW cont.

• Timed loops allow the user to specify the period and offset at which functions are to be executed

IEEE DS-RT, Oct. 27, 2008An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture, Forbes 5

Timed Loop

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Plug-in

• LabVIEW has a plug-in architecture.• We implemented a plug-in that maps

LabVIEW to the PRET architecture.

• Implements timed loops with the PRET timing instruction.

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Simple mutual exclusion example

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Producer

Observer Consumer

Questions?

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Demo

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