SE303A : Backend ASIC...SE303A : Backend ASIC ASIC Design automation Yves MATHIEU...

SE303A : Backend ASICASIC Design automation

Yves MATHIEUyves.mathieu@telecom-paristech.fr

Outline

Bases of CMOS logic

Standard cell design

Standard cell libraries

Standard Cell characterization

Digital Integrated Circuit Testing

Place and route flow

2/69 ICS904-EN2-L4 Yves MATHIEU

The MOS transistorMetal Oxide Semiconductor

N+

LW

t ox

N+

P−

3/69 ICS904-EN2-L4 Yves MATHIEU

CMOS transistorsComplementary Metal Oxide Semiconductor

Gate : G, Drain : D, Source : S, Threshold Voltage : VT

With VTN > 0 and VTP < 0

S

G

D

N+ N+

P−

nMOS transistor

N channelElectrons currentConduction if Vgs > VTN

S

G

D

P+ P+

N−

pMOS transistor

P channelHoles currentConduction if Vgs < VTP

4/69 ICS904-EN2-L4 Yves MATHIEU

Reference technology profile

5/69 ICS904-EN2-L4 Yves MATHIEU

MOS transistors and logic levelsTwo non ideal electronic switches

S

D

VG

nMOS Transistor with Sourceconnected to Ground.

VG = Vss⇒ open switch

VG = Vdd⇒ closed switch

Vdd

D

S

VG

pMOS Transistor with Sourceconnected to power supply

VG = Vss⇒ closed switch

VG = Vdd⇒ open switch

6/69 ICS904-EN2-L4 Yves MATHIEU

CMOS logicCMOS invertor

Boolean input value a = 0

→ Va = 0→ nMOS cutoff→ pMOS conducting

→ Vz = Vdd

→ boolean output value z = 1

boolean input value a = 1

→ Va = Vdd

→ nMOS conducting→ pMOS cutoff

→ Vz = 0

→ Boolean output value z = 0

Vss

Vdd

a z

No static power consumption (first order approximation)

7/69 ICS904-EN2-L4 Yves MATHIEU

CMOS logicCMOS invertor

Boolean input value a = 0

→ Va = 0→ nMOS cutoff→ pMOS conducting

→ Vz = Vdd

→ boolean output value z = 1

boolean input value a = 1

→ Va = Vdd

→ nMOS conducting→ pMOS cutoff

→ Vz = 0

→ Boolean output value z = 0

Vss

Vdd

a z

No static power consumption (first order approximation)

7/69 ICS904-EN2-L4 Yves MATHIEU

CMOS logicCMOS invertor

Boolean input value a = 0

→ Va = 0→ nMOS cutoff→ pMOS conducting

→ Vz = Vdd

→ boolean output value z = 1

boolean input value a = 1

→ Va = Vdd

→ nMOS conducting→ pMOS cutoff

→ Vz = 0

→ Boolean output value z = 0

Vss

Vdd

a z

No static power consumption (first order approximation)

7/69 ICS904-EN2-L4 Yves MATHIEU

CMOS logicThe two input NAND gate

Vss

Vdd

a

a

b

b

z

8/69 ICS904-EN2-L4 Yves MATHIEU

Outline

Bases of CMOS logic

Standard cell design

Standard cell libraries

Standard Cell characterization

Digital Integrated Circuit Testing

Place and route flow

9/69 ICS904-EN2-L4 Yves MATHIEU

"Standard Cells" versus "Full Custom"

Full CustomManual layout of allneeded cells.Long elec. simulations forverif. of a whole block.Wide logic styles choice.Scripting may help layoutphases.Ultimate optimisation forspeed power or area.Only for high value addeddigital or analog blocs.

Standard CellsLayout design limited togeneric cells.Electrical simulation for cellproperties extraction.Small logic styles choice.Automation of synthesis,place and route phases.Suboptimal for speedpower and area.When time-to-market is themain criterion.

10/69 ICS904-EN2-L4 Yves MATHIEU

"Standard Cells" versus "Full Custom"

Full CustomManual layout of allneeded cells.Long elec. simulations forverif. of a whole block.Wide logic styles choice.Scripting may help layoutphases.Ultimate optimisation forspeed power or area.Only for high value addeddigital or analog blocs.

Standard CellsLayout design limited togeneric cells.Electrical simulation for cellproperties extraction.Small logic styles choice.Automation of synthesis,place and route phases.Suboptimal for speedpower and area.When time-to-market is themain criterion.

10/69 ICS904-EN2-L4 Yves MATHIEU

"Standard Cells" versus "Full Custom"

Full CustomManual layout of allneeded cells.Long elec. simulations forverif. of a whole block.Wide logic styles choice.Scripting may help layoutphases.Ultimate optimisation forspeed power or area.Only for high value addeddigital or analog blocs.

Standard CellsLayout design limited togeneric cells.Electrical simulation for cellproperties extraction.Small logic styles choice.Automation of synthesis,place and route phases.Suboptimal for speedpower and area.When time-to-market is themain criterion.

10/69 ICS904-EN2-L4 Yves MATHIEU

"Standard Cells" versus "Full Custom"

Full CustomManual layout of allneeded cells.Long elec. simulations forverif. of a whole block.Wide logic styles choice.Scripting may help layoutphases.Ultimate optimisation forspeed power or area.Only for high value addeddigital or analog blocs.

Standard CellsLayout design limited togeneric cells.Electrical simulation for cellproperties extraction.Small logic styles choice.Automation of synthesis,place and route phases.Suboptimal for speedpower and area.When time-to-market is themain criterion.

10/69 ICS904-EN2-L4 Yves MATHIEU

"Standard Cells" versus "Full Custom"

Full CustomManual layout of allneeded cells.Long elec. simulations forverif. of a whole block.Wide logic styles choice.Scripting may help layoutphases.Ultimate optimisation forspeed power or area.Only for high value addeddigital or analog blocs.

Standard CellsLayout design limited togeneric cells.Electrical simulation for cellproperties extraction.Small logic styles choice.Automation of synthesis,place and route phases.Suboptimal for speedpower and area.When time-to-market is themain criterion.

10/69 ICS904-EN2-L4 Yves MATHIEU

"Standard Cells" versus "Full Custom"

Full CustomManual layout of allneeded cells.Long elec. simulations forverif. of a whole block.Wide logic styles choice.Scripting may help layoutphases.Ultimate optimisation forspeed power or area.Only for high value addeddigital or analog blocs.

Standard CellsLayout design limited togeneric cells.Electrical simulation for cellproperties extraction.Small logic styles choice.Automation of synthesis,place and route phases.Suboptimal for speedpower and area.When time-to-market is themain criterion.

10/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell principles

All cells have sameheight

Power supply andGround connected byabutment.

Cell design should befree of DRC error.

Any abutment of anycouple of cells shouldbe free of DRC error.

Wiring inside celllimited to Metal1 level.

11/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell principles

All cells have sameheight

Power supply andGround connected byabutment.

Cell design should befree of DRC error.

Any abutment of anycouple of cells shouldbe free of DRC error.

Wiring inside celllimited to Metal1 level.

11/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell principles

All cells have sameheight

Power supply andGround connected byabutment.

Cell design should befree of DRC error.

Any abutment of anycouple of cells shouldbe free of DRC error.

Wiring inside celllimited to Metal1 level.

11/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell principles

All cells have sameheight

Power supply andGround connected byabutment.

Cell design should befree of DRC error.

Any abutment of anycouple of cells shouldbe free of DRC error.

Wiring inside celllimited to Metal1 level.

11/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell principles

All cells have sameheight

Power supply andGround connected byabutment.

Cell design should befree of DRC error.

Any abutment of anycouple of cells shouldbe free of DRC error.

Wiring inside celllimited to Metal1 level.

11/69 ICS904-EN2-L4 Yves MATHIEU

Reference technology profile

12/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 standard cell templatepractical design

NMOS areas and PMOSareas already filled.

Body-ties areas for NMOSand PMOS already filled

Body-ties already connectedto Vdd (for PMOS) or Vss (forNMOS)

Simple abutment of cells fillan raw of cells with NMOSand PMOS areas.

13/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 standard cell templatepractical design

NMOS areas and PMOSareas already filled.

Body-ties areas for NMOSand PMOS already filled

Body-ties already connectedto Vdd (for PMOS) or Vss (forNMOS)

Simple abutment of cells fillan raw of cells with NMOSand PMOS areas.

13/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 standard cell templatepractical design

NMOS areas and PMOSareas already filled.

Body-ties areas for NMOSand PMOS already filled

Body-ties already connectedto Vdd (for PMOS) or Vss (forNMOS)

Simple abutment of cells fillan raw of cells with NMOSand PMOS areas.

13/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 standard cell templatepractical design

NMOS areas and PMOSareas already filled.

Body-ties areas for NMOSand PMOS already filled

Body-ties already connectedto Vdd (for PMOS) or Vss (forNMOS)

Simple abutment of cells fillan raw of cells with NMOSand PMOS areas.

13/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 adderpractical design

All transistors have horizontal orientation.

Maximal width defined by NMOS and PMOS areas height.

Use parallel transistors for larger widths.

Drain/Source implants may be used for local short wires (bewarethe resistivity).

Global optimisation of Eulerian Paths (N(P)MOS subcircuits aregraphs which visits every edge exactly once)

14/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 adderpractical design

All transistors have horizontal orientation.

Maximal width defined by NMOS and PMOS areas height.

Use parallel transistors for larger widths.

Drain/Source implants may be used for local short wires (bewarethe resistivity).

Global optimisation of Eulerian Paths (N(P)MOS subcircuits aregraphs which visits every edge exactly once)

14/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 adderpractical design

All transistors have horizontal orientation.

Maximal width defined by NMOS and PMOS areas height.

Use parallel transistors for larger widths.

Drain/Source implants may be used for local short wires (bewarethe resistivity).

Global optimisation of Eulerian Paths (N(P)MOS subcircuits aregraphs which visits every edge exactly once)

14/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 adderpractical design

All transistors have horizontal orientation.

Maximal width defined by NMOS and PMOS areas height.

Use parallel transistors for larger widths.

Drain/Source implants may be used for local short wires (bewarethe resistivity).

Global optimisation of Eulerian Paths (N(P)MOS subcircuits aregraphs which visits every edge exactly once)

14/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 adderpractical design

All transistors have horizontal orientation.

Maximal width defined by NMOS and PMOS areas height.

Use parallel transistors for larger widths.

Drain/Source implants may be used for local short wires (bewarethe resistivity).

Global optimisation of Eulerian Paths (N(P)MOS subcircuits aregraphs which visits every edge exactly once)

14/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 adder abstractpractical design

Only needed informations for Place and Route.

Wires connected to Input/Output pins of the cell

Wires that are obstacles for wiring

The router may use Metal1 has a wiring layer if enough roominside the cell

15/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 adder abstractpractical design

Only needed informations for Place and Route.

Wires connected to Input/Output pins of the cell

Wires that are obstacles for wiring

The router may use Metal1 has a wiring layer if enough roominside the cell

15/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 adder abstractpractical design

Only needed informations for Place and Route.

Wires connected to Input/Output pins of the cell

Wires that are obstacles for wiring

The router may use Metal1 has a wiring layer if enough roominside the cell

15/69 ICS904-EN2-L4 Yves MATHIEU

gpdk045 adder abstractpractical design

Only needed informations for Place and Route.

Wires connected to Input/Output pins of the cell

Wires that are obstacles for wiring

The router may use Metal1 has a wiring layer if enough roominside the cell

15/69 ICS904-EN2-L4 Yves MATHIEU

Outline

Bases of CMOS logic

Standard cell design

Standard cell libraries

Standard Cell characterization

Digital Integrated Circuit Testing

Place and route flow

16/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryExample : gsclib045 library based on gpdk045 technology

Cell category Cell listADD Full/Half adders, 2 outputsAND up to inputsAO AO/AOI up to 6 inputsBUF BuffersFF DFF (EN,SET,RST,QB. . .)INV InvertorMX Multiplexor up to 4 inputsNAND up to 4 inputsNOR up to inputsOA OA/OAI up to 6 inputsOR up to 4 inputsTLAT Latches (SET,RST,. . .)XNOR up to 3 inputsXOR up to 3 inputs

A wide selection ofcells

Facilitate synthesistools usage

Non obvious cells

17/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryExample : gsclib045 library based on gpdk045 technology

Cell category Cell listADD Full/Half adders, 2 outputsAND up to inputsAO AO/AOI up to 6 inputsBUF BuffersFF DFF (EN,SET,RST,QB. . .)INV InvertorMX Multiplexor up to 4 inputsNAND up to 4 inputsNOR up to inputsOA OA/OAI up to 6 inputsOR up to 4 inputsTLAT Latches (SET,RST,. . .)XNOR up to 3 inputsXOR up to 3 inputs

A wide selection ofcells

Facilitate synthesistools usage

Non obvious cells

17/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryExample : gsclib045 library based on gpdk045 technology

Cell category Cell listADD Full/Half adders, 2 outputsAND up to inputsAO AO/AOI up to 6 inputsBUF BuffersFF DFF (EN,SET,RST,QB. . .)INV InvertorMX Multiplexor up to 4 inputsNAND up to 4 inputsNOR up to inputsOA OA/OAI up to 6 inputsOR up to 4 inputsTLAT Latches (SET,RST,. . .)XNOR up to 3 inputsXOR up to 3 inputs

A wide selection ofcells

Facilitate synthesistools usage

Non obvious cells

17/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryBuffering

Cell category Cell listADD X1,X2,X4AND X1,X2,X4,X6,X8AO X2,X2,X4BUF X2,X3,. . .,X16,X20FF X1,X2,X4,X8INV X2,X3,. . .,X16,X20MX X1,X2,X4NAND X1,X2,X4,X6,X8NOR X1,X2,X4,X6,X8OA X1,X2,X4OR X1,X2,X4,X6,X8TLAT X1,X2,X4,X6,X8XNOR X1,X2,X4XOR X1,X2,X4

For synthesis and P&R timingoptimisation.

No way to resize transistors

Growing sizes of predefinedoutput transistors

Large choice for simple cells

Small choice for complexcells

Extra large choice forINV/BUF (load adaptation)

18/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryBuffering

Cell category Cell listADD X1,X2,X4AND X1,X2,X4,X6,X8AO X2,X2,X4BUF X2,X3,. . .,X16,X20FF X1,X2,X4,X8INV X2,X3,. . .,X16,X20MX X1,X2,X4NAND X1,X2,X4,X6,X8NOR X1,X2,X4,X6,X8OA X1,X2,X4OR X1,X2,X4,X6,X8TLAT X1,X2,X4,X6,X8XNOR X1,X2,X4XOR X1,X2,X4

For synthesis and P&R timingoptimisation.

No way to resize transistors

Growing sizes of predefinedoutput transistors

Large choice for simple cells

Small choice for complexcells

Extra large choice forINV/BUF (load adaptation)

18/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryBuffering

Cell category Cell listADD X1,X2,X4AND X1,X2,X4,X6,X8AO X2,X2,X4BUF X2,X3,. . .,X16,X20FF X1,X2,X4,X8INV X2,X3,. . .,X16,X20MX X1,X2,X4NAND X1,X2,X4,X6,X8NOR X1,X2,X4,X6,X8OA X1,X2,X4OR X1,X2,X4,X6,X8TLAT X1,X2,X4,X6,X8XNOR X1,X2,X4XOR X1,X2,X4

For synthesis and P&R timingoptimisation.

No way to resize transistors

Growing sizes of predefinedoutput transistors

Large choice for simple cells

Small choice for complexcells

Extra large choice forINV/BUF (load adaptation)

18/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryBuffering

Cell category Cell listADD X1,X2,X4AND X1,X2,X4,X6,X8AO X2,X2,X4BUF X2,X3,. . .,X16,X20FF X1,X2,X4,X8INV X2,X3,. . .,X16,X20MX X1,X2,X4NAND X1,X2,X4,X6,X8NOR X1,X2,X4,X6,X8OA X1,X2,X4OR X1,X2,X4,X6,X8TLAT X1,X2,X4,X6,X8XNOR X1,X2,X4XOR X1,X2,X4

For synthesis and P&R timingoptimisation.

No way to resize transistors

Growing sizes of predefinedoutput transistors

Large choice for simple cells

Small choice for complexcells

Extra large choice forINV/BUF (load adaptation)

18/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryBuffering

Cell category Cell listADD X1,X2,X4AND X1,X2,X4,X6,X8AO X2,X2,X4BUF X2,X3,. . .,X16,X20FF X1,X2,X4,X8INV X2,X3,. . .,X16,X20MX X1,X2,X4NAND X1,X2,X4,X6,X8NOR X1,X2,X4,X6,X8OA X1,X2,X4OR X1,X2,X4,X6,X8TLAT X1,X2,X4,X6,X8XNOR X1,X2,X4XOR X1,X2,X4

For synthesis and P&R timingoptimisation.

No way to resize transistors

Growing sizes of predefinedoutput transistors

Large choice for simple cells

Small choice for complexcells

Extra large choice forINV/BUF (load adaptation)

18/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryBuffering

Cell category Cell listADD X1,X2,X4AND X1,X2,X4,X6,X8AO X2,X2,X4BUF X2,X3,. . .,X16,X20FF X1,X2,X4,X8INV X2,X3,. . .,X16,X20MX X1,X2,X4NAND X1,X2,X4,X6,X8NOR X1,X2,X4,X6,X8OA X1,X2,X4OR X1,X2,X4,X6,X8TLAT X1,X2,X4,X6,X8XNOR X1,X2,X4XOR X1,X2,X4

For synthesis and P&R timingoptimisation.

No way to resize transistors

Growing sizes of predefinedoutput transistors

Large choice for simple cells

Small choice for complexcells

Extra large choice forINV/BUF (load adaptation)

18/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpeed / Dynamic power / Leakage power trade-off

Several versions of the library with the same cell layout.Based on the available transistor threshold choice.A "Standard VT" version for general purpose logic.A low leakage version using "High VT" transistors butslower gates...A high speed version using "Low VT" transistors but moreleakage...Synthesizer strategy :

• Use high speed gates, if needed, on critical paths.• Use low leakage gates on paths with relaxed timing

constraints.

"Backbias" versions used to dynamically adapt speed toexternal conditions.

19/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpeed / Dynamic power / Leakage power trade-off

Several versions of the library with the same cell layout.Based on the available transistor threshold choice.A "Standard VT" version for general purpose logic.A low leakage version using "High VT" transistors butslower gates...A high speed version using "Low VT" transistors but moreleakage...Synthesizer strategy :

• Use high speed gates, if needed, on critical paths.• Use low leakage gates on paths with relaxed timing

constraints.

"Backbias" versions used to dynamically adapt speed toexternal conditions.

19/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpeed / Dynamic power / Leakage power trade-off

Several versions of the library with the same cell layout.Based on the available transistor threshold choice.A "Standard VT" version for general purpose logic.A low leakage version using "High VT" transistors butslower gates...A high speed version using "Low VT" transistors but moreleakage...Synthesizer strategy :

• Use high speed gates, if needed, on critical paths.• Use low leakage gates on paths with relaxed timing

constraints.

"Backbias" versions used to dynamically adapt speed toexternal conditions.

19/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpeed / Dynamic power / Leakage power trade-off

Several versions of the library with the same cell layout.Based on the available transistor threshold choice.A "Standard VT" version for general purpose logic.A low leakage version using "High VT" transistors butslower gates...A high speed version using "Low VT" transistors but moreleakage...Synthesizer strategy :

• Use high speed gates, if needed, on critical paths.• Use low leakage gates on paths with relaxed timing

constraints.

"Backbias" versions used to dynamically adapt speed toexternal conditions.

19/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpeed / Dynamic power / Leakage power trade-off

Several versions of the library with the same cell layout.Based on the available transistor threshold choice.A "Standard VT" version for general purpose logic.A low leakage version using "High VT" transistors butslower gates...A high speed version using "Low VT" transistors but moreleakage...Synthesizer strategy :

• Use high speed gates, if needed, on critical paths.• Use low leakage gates on paths with relaxed timing

constraints.

"Backbias" versions used to dynamically adapt speed toexternal conditions.

19/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpeed / Dynamic power / Leakage power trade-off

Several versions of the library with the same cell layout.Based on the available transistor threshold choice.A "Standard VT" version for general purpose logic.A low leakage version using "High VT" transistors butslower gates...A high speed version using "Low VT" transistors but moreleakage...Synthesizer strategy :

• Use high speed gates, if needed, on critical paths.• Use low leakage gates on paths with relaxed timing

constraints.

"Backbias" versions used to dynamically adapt speed toexternal conditions.

19/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpeed / Dynamic power / Leakage power trade-off

Several versions of the library with the same cell layout.Based on the available transistor threshold choice.A "Standard VT" version for general purpose logic.A low leakage version using "High VT" transistors butslower gates...A high speed version using "Low VT" transistors but moreleakage...Synthesizer strategy :

• Use high speed gates, if needed, on critical paths.• Use low leakage gates on paths with relaxed timing

constraints.

"Backbias" versions used to dynamically adapt speed toexternal conditions.

19/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : clock tree, delay cells, clock gating, LowPo-wer Cells. . .

During synthesis : clock signals are considered as ideal clocks,the designer defines expected clock properties (period, skew)

Based on activity simulation, synthesis tool may insert "clockgating cells" in order to minimize power consumption

During P&R phase, a clock tree is generated by the tools in orderto full-fill the expected behavior. Specific clock buffers, withspecific timing constraints are used (very short transition time)

The P&R tool may insert "delay cells" in order to full-fill "holdtiming" constraints (course between clk and data between Dflip-flops

In a "multi-domain power supply" designs, "level adapter cells"are inserted between cells of different power domains, "powerswitch cells" are inserted in order to switch on/off completeblocks.

20/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : clock tree, delay cells, clock gating, LowPo-wer Cells. . .

During synthesis : clock signals are considered as ideal clocks,the designer defines expected clock properties (period, skew)

Based on activity simulation, synthesis tool may insert "clockgating cells" in order to minimize power consumption

During P&R phase, a clock tree is generated by the tools in orderto full-fill the expected behavior. Specific clock buffers, withspecific timing constraints are used (very short transition time)

The P&R tool may insert "delay cells" in order to full-fill "holdtiming" constraints (course between clk and data between Dflip-flops

In a "multi-domain power supply" designs, "level adapter cells"are inserted between cells of different power domains, "powerswitch cells" are inserted in order to switch on/off completeblocks.

20/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : clock tree, delay cells, clock gating, LowPo-wer Cells. . .

During synthesis : clock signals are considered as ideal clocks,the designer defines expected clock properties (period, skew)

Based on activity simulation, synthesis tool may insert "clockgating cells" in order to minimize power consumption

During P&R phase, a clock tree is generated by the tools in orderto full-fill the expected behavior. Specific clock buffers, withspecific timing constraints are used (very short transition time)

The P&R tool may insert "delay cells" in order to full-fill "holdtiming" constraints (course between clk and data between Dflip-flops

In a "multi-domain power supply" designs, "level adapter cells"are inserted between cells of different power domains, "powerswitch cells" are inserted in order to switch on/off completeblocks.

20/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : clock tree, delay cells, clock gating, LowPo-wer Cells. . .

During synthesis : clock signals are considered as ideal clocks,the designer defines expected clock properties (period, skew)

Based on activity simulation, synthesis tool may insert "clockgating cells" in order to minimize power consumption

During P&R phase, a clock tree is generated by the tools in orderto full-fill the expected behavior. Specific clock buffers, withspecific timing constraints are used (very short transition time)

The P&R tool may insert "delay cells" in order to full-fill "holdtiming" constraints (course between clk and data between Dflip-flops

In a "multi-domain power supply" designs, "level adapter cells"are inserted between cells of different power domains, "powerswitch cells" are inserted in order to switch on/off completeblocks.

20/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : clock tree, delay cells, clock gating, LowPo-wer Cells. . .

During synthesis : clock signals are considered as ideal clocks,the designer defines expected clock properties (period, skew)

Based on activity simulation, synthesis tool may insert "clockgating cells" in order to minimize power consumption

During P&R phase, a clock tree is generated by the tools in orderto full-fill the expected behavior. Specific clock buffers, withspecific timing constraints are used (very short transition time)

The P&R tool may insert "delay cells" in order to full-fill "holdtiming" constraints (course between clk and data between Dflip-flops

In a "multi-domain power supply" designs, "level adapter cells"are inserted between cells of different power domains, "powerswitch cells" are inserted in order to switch on/off completeblocks.

20/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : physical only cells. . .

Physical only cells are cells that have no logic behavior. Theyare only needed by physical constraints of the layout

Filler cells are used to fill holes between standard cells. Thisensures, supply and well continuity.

Well tap cells are used to connect Nwell and Pwell to the powersupply and the ground.

Antenna cells are used to limit the so called Antenna Effectduring manufacturing

Decap cells are used to limit ground and power bounce oftencalled IRdrop.

. . .

21/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : physical only cells. . .

Physical only cells are cells that have no logic behavior. Theyare only needed by physical constraints of the layout

Filler cells are used to fill holes between standard cells. Thisensures, supply and well continuity.

Well tap cells are used to connect Nwell and Pwell to the powersupply and the ground.

Antenna cells are used to limit the so called Antenna Effectduring manufacturing

Decap cells are used to limit ground and power bounce oftencalled IRdrop.

. . .

21/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : physical only cells. . .

Physical only cells are cells that have no logic behavior. Theyare only needed by physical constraints of the layout

Filler cells are used to fill holes between standard cells. Thisensures, supply and well continuity.

Well tap cells are used to connect Nwell and Pwell to the powersupply and the ground.

Antenna cells are used to limit the so called Antenna Effectduring manufacturing

Decap cells are used to limit ground and power bounce oftencalled IRdrop.

. . .

21/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : physical only cells. . .

Physical only cells are cells that have no logic behavior. Theyare only needed by physical constraints of the layout

Filler cells are used to fill holes between standard cells. Thisensures, supply and well continuity.

Well tap cells are used to connect Nwell and Pwell to the powersupply and the ground.

Antenna cells are used to limit the so called Antenna Effectduring manufacturing

Decap cells are used to limit ground and power bounce oftencalled IRdrop.

. . .

21/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : physical only cells. . .

Physical only cells are cells that have no logic behavior. Theyare only needed by physical constraints of the layout

Filler cells are used to fill holes between standard cells. Thisensures, supply and well continuity.

Well tap cells are used to connect Nwell and Pwell to the powersupply and the ground.

Antenna cells are used to limit the so called Antenna Effectduring manufacturing

Decap cells are used to limit ground and power bounce oftencalled IRdrop.

. . .

21/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell librarySpecial purpose cells : physical only cells. . .

Physical only cells are cells that have no logic behavior. Theyare only needed by physical constraints of the layout

Filler cells are used to fill holes between standard cells. Thisensures, supply and well continuity.

Well tap cells are used to connect Nwell and Pwell to the powersupply and the ground.

Antenna cells are used to limit the so called Antenna Effectduring manufacturing

Decap cells are used to limit ground and power bounce oftencalled IRdrop.

. . .

21/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryRefresh on Antenna Effect. . .

During manufacturing phases, plasma etching leads to chargeaccumulation in conductor layers already created.

If this layers are floating (not connected to drain/sources oftransistors or wells) and connected to gates then gate oxide maybreak ! !

Place and route tools are able to evaluate and correct thisproblem :

Evaluation : estimate the risk of breakdown, based on areas ofmetal/gates/implants connected to the conductor.

Correction1 : Add and connect specific diodes (Antenna cells)in order to avoid floating layers during manufacturing

Correction2 : Modify routing in order to connect long lines ofmetal only during the last steps of manufacturing.

22/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryRefresh on Antenna Effect. . .

During manufacturing phases, plasma etching leads to chargeaccumulation in conductor layers already created.

If this layers are floating (not connected to drain/sources oftransistors or wells) and connected to gates then gate oxide maybreak ! !

Place and route tools are able to evaluate and correct thisproblem :

Evaluation : estimate the risk of breakdown, based on areas ofmetal/gates/implants connected to the conductor.

Correction1 : Add and connect specific diodes (Antenna cells)in order to avoid floating layers during manufacturing

Correction2 : Modify routing in order to connect long lines ofmetal only during the last steps of manufacturing.

22/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryRefresh on Antenna Effect. . .

During manufacturing phases, plasma etching leads to chargeaccumulation in conductor layers already created.

If this layers are floating (not connected to drain/sources oftransistors or wells) and connected to gates then gate oxide maybreak ! !

Place and route tools are able to evaluate and correct thisproblem :

Evaluation : estimate the risk of breakdown, based on areas ofmetal/gates/implants connected to the conductor.

Correction1 : Add and connect specific diodes (Antenna cells)in order to avoid floating layers during manufacturing

Correction2 : Modify routing in order to connect long lines ofmetal only during the last steps of manufacturing.

22/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryRefresh on Antenna Effect. . .

During manufacturing phases, plasma etching leads to chargeaccumulation in conductor layers already created.

If this layers are floating (not connected to drain/sources oftransistors or wells) and connected to gates then gate oxide maybreak ! !

Place and route tools are able to evaluate and correct thisproblem :

Evaluation : estimate the risk of breakdown, based on areas ofmetal/gates/implants connected to the conductor.

Correction1 : Add and connect specific diodes (Antenna cells)in order to avoid floating layers during manufacturing

Correction2 : Modify routing in order to connect long lines ofmetal only during the last steps of manufacturing.

22/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryRefresh on Antenna Effect. . .

During manufacturing phases, plasma etching leads to chargeaccumulation in conductor layers already created.

If this layers are floating (not connected to drain/sources oftransistors or wells) and connected to gates then gate oxide maybreak ! !

Place and route tools are able to evaluate and correct thisproblem :

Evaluation : estimate the risk of breakdown, based on areas ofmetal/gates/implants connected to the conductor.

Correction1 : Add and connect specific diodes (Antenna cells)in order to avoid floating layers during manufacturing

Correction2 : Modify routing in order to connect long lines ofmetal only during the last steps of manufacturing.

22/69 ICS904-EN2-L4 Yves MATHIEU

Standard cell libraryRefresh on Antenna Effect. . .

During manufacturing phases, plasma etching leads to chargeaccumulation in conductor layers already created.

If this layers are floating (not connected to drain/sources oftransistors or wells) and connected to gates then gate oxide maybreak ! !

Place and route tools are able to evaluate and correct thisproblem :

Evaluation : estimate the risk of breakdown, based on areas ofmetal/gates/implants connected to the conductor.

Correction1 : Add and connect specific diodes (Antenna cells)in order to avoid floating layers during manufacturing

Correction2 : Modify routing in order to connect long lines ofmetal only during the last steps of manufacturing.

22/69 ICS904-EN2-L4 Yves MATHIEU

Outline

Bases of CMOS logic

Standard cell design

Standard cell libraries

Standard Cell characterization

Digital Integrated Circuit Testing

Place and route flow

23/69 ICS904-EN2-L4 Yves MATHIEU

Standard Cell characterization"Liberty" files

Give all necessary informations to the synthesis and P&RtoolsA de-facto standard : "Liberty" files from "Synopsys"company.For each cell :

• Logic behavior• Area• Power Consumption• Timing

But also, for a whole library :• Characterization conditions (Process, Supply Voltage ,

Temperature)• Characterization conditions (Max rising time, Max

capacitances,...)• Statistical capacitance model for wiring...

24/69 ICS904-EN2-L4 Yves MATHIEU

Standard Cell characterization"Liberty" files

Give all necessary informations to the synthesis and P&RtoolsA de-facto standard : "Liberty" files from "Synopsys"company.For each cell :

• Logic behavior• Area• Power Consumption• Timing

But also, for a whole library :• Characterization conditions (Process, Supply Voltage ,

Temperature)• Characterization conditions (Max rising time, Max

capacitances,...)• Statistical capacitance model for wiring...

24/69 ICS904-EN2-L4 Yves MATHIEU

Standard Cell characterization"Liberty" files

Give all necessary informations to the synthesis and P&RtoolsA de-facto standard : "Liberty" files from "Synopsys"company.For each cell :

• Logic behavior• Area• Power Consumption• Timing

But also, for a whole library :• Characterization conditions (Process, Supply Voltage ,

Temperature)• Characterization conditions (Max rising time, Max

capacitances,...)• Statistical capacitance model for wiring...

24/69 ICS904-EN2-L4 Yves MATHIEU

Standard Cell characterization"Liberty" files

Give all necessary informations to the synthesis and P&RtoolsA de-facto standard : "Liberty" files from "Synopsys"company.For each cell :

• Logic behavior• Area• Power Consumption• Timing

But also, for a whole library :• Characterization conditions (Process, Supply Voltage ,

Temperature)• Characterization conditions (Max rising time, Max

capacitances,...)• Statistical capacitance model for wiring...

24/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell Library"Corners" : Process, Voltage, Temperature

define(process_corner, operating_conditions, string);operating_conditions (typical) {

process_corner : "TypTyp";process : 1.00;voltage : 1.10;temperature : 25.00;tree_type : balanced_tree;

}default_operating_conditions : typical;

Several liberty files may be loaded at the same time by the tools(synthesis, P&R)

For each kind of analysis, the appropriate "PVT" corner ischoosen by the tool.

For example a "worst case" corner is used for Tsetup analysis.

For example a "best case" corner is used for Thold analysis.25/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell Library"Corners" : Process, Voltage, Temperature

define(process_corner, operating_conditions, string);operating_conditions (typical) {

process_corner : "TypTyp";process : 1.00;voltage : 1.10;temperature : 25.00;tree_type : balanced_tree;

}default_operating_conditions : typical;

Several liberty files may be loaded at the same time by the tools(synthesis, P&R)

For each kind of analysis, the appropriate "PVT" corner ischoosen by the tool.

For example a "worst case" corner is used for Tsetup analysis.

For example a "best case" corner is used for Thold analysis.25/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell Library"Corners" : Process, Voltage, Temperature

define(process_corner, operating_conditions, string);operating_conditions (typical) {

process_corner : "TypTyp";process : 1.00;voltage : 1.10;temperature : 25.00;tree_type : balanced_tree;

}default_operating_conditions : typical;

Several liberty files may be loaded at the same time by the tools(synthesis, P&R)

For each kind of analysis, the appropriate "PVT" corner ischoosen by the tool.

For example a "worst case" corner is used for Tsetup analysis.

For example a "best case" corner is used for Thold analysis.25/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell Library"Corners" : Process, Voltage, Temperature

define(process_corner, operating_conditions, string);operating_conditions (typical) {

process_corner : "TypTyp";process : 1.00;voltage : 1.10;temperature : 25.00;tree_type : balanced_tree;

}default_operating_conditions : typical;

Several liberty files may be loaded at the same time by the tools(synthesis, P&R)

For each kind of analysis, the appropriate "PVT" corner ischoosen by the tool.

For example a "worst case" corner is used for Tsetup analysis.

For example a "best case" corner is used for Thold analysis.25/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : global data

cell (NAND2_X4) {drive_strength : 4;area : 2.394000;pg_pin(VDD) {voltage_name : VDD;pg_type : primary_power;

}...

Global info on the cellGeneral info on output buffers .(integer 1,2,4,8...)The synthesizer uses area info in order to optimize globalsynthesized area.All signals should be known, even supplies and grounds.

26/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : global data

cell (NAND2_X4) {drive_strength : 4;area : 2.394000;pg_pin(VDD) {voltage_name : VDD;pg_type : primary_power;

}...

Global info on the cellGeneral info on output buffers .(integer 1,2,4,8...)The synthesizer uses area info in order to optimize globalsynthesized area.All signals should be known, even supplies and grounds.

26/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : global data

cell (NAND2_X4) {drive_strength : 4;area : 2.394000;pg_pin(VDD) {voltage_name : VDD;pg_type : primary_power;

}...

Global info on the cellGeneral info on output buffers .(integer 1,2,4,8...)The synthesizer uses area info in order to optimize globalsynthesized area.All signals should be known, even supplies and grounds.

26/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : global data

cell (NAND2_X4) {drive_strength : 4;area : 2.394000;pg_pin(VDD) {voltage_name : VDD;pg_type : primary_power;

}...

Global info on the cellGeneral info on output buffers .(integer 1,2,4,8...)The synthesizer uses area info in order to optimize globalsynthesized area.All signals should be known, even supplies and grounds.

26/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : Leakage power

cell_leakage_power : 69.573240;leakage_power () {when : "!A1 & !A2";value : 13.930180;

}leakage_power () {when : "!A1 & A2";value : 99.197450;

}leakage_power () {when...

The leakage power(Watts...) of the cell is afunction of the internalstate of the cellOne mean value4 values for the 4 entries inthe truth table of the gate

27/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : Leakage power

cell_leakage_power : 69.573240;leakage_power () {when : "!A1 & !A2";value : 13.930180;

}leakage_power () {when : "!A1 & A2";value : 99.197450;

}leakage_power () {when...

The leakage power(Watts...) of the cell is afunction of the internalstate of the cellOne mean value4 values for the 4 entries inthe truth table of the gate

27/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : Leakage power

cell_leakage_power : 69.573240;leakage_power () {when : "!A1 & !A2";value : 13.930180;

}leakage_power () {when : "!A1 & A2";value : 99.197450;

}leakage_power () {when...

The leakage power(Watts...) of the cell is afunction of the internalstate of the cellOne mean value4 values for the 4 entries inthe truth table of the gate

27/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An input signal : A1

pin (A1) {direction : input;related_power_pin : "VDD";related_ground_pin : "VSS";capacitance : 5.954965;fall_capacitance : 5.698021;rise_capacitance : 5.954965;

}

A1 is an inputA1 has an inputcapacitance.A mean value of the inputcapacitance is givenAn input capacitance whenA1 is falling.An different inputcapacitance when A1 isrising.

QUESTION : Why two different input capacitances?

28/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An input signal : A1

pin (A1) {direction : input;related_power_pin : "VDD";related_ground_pin : "VSS";capacitance : 5.954965;fall_capacitance : 5.698021;rise_capacitance : 5.954965;

}

A1 is an inputA1 has an inputcapacitance.A mean value of the inputcapacitance is givenAn input capacitance whenA1 is falling.An different inputcapacitance when A1 isrising.

QUESTION : Why two different input capacitances?

28/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An input signal : A1

pin (A1) {direction : input;related_power_pin : "VDD";related_ground_pin : "VSS";capacitance : 5.954965;fall_capacitance : 5.698021;rise_capacitance : 5.954965;

}

A1 is an inputA1 has an inputcapacitance.A mean value of the inputcapacitance is givenAn input capacitance whenA1 is falling.An different inputcapacitance when A1 isrising.

QUESTION : Why two different input capacitances?

28/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An input signal : A1

pin (A1) {direction : input;related_power_pin : "VDD";related_ground_pin : "VSS";capacitance : 5.954965;fall_capacitance : 5.698021;rise_capacitance : 5.954965;

}

A1 is an inputA1 has an inputcapacitance.A mean value of the inputcapacitance is givenAn input capacitance whenA1 is falling.An different inputcapacitance when A1 isrising.

QUESTION : Why two different input capacitances?

28/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An input signal : A1

pin (A1) {direction : input;related_power_pin : "VDD";related_ground_pin : "VSS";capacitance : 5.954965;fall_capacitance : 5.698021;rise_capacitance : 5.954965;

}

A1 is an inputA1 has an inputcapacitance.A mean value of the inputcapacitance is givenAn input capacitance whenA1 is falling.An different inputcapacitance when A1 isrising.

QUESTION : Why two different input capacitances?

28/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An input signal : A1

pin (A1) {direction : input;related_power_pin : "VDD";related_ground_pin : "VSS";capacitance : 5.954965;fall_capacitance : 5.698021;rise_capacitance : 5.954965;

}

A1 is an inputA1 has an inputcapacitance.A mean value of the inputcapacitance is givenAn input capacitance whenA1 is falling.An different inputcapacitance when A1 isrising.

QUESTION : Why two different input capacitances?

28/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An output signal : ZN

pin (ZN) {direction : output;related_power_pin : "VDD";related_ground_pin : "VSS";max_capacitance : 237.427000;function : "!(A1 & A2)";

ZN is an outputThe boolean equation isgiven (for synthesis...)Remember that theNAND2_X4 gate has amax fanout of 4.The max capacitance for aX1 gate is 59.3567fFThe max load capacitancea X4 gate is four times thisvalue.

QUESTION : Is it coherent with the max transition time?

29/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An output signal : ZN

pin (ZN) {direction : output;related_power_pin : "VDD";related_ground_pin : "VSS";max_capacitance : 237.427000;function : "!(A1 & A2)";

ZN is an outputThe boolean equation isgiven (for synthesis...)Remember that theNAND2_X4 gate has amax fanout of 4.The max capacitance for aX1 gate is 59.3567fFThe max load capacitancea X4 gate is four times thisvalue.

QUESTION : Is it coherent with the max transition time?

29/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An output signal : ZN

pin (ZN) {direction : output;related_power_pin : "VDD";related_ground_pin : "VSS";max_capacitance : 237.427000;function : "!(A1 & A2)";

ZN is an outputThe boolean equation isgiven (for synthesis...)Remember that theNAND2_X4 gate has amax fanout of 4.The max capacitance for aX1 gate is 59.3567fFThe max load capacitancea X4 gate is four times thisvalue.

QUESTION : Is it coherent with the max transition time?

29/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An output signal : ZN

pin (ZN) {direction : output;related_power_pin : "VDD";related_ground_pin : "VSS";max_capacitance : 237.427000;function : "!(A1 & A2)";

ZN is an outputThe boolean equation isgiven (for synthesis...)Remember that theNAND2_X4 gate has amax fanout of 4.The max capacitance for aX1 gate is 59.3567fFThe max load capacitancea X4 gate is four times thisvalue.

QUESTION : Is it coherent with the max transition time?

29/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An output signal : ZN

pin (ZN) {direction : output;related_power_pin : "VDD";related_ground_pin : "VSS";max_capacitance : 237.427000;function : "!(A1 & A2)";

ZN is an outputThe boolean equation isgiven (for synthesis...)Remember that theNAND2_X4 gate has amax fanout of 4.The max capacitance for aX1 gate is 59.3567fFThe max load capacitancea X4 gate is four times thisvalue.

QUESTION : Is it coherent with the max transition time?

29/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : An output signal : ZN

pin (ZN) {direction : output;related_power_pin : "VDD";related_ground_pin : "VSS";max_capacitance : 237.427000;function : "!(A1 & A2)";

ZN is an outputThe boolean equation isgiven (for synthesis...)Remember that theNAND2_X4 gate has amax fanout of 4.The max capacitance for aX1 gate is 59.3567fFThe max load capacitancea X4 gate is four times thisvalue.

QUESTION : Is it coherent with the max transition time?

29/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

related_pin : which is the input pin causing the outputtransition?timing_sense : The output transition has not the samedirection as the input transition.cell_fall : Propagation time for a falling output.Reference to the Timing_7_7 (transition,load) template.First index related to line. Second Index related to column.

30/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

related_pin : which is the input pin causing the outputtransition?timing_sense : The output transition has not the samedirection as the input transition.cell_fall : Propagation time for a falling output.Reference to the Timing_7_7 (transition,load) template.First index related to line. Second Index related to column.

30/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

related_pin : which is the input pin causing the outputtransition?timing_sense : The output transition has not the samedirection as the input transition.cell_fall : Propagation time for a falling output.Reference to the Timing_7_7 (transition,load) template.First index related to line. Second Index related to column.

30/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

related_pin : which is the input pin causing the outputtransition?timing_sense : The output transition has not the samedirection as the input transition.cell_fall : Propagation time for a falling output.Reference to the Timing_7_7 (transition,load) template.First index related to line. Second Index related to column.

30/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

related_pin : which is the input pin causing the outputtransition?timing_sense : The output transition has not the samedirection as the input transition.cell_fall : Propagation time for a falling output.Reference to the Timing_7_7 (transition,load) template.First index related to line. Second Index related to column.

30/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

Index values are redefined.Note : max transition < default_max_transition.Note : max capa < max_capacitance.Same kind of table for a rising transition of the output.Same kind of table for each path from any input to anyoutput.

31/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

Index values are redefined.Note : max transition < default_max_transition.Note : max capa < max_capacitance.Same kind of table for a rising transition of the output.Same kind of table for each path from any input to anyoutput.

31/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

Index values are redefined.Note : max transition < default_max_transition.Note : max capa < max_capacitance.Same kind of table for a rising transition of the output.Same kind of table for each path from any input to anyoutput.

31/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

Index values are redefined.Note : max transition < default_max_transition.Note : max capa < max_capacitance.Same kind of table for a rising transition of the output.Same kind of table for each path from any input to anyoutput.

31/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : propagation time between A1 and ZN

timing () {related_pin : "A1";timing_sense : negative_unate;cell_fall(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00616709,0.00999692,0.0139268,0.0217239,0.0372647,0.0683098,0.130380", \

"0.00734947,0.0112111,0.0151774,0.0230153,0.0385880,0.0696532,0.131734", \"0.00995234,0.0155306,0.0201539,0.0279856,0.0435159,0.0745711,0.136650", \"0.0111666,0.0189948,0.0256394,0.0365212,0.0535191,0.0842981,0.146225", \"0.0108485,0.0208434,0.0293531,0.0434564,0.0658692,0.100138,0.161536", \"0.00880319,0.0209282,0.0312687,0.0484222,0.0759517,0.118635,0.183723", \"0.00494015,0.0190727,0.0312259,0.0514041,0.0838078,0.134588,0.211792");

}cell_rise(Timing_7_7) {

Index values are redefined.Note : max transition < default_max_transition.Note : max capa < max_capacitance.Same kind of table for a rising transition of the output.Same kind of table for each path from any input to anyoutput.

31/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : Falling Transition time of ZN signal

fall_transition(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00313418,0.00633765,0.00970606,0.0164353,0.0298921,0.0567985,0.110610", \

"0.00315002,0.00633771,0.00970602,0.0164361,0.0298928,0.0567975,0.110614", \"0.00594783,0.00855601,0.0108711,0.0165314,0.0298930,0.0567989,0.110613", \"0.0100557,0.0135596,0.0166079,0.0217381,0.0314545,0.0568000,0.110613", \"0.0155905,0.0199433,0.0237401,0.0301861,0.0406656,0.0599695,0.110612", \"0.0227162,0.0279150,0.0324341,0.0400918,0.0526945,0.0727865,0.113484", \"0.0316036,0.0376134,0.0428795,0.0517033,0.0662647,0.0896769,0.127281");

}

Reference to the Timing_7_7 (transition,load) templateSame kind of table for a rising transition of the output.Coherency : The maximum transition time (0.127281) isless than the default_max_transition

32/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : Falling Transition time of ZN signal

fall_transition(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00313418,0.00633765,0.00970606,0.0164353,0.0298921,0.0567985,0.110610", \

"0.00315002,0.00633771,0.00970602,0.0164361,0.0298928,0.0567975,0.110614", \"0.00594783,0.00855601,0.0108711,0.0165314,0.0298930,0.0567989,0.110613", \"0.0100557,0.0135596,0.0166079,0.0217381,0.0314545,0.0568000,0.110613", \"0.0155905,0.0199433,0.0237401,0.0301861,0.0406656,0.0599695,0.110612", \"0.0227162,0.0279150,0.0324341,0.0400918,0.0526945,0.0727865,0.113484", \"0.0316036,0.0376134,0.0428795,0.0517033,0.0662647,0.0896769,0.127281");

}

Reference to the Timing_7_7 (transition,load) templateSame kind of table for a rising transition of the output.Coherency : The maximum transition time (0.127281) isless than the default_max_transition

32/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : Falling Transition time of ZN signal

fall_transition(Timing_7_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.00313418,0.00633765,0.00970606,0.0164353,0.0298921,0.0567985,0.110610", \

"0.00315002,0.00633771,0.00970602,0.0164361,0.0298928,0.0567975,0.110614", \"0.00594783,0.00855601,0.0108711,0.0165314,0.0298930,0.0567989,0.110613", \"0.0100557,0.0135596,0.0166079,0.0217381,0.0314545,0.0568000,0.110613", \"0.0155905,0.0199433,0.0237401,0.0301861,0.0406656,0.0599695,0.110612", \"0.0227162,0.0279150,0.0324341,0.0400918,0.0526945,0.0727865,0.113484", \"0.0316036,0.0376134,0.0428795,0.0517033,0.0662647,0.0896769,0.127281");

}

Reference to the Timing_7_7 (transition,load) templateSame kind of table for a rising transition of the output.Coherency : The maximum transition time (0.127281) isless than the default_max_transition

32/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : Internal Dynamic power consumption of the gate

internal_power () {related_pin : "A1";fall_power(Power_7_7) {

index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.795787,0.940878,0.980508,1.014321,1.042872,1.047780,1.052940", \

"0.527188,0.716998,0.831193,0.921873,0.985745,1.018615,1.041402", \"0.838523,0.654409,0.697793,0.801639,0.888976,0.958862,1.007789", \"2.454897,1.823314,1.436914,1.141771,1.072669,1.059437,1.049585", \"5.068604,4.189900,3.531058,2.676582,1.933285,1.575694,1.350992", \"8.605884,7.786085,6.914839,5.578610,4.057340,2.851663,2.142791", \"13.235730,12.471150,11.622380,9.965538,7.625804,5.289704,3.673908");

}

Internal energy consumption (Joules...) used for a falltransition of Z1 caused by a A1 transition .Correlated with the input transition time and the capacitiveload.All cases should be tabulated...Warning : This doesn’t take into account the energy storedin the load capacitor itself.Question : How to explain this kind of measurements?.

33/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : Internal Dynamic power consumption of the gate

internal_power () {related_pin : "A1";fall_power(Power_7_7) {

index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.795787,0.940878,0.980508,1.014321,1.042872,1.047780,1.052940", \

"0.527188,0.716998,0.831193,0.921873,0.985745,1.018615,1.041402", \"0.838523,0.654409,0.697793,0.801639,0.888976,0.958862,1.007789", \"2.454897,1.823314,1.436914,1.141771,1.072669,1.059437,1.049585", \"5.068604,4.189900,3.531058,2.676582,1.933285,1.575694,1.350992", \"8.605884,7.786085,6.914839,5.578610,4.057340,2.851663,2.142791", \"13.235730,12.471150,11.622380,9.965538,7.625804,5.289704,3.673908");

}

Internal energy consumption (Joules...) used for a falltransition of Z1 caused by a A1 transition .Correlated with the input transition time and the capacitiveload.All cases should be tabulated...Warning : This doesn’t take into account the energy storedin the load capacitor itself.Question : How to explain this kind of measurements?.

33/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryNAND2_X4 : Internal Dynamic power consumption of the gate

internal_power () {related_pin : "A1";fall_power(Power_7_7) {

index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");index_2 ("0.365616,7.419590,14.839200,29.678400,59.356800,118.714000,237.427000");values ("0.795787,0.940878,0.980508,1.014321,1.042872,1.047780,1.052940", \

"0.527188,0.716998,0.831193,0.921873,0.985745,1.018615,1.041402", \"0.838523,0.654409,0.697793,0.801639,0.888976,0.958862,1.007789", \"2.454897,1.823314,1.436914,1.141771,1.072669,1.059437,1.049585", \"5.068604,4.189900,3.531058,2.676582,1.933285,1.575694,1.350992", \"8.605884,7.786085,6.914839,5.578610,4.057340,2.851663,2.142791", \"13.235730,12.471150,11.622380,9.965538,7.625804,5.289704,3.673908");

}

Internal energy consumption (Joules...) used for a falltransition of Z1 caused by a A1 transition .Correlated with the input transition time and the capacitiveload.All cases should be tabulated...Warning : This doesn’t take into account the energy storedin the load capacitor itself.Question : How to explain this kind of measurements?.

33/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Global data

cell (DFF_X2) {drive_strength : 2;ff ("IQ" , "IQN") {next_state : "D";clocked_on : "CK";

}

Global information on the cellBuffer size X2The gate is a D flip-flop working on the rising edge of CKThe gate has two outputs Q and QN

34/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Global data

cell (DFF_X2) {drive_strength : 2;ff ("IQ" , "IQN") {next_state : "D";clocked_on : "CK";

}

Global information on the cellBuffer size X2The gate is a D flip-flop working on the rising edge of CKThe gate has two outputs Q and QN

34/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Global data

cell (DFF_X2) {drive_strength : 2;ff ("IQ" , "IQN") {next_state : "D";clocked_on : "CK";

}

Global information on the cellBuffer size X2The gate is a D flip-flop working on the rising edge of CKThe gate has two outputs Q and QN

34/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Global data

cell (DFF_X2) {drive_strength : 2;ff ("IQ" , "IQN") {next_state : "D";clocked_on : "CK";

}

Global information on the cellBuffer size X2The gate is a D flip-flop working on the rising edge of CKThe gate has two outputs Q and QN

34/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Leakage Power

cell_leakage_power : 115.103670;

leakage_power () {when : "!CK & !D & !Q & QN";value : 107.651390;

}leakage_power () {when : "!CK & !D & Q & !QN";value : 115.805800;

}...

The leakage power is a functionof the state of the cell.A mean value.As the cell is sequential theleakage power is also a functionof the outputs ! !.Here 8 cases have to bemeasured.

35/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Leakage Power

cell_leakage_power : 115.103670;

leakage_power () {when : "!CK & !D & !Q & QN";value : 107.651390;

}leakage_power () {when : "!CK & !D & Q & !QN";value : 115.805800;

}...

The leakage power is a functionof the state of the cell.A mean value.As the cell is sequential theleakage power is also a functionof the outputs ! !.Here 8 cases have to bemeasured.

35/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Leakage Power

cell_leakage_power : 115.103670;

leakage_power () {when : "!CK & !D & !Q & QN";value : 107.651390;

}leakage_power () {when : "!CK & !D & Q & !QN";value : 115.805800;

}...

The leakage power is a functionof the state of the cell.A mean value.As the cell is sequential theleakage power is also a functionof the outputs ! !.Here 8 cases have to bemeasured.

35/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Leakage Power

cell_leakage_power : 115.103670;

leakage_power () {when : "!CK & !D & !Q & QN";value : 107.651390;

}leakage_power () {when : "!CK & !D & Q & !QN";value : 115.805800;

}...

The leakage power is a functionof the state of the cell.A mean value.As the cell is sequential theleakage power is also a functionof the outputs ! !.Here 8 cases have to bemeasured.

35/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hold constraint on the D input

timing () {related_pin : "CK";timing_type : hold_rising;fall_constraint(Hold_3_3) {index_1 ("0.00117378,0.0449324,0.198535");index_2 ("0.00117378,0.0449324,0.198535");values ("0.000950,0.009897,0.009901", \

"0.004801,0.011035,0.005683", \"0.144217,0.153663,0.144977");

}

"Hold time" from rising of clk for arising transition of D.Tabulated (Hold_3_3)Index 1 : Transition time of DIndex 2 : Transition time of CKSame kind of table for the "SetupTime".

QUESTION : What about the output load capacitance?

36/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hold constraint on the D input

timing () {related_pin : "CK";timing_type : hold_rising;fall_constraint(Hold_3_3) {index_1 ("0.00117378,0.0449324,0.198535");index_2 ("0.00117378,0.0449324,0.198535");values ("0.000950,0.009897,0.009901", \

"0.004801,0.011035,0.005683", \"0.144217,0.153663,0.144977");

}

"Hold time" from rising of clk for arising transition of D.Tabulated (Hold_3_3)Index 1 : Transition time of DIndex 2 : Transition time of CKSame kind of table for the "SetupTime".

QUESTION : What about the output load capacitance?

36/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hold constraint on the D input

timing () {related_pin : "CK";timing_type : hold_rising;fall_constraint(Hold_3_3) {index_1 ("0.00117378,0.0449324,0.198535");index_2 ("0.00117378,0.0449324,0.198535");values ("0.000950,0.009897,0.009901", \

"0.004801,0.011035,0.005683", \"0.144217,0.153663,0.144977");

}

"Hold time" from rising of clk for arising transition of D.Tabulated (Hold_3_3)Index 1 : Transition time of DIndex 2 : Transition time of CKSame kind of table for the "SetupTime".

QUESTION : What about the output load capacitance?

36/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hold constraint on the D input

timing () {related_pin : "CK";timing_type : hold_rising;fall_constraint(Hold_3_3) {index_1 ("0.00117378,0.0449324,0.198535");index_2 ("0.00117378,0.0449324,0.198535");values ("0.000950,0.009897,0.009901", \

"0.004801,0.011035,0.005683", \"0.144217,0.153663,0.144977");

}

"Hold time" from rising of clk for arising transition of D.Tabulated (Hold_3_3)Index 1 : Transition time of DIndex 2 : Transition time of CKSame kind of table for the "SetupTime".

QUESTION : What about the output load capacitance?

36/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hold constraint on the D input

timing () {related_pin : "CK";timing_type : hold_rising;fall_constraint(Hold_3_3) {index_1 ("0.00117378,0.0449324,0.198535");index_2 ("0.00117378,0.0449324,0.198535");values ("0.000950,0.009897,0.009901", \

"0.004801,0.011035,0.005683", \"0.144217,0.153663,0.144977");

}

"Hold time" from rising of clk for arising transition of D.Tabulated (Hold_3_3)Index 1 : Transition time of DIndex 2 : Transition time of CKSame kind of table for the "SetupTime".

QUESTION : What about the output load capacitance?

36/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hold constraint on the D input

timing () {related_pin : "CK";timing_type : hold_rising;fall_constraint(Hold_3_3) {index_1 ("0.00117378,0.0449324,0.198535");index_2 ("0.00117378,0.0449324,0.198535");values ("0.000950,0.009897,0.009901", \

"0.004801,0.011035,0.005683", \"0.144217,0.153663,0.144977");

}

"Hold time" from rising of clk for arising transition of D.Tabulated (Hold_3_3)Index 1 : Transition time of DIndex 2 : Transition time of CKSame kind of table for the "SetupTime".

QUESTION : What about the output load capacitance?

36/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hidden power for a transition of D

internal_power () {

when : "!CK & !Q & QN";

fall_power(Hidden_power_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");values ("4.354644,4.333607,4.304507,4.328622,4.507989,4.894921,5.519367");

}rise_power(Hidden_power_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");values ("3.211098,3.175770,3.145376,3.177001,3.349767,3.724420,4.327453");

}

}...

Energy used for a transition of D (no transition on CLK orthe outputs)Depends only on then transition time of D.Warning : Doesnt take into account energy stored in theinput capacitance itself.4x2 cases linked to the state of the flip-flop and the valueof CK.

37/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hidden power for a transition of D

internal_power () {

when : "!CK & !Q & QN";

fall_power(Hidden_power_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");values ("4.354644,4.333607,4.304507,4.328622,4.507989,4.894921,5.519367");

}rise_power(Hidden_power_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");values ("3.211098,3.175770,3.145376,3.177001,3.349767,3.724420,4.327453");

}

}...

Energy used for a transition of D (no transition on CLK orthe outputs)Depends only on then transition time of D.Warning : Doesnt take into account energy stored in theinput capacitance itself.4x2 cases linked to the state of the flip-flop and the valueof CK.

37/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hidden power for a transition of D

internal_power () {

when : "!CK & !Q & QN";

fall_power(Hidden_power_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");values ("4.354644,4.333607,4.304507,4.328622,4.507989,4.894921,5.519367");

}rise_power(Hidden_power_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");values ("3.211098,3.175770,3.145376,3.177001,3.349767,3.724420,4.327453");

}

}...

Energy used for a transition of D (no transition on CLK orthe outputs)Depends only on then transition time of D.Warning : Doesnt take into account energy stored in theinput capacitance itself.4x2 cases linked to the state of the flip-flop and the valueof CK.

37/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Hidden power for a transition of D

internal_power () {

when : "!CK & !Q & QN";

fall_power(Hidden_power_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");values ("4.354644,4.333607,4.304507,4.328622,4.507989,4.894921,5.519367");

}rise_power(Hidden_power_7) {index_1 ("0.00117378,0.00472397,0.0171859,0.0409838,0.0780596,0.130081,0.198535");values ("3.211098,3.175770,3.145376,3.177001,3.349767,3.724420,4.327453");

}

}...

Energy used for a transition of D (no transition on CLK orthe outputs)Depends only on then transition time of D.Warning : Doesnt take into account energy stored in theinput capacitance itself.4x2 cases linked to the state of the flip-flop and the valueof CK.

37/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : CK clock constraints

...clock : true;...timing () {

related_pin : "CK";timing_type : min_pulse_width;fall_constraint(Pulse_width_3) {index_1 ("0.00117378,0.0449324,0.198535");values ("0.054590,0.069863,0.198733");}rise_constraint(Pulse_width_3) {index_1 ("0.00117378,0.0449324,0.198535");values ("0.080840,0.080924,0.198733");}

}...internal_power() {...}...

CK is clock...The minimum duration of the "1"state is tabulated.This duration is a function of thetransition time of the clock.With hidden power consumptionwhen D and Q are identical. . .

38/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : CK clock constraints

...clock : true;...timing () {

related_pin : "CK";timing_type : min_pulse_width;fall_constraint(Pulse_width_3) {index_1 ("0.00117378,0.0449324,0.198535");values ("0.054590,0.069863,0.198733");}rise_constraint(Pulse_width_3) {index_1 ("0.00117378,0.0449324,0.198535");values ("0.080840,0.080924,0.198733");}

}...internal_power() {...}...

CK is clock...The minimum duration of the "1"state is tabulated.This duration is a function of thetransition time of the clock.With hidden power consumptionwhen D and Q are identical. . .

38/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : CK clock constraints

...clock : true;...timing () {

related_pin : "CK";timing_type : min_pulse_width;fall_constraint(Pulse_width_3) {index_1 ("0.00117378,0.0449324,0.198535");values ("0.054590,0.069863,0.198733");}rise_constraint(Pulse_width_3) {index_1 ("0.00117378,0.0449324,0.198535");values ("0.080840,0.080924,0.198733");}

}...internal_power() {...}...

CK is clock...The minimum duration of the "1"state is tabulated.This duration is a function of thetransition time of the clock.With hidden power consumptionwhen D and Q are identical. . .

38/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : CK clock constraints

...clock : true;...timing () {

related_pin : "CK";timing_type : min_pulse_width;fall_constraint(Pulse_width_3) {index_1 ("0.00117378,0.0449324,0.198535");values ("0.054590,0.069863,0.198733");}rise_constraint(Pulse_width_3) {index_1 ("0.00117378,0.0449324,0.198535");values ("0.080840,0.080924,0.198733");}

}...internal_power() {...}...

CK is clock...The minimum duration of the "1"state is tabulated.This duration is a function of thetransition time of the clock.With hidden power consumptionwhen D and Q are identical. . .

38/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Output signals (timing/power)

Warning : All events on outputs are related to the CKtransitionTransition times are functions of the CK transition time andof the ouput load capacitance.Propagation times are functions of the CK transition timeand of the ouput load capacitance.Power consumption tabulated for transition of Q due to atransition of CK.

39/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Output signals (timing/power)

Warning : All events on outputs are related to the CKtransitionTransition times are functions of the CK transition time andof the ouput load capacitance.Propagation times are functions of the CK transition timeand of the ouput load capacitance.Power consumption tabulated for transition of Q due to atransition of CK.

39/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Output signals (timing/power)

Warning : All events on outputs are related to the CKtransitionTransition times are functions of the CK transition time andof the ouput load capacitance.Propagation times are functions of the CK transition timeand of the ouput load capacitance.Power consumption tabulated for transition of Q due to atransition of CK.

39/69 ICS904-EN2-L4 Yves MATHIEU

Nangate 45nm Open Cell LibraryDFF_X2 : Output signals (timing/power)

Warning : All events on outputs are related to the CKtransitionTransition times are functions of the CK transition time andof the ouput load capacitance.Propagation times are functions of the CK transition timeand of the ouput load capacitance.Power consumption tabulated for transition of Q due to atransition of CK.

39/69 ICS904-EN2-L4 Yves MATHIEU

Outline

Bases of CMOS logic

Standard cell design

Standard cell libraries

Standard Cell characterization

Digital Integrated Circuit Testing

Place and route flow

40/69 ICS904-EN2-L4 Yves MATHIEU

The goal of test

Filtering out defective devices during manufacturing.The more you wait to detect defaults, the more it costs.Test done at wafer level and after packaging.Specification oriented test : check the conformance todesign specification.Application oriented test : check that the device worksproperly in its application environment.Structural test : check that there is no physical defect inthe chip.Structural test is the more efficient et more easy toimplement with generic methods.

41/69 ICS904-EN2-L4 Yves MATHIEU

The goal of test

Filtering out defective devices during manufacturing.The more you wait to detect defaults, the more it costs.Test done at wafer level and after packaging.Specification oriented test : check the conformance todesign specification.Application oriented test : check that the device worksproperly in its application environment.Structural test : check that there is no physical defect inthe chip.Structural test is the more efficient et more easy toimplement with generic methods.

41/69 ICS904-EN2-L4 Yves MATHIEU

The goal of test

Filtering out defective devices during manufacturing.The more you wait to detect defaults, the more it costs.Test done at wafer level and after packaging.Specification oriented test : check the conformance todesign specification.Application oriented test : check that the device worksproperly in its application environment.Structural test : check that there is no physical defect inthe chip.Structural test is the more efficient et more easy toimplement with generic methods.

41/69 ICS904-EN2-L4 Yves MATHIEU

The goal of test

Filtering out defective devices during manufacturing.The more you wait to detect defaults, the more it costs.Test done at wafer level and after packaging.Specification oriented test : check the conformance todesign specification.Application oriented test : check that the device worksproperly in its application environment.Structural test : check that there is no physical defect inthe chip.Structural test is the more efficient et more easy toimplement with generic methods.

41/69 ICS904-EN2-L4 Yves MATHIEU

The goal of test

Filtering out defective devices during manufacturing.The more you wait to detect defaults, the more it costs.Test done at wafer level and after packaging.Specification oriented test : check the conformance todesign specification.Application oriented test : check that the device worksproperly in its application environment.Structural test : check that there is no physical defect inthe chip.Structural test is the more efficient et more easy toimplement with generic methods.

41/69 ICS904-EN2-L4 Yves MATHIEU

The goal of test

Filtering out defective devices during manufacturing.The more you wait to detect defaults, the more it costs.Test done at wafer level and after packaging.Specification oriented test : check the conformance todesign specification.Application oriented test : check that the device worksproperly in its application environment.Structural test : check that there is no physical defect inthe chip.Structural test is the more efficient et more easy toimplement with generic methods.

41/69 ICS904-EN2-L4 Yves MATHIEU

The goal of test

Filtering out defective devices during manufacturing.The more you wait to detect defaults, the more it costs.Test done at wafer level and after packaging.Specification oriented test : check the conformance todesign specification.Application oriented test : check that the device worksproperly in its application environment.Structural test : check that there is no physical defect inthe chip.Structural test is the more efficient et more easy toimplement with generic methods.

41/69 ICS904-EN2-L4 Yves MATHIEU

Structural testWhat kind of defects?

Hard shorts, Hard open.Resistive bridges, Resitive shorts.Wiring defects, Component (transistors) defects.A fault is an undesired behaviour of a chip as a result of adefectfault models should :

• Accurately reflect the effect of a defect.• Represent defects that are typical for the technology used.• Be easy to implement in tools.

42/69 ICS904-EN2-L4 Yves MATHIEU

Structural testWhat kind of defects?

Hard shorts, Hard open.Resistive bridges, Resitive shorts.Wiring defects, Component (transistors) defects.A fault is an undesired behaviour of a chip as a result of adefectfault models should :

• Accurately reflect the effect of a defect.• Represent defects that are typical for the technology used.• Be easy to implement in tools.

42/69 ICS904-EN2-L4 Yves MATHIEU

Structural testWhat kind of defects?

Hard shorts, Hard open.Resistive bridges, Resitive shorts.Wiring defects, Component (transistors) defects.A fault is an undesired behaviour of a chip as a result of adefectfault models should :

• Accurately reflect the effect of a defect.• Represent defects that are typical for the technology used.• Be easy to implement in tools.

42/69 ICS904-EN2-L4 Yves MATHIEU

Structural testWhat kind of defects?

Hard shorts, Hard open.Resistive bridges, Resitive shorts.Wiring defects, Component (transistors) defects.A fault is an undesired behaviour of a chip as a result of adefectfault models should :

• Accurately reflect the effect of a defect.• Represent defects that are typical for the technology used.• Be easy to implement in tools.

42/69 ICS904-EN2-L4 Yves MATHIEU

Structural testWhat kind of defects?

Hard shorts, Hard open.Resistive bridges, Resitive shorts.Wiring defects, Component (transistors) defects.A fault is an undesired behaviour of a chip as a result of adefectfault models should :

• Accurately reflect the effect of a defect.• Represent defects that are typical for the technology used.• Be easy to implement in tools.

42/69 ICS904-EN2-L4 Yves MATHIEU

Structural testWhat kind of defects?

Hard shorts, Hard open.Resistive bridges, Resitive shorts.Wiring defects, Component (transistors) defects.A fault is an undesired behaviour of a chip as a result of adefectfault models should :

• Accurately reflect the effect of a defect.• Represent defects that are typical for the technology used.• Be easy to implement in tools.

42/69 ICS904-EN2-L4 Yves MATHIEU

Structural testWhat kind of defects?

Hard shorts, Hard open.Resistive bridges, Resitive shorts.Wiring defects, Component (transistors) defects.A fault is an undesired behaviour of a chip as a result of adefectfault models should :

• Accurately reflect the effect of a defect.• Represent defects that are typical for the technology used.• Be easy to implement in tools.

42/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testThe "stuck-at" fault model

We assume that the only effect of a defect is a node that isstuck at low or high logic level.We assume that there is only one "stuck-at" fault in thecircuit.All the remaining circuit may be used to test if this faultexists.How to detect a stuck-at "0" at node between G1 and G3?

Controllability

Try to put "1" onfaulty node.

Put "1" at G1output

Put "1,1" at G1inputs

Observability

G3 used totransmit value.

Put "0" on otherG3 input.

Put "1,1" on G2inputs.

43/69 ICS904-EN2-L4 Yves MATHIEU

Structural testStuck-at fault model

Usable for any combinational block based on simplecombinational gates.Inputs are called primary inputsOutputs are called primary outputsFor any combinational netlist algorithmic tools cancompute a test program :

• The test program is a set of test vectors.• A test vector is the union of a stimuli on primary inputs,

and expected values on primary outputs.

A 100% stuck-at fault coverage can be achieved.

44/69 ICS904-EN2-L4 Yves MATHIEU

Structural testStuck-at fault model

Usable for any combinational block based on simplecombinational gates.Inputs are called primary inputsOutputs are called primary outputsFor any combinational netlist algorithmic tools cancompute a test program :

• The test program is a set of test vectors.• A test vector is the union of a stimuli on primary inputs,

and expected values on primary outputs.

A 100% stuck-at fault coverage can be achieved.

44/69 ICS904-EN2-L4 Yves MATHIEU

Structural testStuck-at fault model

Usable for any combinational block based on simplecombinational gates.Inputs are called primary inputsOutputs are called primary outputsFor any combinational netlist algorithmic tools cancompute a test program :

• The test program is a set of test vectors.• A test vector is the union of a stimuli on primary inputs,

and expected values on primary outputs.

A 100% stuck-at fault coverage can be achieved.

44/69 ICS904-EN2-L4 Yves MATHIEU

Structural testStuck-at fault model

Usable for any combinational block based on simplecombinational gates.Inputs are called primary inputsOutputs are called primary outputsFor any combinational netlist algorithmic tools cancompute a test program :

• The test program is a set of test vectors.• A test vector is the union of a stimuli on primary inputs,

and expected values on primary outputs.

A 100% stuck-at fault coverage can be achieved.

44/69 ICS904-EN2-L4 Yves MATHIEU

Structural testStuck-at fault model

Usable for any combinational block based on simplecombinational gates.Inputs are called primary inputsOutputs are called primary outputsFor any combinational netlist algorithmic tools cancompute a test program :

• The test program is a set of test vectors.• A test vector is the union of a stimuli on primary inputs,

and expected values on primary outputs.

A 100% stuck-at fault coverage can be achieved.

44/69 ICS904-EN2-L4 Yves MATHIEU

Structural testStuck-at fault model

Usable for any combinational block based on simplecombinational gates.Inputs are called primary inputsOutputs are called primary outputsFor any combinational netlist algorithmic tools cancompute a test program :

• The test program is a set of test vectors.• A test vector is the union of a stimuli on primary inputs,

and expected values on primary outputs.

A 100% stuck-at fault coverage can be achieved.

44/69 ICS904-EN2-L4 Yves MATHIEU

Structural testStuck-at fault model

Usable for any combinational block based on simplecombinational gates.Inputs are called primary inputsOutputs are called primary outputsFor any combinational netlist algorithmic tools cancompute a test program :

• The test program is a set of test vectors.• A test vector is the union of a stimuli on primary inputs,

and expected values on primary outputs.

A 100% stuck-at fault coverage can be achieved.

44/69 ICS904-EN2-L4 Yves MATHIEU

Structural testHow to get full observability and full controllability in a synchro-nous circuit?

A digital circuit is build of combinational bloc synchronizedby D flip-flops.Only a few primary inputs are usable.Only a few primary outputs are usable.Some combinational blocs are completely isolated fromPIs or POs

45/69 ICS904-EN2-L4 Yves MATHIEU

Structural testHow to get full observability and full controllability in a synchro-nous circuit?

A digital circuit is build of combinational bloc synchronizedby D flip-flops.Only a few primary inputs are usable.Only a few primary outputs are usable.Some combinational blocs are completely isolated fromPIs or POs

45/69 ICS904-EN2-L4 Yves MATHIEU

Structural testHow to get full observability and full controllability in a synchro-nous circuit?

A digital circuit is build of combinational bloc synchronizedby D flip-flops.Only a few primary inputs are usable.Only a few primary outputs are usable.Some combinational blocs are completely isolated fromPIs or POs

45/69 ICS904-EN2-L4 Yves MATHIEU

Structural testHow to get full observability and full controllability in a synchro-nous circuit?

A digital circuit is build of combinational bloc synchronizedby D flip-flops.Only a few primary inputs are usable.Only a few primary outputs are usable.Some combinational blocs are completely isolated fromPIs or POs

45/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Flip-Flop and Scan-chain

Each DFF is replaced by a Scan-DFF.

In test mode (TE=1) D input of the flip_flopis replaced by TD input

Scan DFF are chained in a long shift register.

A new SI serial input is used for controllability.

A new SO serial output is used for observability.

A test enable mode is inserted.

46/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Flip-Flop and Scan-chain

Each DFF is replaced by a Scan-DFF.

In test mode (TE=1) D input of the flip_flopis replaced by TD input

Scan DFF are chained in a long shift register.

A new SI serial input is used for controllability.

A new SO serial output is used for observability.

A test enable mode is inserted.

46/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Flip-Flop and Scan-chain

Each DFF is replaced by a Scan-DFF.

In test mode (TE=1) D input of the flip_flopis replaced by TD input

Scan DFF are chained in a long shift register.

A new SI serial input is used for controllability.

A new SO serial output is used for observability.

A test enable mode is inserted.

46/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Flip-Flop and Scan-chain

Each DFF is replaced by a Scan-DFF.

In test mode (TE=1) D input of the flip_flopis replaced by TD input

Scan DFF are chained in a long shift register.

A new SI serial input is used for controllability.

A new SO serial output is used for observability.

A test enable mode is inserted.

46/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Flip-Flop and Scan-chain

Each DFF is replaced by a Scan-DFF.

In test mode (TE=1) D input of the flip_flopis replaced by TD input

Scan DFF are chained in a long shift register.

A new SI serial input is used for controllability.

A new SO serial output is used for observability.

A test enable mode is inserted.

46/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Flip-Flop and Scan-chain

Each DFF is replaced by a Scan-DFF.

In test mode (TE=1) D input of the flip_flopis replaced by TD input

Scan DFF are chained in a long shift register.

A new SI serial input is used for controllability.

A new SO serial output is used for observability.

A test enable mode is inserted.

46/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Test and design automation

A test program consists on loops of the followingprocedure :

• TE=1 A test vector is loaded via input SI using theshift-register.

• TE=0 A one cycle computation is done in normal mode. Allregisters are loaded by computed values.

• TE=1 The shift-register is dumped via SO, results arecompared to expected results.

Scan chain insertion can be fully automatic (duringsynthesis)Test vector generation can be fully automatic (aftersynthesis)Warning Using scan test reduces performances (lowerclock frequency, higher power consumption)

47/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Test and design automation

A test program consists on loops of the followingprocedure :

• TE=1 A test vector is loaded via input SI using theshift-register.

• TE=0 A one cycle computation is done in normal mode. Allregisters are loaded by computed values.

• TE=1 The shift-register is dumped via SO, results arecompared to expected results.

Scan chain insertion can be fully automatic (duringsynthesis)Test vector generation can be fully automatic (aftersynthesis)Warning Using scan test reduces performances (lowerclock frequency, higher power consumption)

47/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Test and design automation

A test program consists on loops of the followingprocedure :

• TE=1 A test vector is loaded via input SI using theshift-register.

• TE=0 A one cycle computation is done in normal mode. Allregisters are loaded by computed values.

• TE=1 The shift-register is dumped via SO, results arecompared to expected results.

Scan chain insertion can be fully automatic (duringsynthesis)Test vector generation can be fully automatic (aftersynthesis)Warning Using scan test reduces performances (lowerclock frequency, higher power consumption)

47/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Test and design automation

A test program consists on loops of the followingprocedure :

• TE=1 A test vector is loaded via input SI using theshift-register.

• TE=0 A one cycle computation is done in normal mode. Allregisters are loaded by computed values.

• TE=1 The shift-register is dumped via SO, results arecompared to expected results.

Scan chain insertion can be fully automatic (duringsynthesis)Test vector generation can be fully automatic (aftersynthesis)Warning Using scan test reduces performances (lowerclock frequency, higher power consumption)

47/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Test and design automation

A test program consists on loops of the followingprocedure :

• TE=1 A test vector is loaded via input SI using theshift-register.

• TE=0 A one cycle computation is done in normal mode. Allregisters are loaded by computed values.

• TE=1 The shift-register is dumped via SO, results arecompared to expected results.

Scan chain insertion can be fully automatic (duringsynthesis)Test vector generation can be fully automatic (aftersynthesis)Warning Using scan test reduces performances (lowerclock frequency, higher power consumption)

47/69 ICS904-EN2-L4 Yves MATHIEU

Structural testScan Test and design automation

A test program consists on loops of the followingprocedure :

• TE=1 A test vector is loaded via input SI using theshift-register.

• TE=0 A one cycle computation is done in normal mode. Allregisters are loaded by computed values.

• TE=1 The shift-register is dumped via SO, results arecompared to expected results.

Scan chain insertion can be fully automatic (duringsynthesis)Test vector generation can be fully automatic (aftersynthesis)Warning Using scan test reduces performances (lowerclock frequency, higher power consumption)

47/69 ICS904-EN2-L4 Yves MATHIEU

Outline

Bases of CMOS logic

Standard cell design

Standard cell libraries

Standard Cell characterization

Digital Integrated Circuit Testing

Place and route flow

48/69 ICS904-EN2-L4 Yves MATHIEU

SoC Encounter tool gui.

49/69 ICS904-EN2-L4 Yves MATHIEU

Viewing nets as elastic wires.

50/69 ICS904-EN2-L4 Yves MATHIEU

Pads around de core, Corner pads.

51/69 ICS904-EN2-L4 Yves MATHIEU

The design hierarchy is preserved in the netlist

52/69 ICS904-EN2-L4 Yves MATHIEU

Floorplan : Placement of macro-cells w/o power rings

53/69 ICS904-EN2-L4 Yves MATHIEU

Floorplan : Defining prohibited areas for standard cells

54/69 ICS904-EN2-L4 Yves MATHIEU

Floorplan : Defining a global power ring

55/69 ICS904-EN2-L4 Yves MATHIEU

Floorplan : Routing reinforcement power stripes

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Floorplan : Connecting Standard Cell Raws and Power pads

57/69 ICS904-EN2-L4 Yves MATHIEU

Connection between lines uses arrays of standard size vias.

58/69 ICS904-EN2-L4 Yves MATHIEU

PLACEMENT : Automatic placement of standard cells.

59/69 ICS904-EN2-L4 Yves MATHIEU

PLACEMENT : Hierarchy analysis, placement guides.

60/69 ICS904-EN2-L4 Yves MATHIEU

PLACEMENT : Details.

61/69 ICS904-EN2-L4 Yves MATHIEU

Initial SCAN chain for test

62/69 ICS904-EN2-L4 Yves MATHIEU

Optimized restructured scan chain

63/69 ICS904-EN2-L4 Yves MATHIEU

Trial routing : not enough metal levels

64/69 ICS904-EN2-L4 Yves MATHIEU

Trial routing : better results with 6 levels

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Trial routing : the full circuit

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Clock tree synthesis : the tree of buffers

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Clock tree synthesis : Skew evaluation on CLK DFF inputs

68/69 ICS904-EN2-L4 Yves MATHIEU

In place optimization and final routing with clock tree

69/69 ICS904-EN2-L4 Yves MATHIEU