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Robust Window-based Robust Window-based Multi-node Technology-Multi-node Technology-
Independent Logic Independent Logic MinimizationMinimization
Jeff L.Cobb
Kanupriya Gulati Sunil P. Khatri
Texas Instruments, Inc. Dept. of ECE, Texas A&M University
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Overview
IntroductionBackgroundPrevious workApproachExperimental resultsConclusions
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Introduction
VLSI design flow◦HDL (Verilog, VHDL)◦Logic optimization◦Physical design
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Introduction
Purpose of logic optimization◦Reduce area◦Reduce power◦Reduce delay
Logic optimization◦Technology-independent optimization
◦Goal: reduce literal count◦Technology-dependent optimization
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BackgroundDon’t Cares
◦Logic function allowed to have 0 or 1 as possible output for a given input
ODC SDC
◦XDC: External don’t cares given5
BackgroundDon’t Cares
◦Computed for one node at a time◦Cannot capture multi-node flexibility
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xy (x+y) = xy(xy) + (x+y)(x+y) = xy+xy = x y
Goal: multi-node logic minimization◦Yields a Boolean relation◦Need to determinize this relation for solution
BackgroundBoolean relations
◦Can express more than one allowed output vector for a single input vector
◦Don’t cares only express flexibility for a single output
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Terminology
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Problem Definition
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• Implement dual-node Boolean relation-based multi-level logic minimization technique
•Goals: • Method must scale to large designs• Compare to best don’t care-based method
(single-node)
Previous Work
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• [CM77] Formulated multi-node minimization problem• No results provided
• [WW94] Multi-node minimization• Extremely large runtimes, works on very
small designs• [MB05] Single node approach, uses windowing and SAT based formulation• Used for comparison purposes
• This work: Efficient choice of nodes, window based, efficient quantification scheduling
Approach
Key featuresDual node optimizationCareful node pair selectionWindow based optimization techniqueEarly quantification for efficiency
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Approach
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Node Pair Selection
Node Pair Selection
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Node Pair Selection
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Node Pair Selection
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Node Pair Selection• Compute common input ratio
• Compute common output ratio
• Select node pairs that satisfy
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Subnetwork Extraction
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Subnetwork Extraction
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Building the Relation
where
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),...,,...,(),...,,...,(),...,,...,( 111 nixnixnix xxxfxxxfxxxfiii
Quantification Scheduling
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Quantification Scheduling
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Quantification Scheduling
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Call BREL (a Boolean relation minimizer) to minimize
Returns new nodes and
Graft new nodes into
Delete original nodes
,
Endgame
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BREL
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• BREL is a heuristic Boolean relation solver
• Solving a Boolean relation • Same as minimum cost determinization of
the relation (i.e. finding the lowest cost function which is contained in the relation)
• Branch and bound approach
Experimental ResultsImplemented in SISUses CUDD ROBDD Package15 benchmark circuits from mcnc91, itc99Metric for quality: literal countPreprocessing steps:
Removes constant-valued nodesRemoves nodes that do not fanout
Merges functionally identical nodes
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Experimental Results
Parameter selection
4 parameters to node selection algorithm
Goal: Find “golden” values
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Experimental ResultsParameter:
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Experimental ResultsParameters:
: Window size
: Partners for
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Experimental Results
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Experimental ResultsParameter:
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Experimental Results
“Golden” parameter values:
Can be modified to balance quality/runtime
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Experimental Results Compared versus
12% lit. improvement
38x runtime increase But runtimes are still within 3-4 min
Low memory (#BDD nodes)
High gain (number of node pairs which givean improvement)
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Experimental Results Run after
13% lit. improvement
Both use 2x2 windows
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Experimental ResultsLimit subnetwork size τ
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Conclusions12% less literals than best DC approachRuntimes under 4 minutes for largest networkLow memory usageFurther reduce literals by 13% after running best
DC approach
Future WorkConsider 3+ nodes in relationSAT-based relation constructionAlternative to BREL
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Thank you!
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SAT-Sweep
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BREL
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BREL
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