Reaching Agreement in the Presence of Faults

Reaching Agreement in the Presence of Faults

M. Pease, R. Shostak, and L. LamportSRI International, Menlo Park, California

Presented by: Prabhjot Mall

Abstract

The problem concerns a set of isolated processors, some unknown subset of which may be faulty. Each non-faulty processor has a private value that must be communicated to every other non-faulty processor.

The Problem

The value inferred for a non-faulty processor must be the processor’s private value and the value inferred for a faulty processor must be consistent with the corresponding value inferred by each other non-faulty processor.

Claim

The given problem is only solvable for n ≥ 3m +1, where m is the number of faulty processors and n is the total number of processors.

Interactive Consistency

Compute a vector of values for every processor, such that: The non-faulty processors compute

the exact same vector The element of this vector corresponding

to a given non-faulty processor is the private value of that processor.

Interactive ConsistencyThe algorithm guarantees Interactive Consistency since it allows the non-faulty processors to come to a consistent view of all processors.

The computed vector is called the Interactive Consistency Vector.

The Single-Fault Case m=1, n=4The procedure consists of an exchange of messages, followed by the computation of the interactive consistency vector on the basis of the results of the exchange.

Two Rounds of exchange are required. In the first round the processors exchange their private values and in the second round they exchange the results obtained in the first round.

The Single-Fault Case

V1

V3

V2

V4

[V1][V2][V3][V5]

FaultyNon Faulty

The Single-Fault Case

V1

V3

V2

V4

FaultyNon Faulty

[V1][V2][V3][V6]

The Single-Fault Case

V1

V3

V2

V4

FaultyNon Faulty

[V1][V2][V3][V4]

The Single-Fault Case

V1

V3

V2

V4

[V1][V2][V3][V6]

FaultyNon Faulty

[V1][V2][V3][V5]

[V1][V2][V3][V4]

[V1][V2][V3][V4]

The Single-Fault Case

V1

V3

V2

V4

[V1][V2][V3][V6]

FaultyNon Faulty

[V1][V2][V3][NIL]

[V1][V2][V3][V4]

[V1][V2][V3][V4]

The Single-Fault Case

V1

V3

V2

V4

FaultyNon Faulty

[V1][V2][V3][NIL]

[V1][V2][V3][V6]

[V1][V2][V3][V4]

[V1][V2][V3][V5]

The Single-Fault Case

V1

V3

V2

V4

FaultyNon Faulty

[V1][V2][V3][NIL]

[V1][V2][V3][V5]

[V1][V2][V3][V6]

[V1][V2][V3][V4]

The Single-Fault Case

V1

V3

V2

V4

[V1][V2][V3][NIL]

FaultyNon Faulty

[V1][V2][V3][NIL]

[V1][V2][V3][NIL]

[V1][V2][V3][NIL]

Procedure for n≥3m+1

For 1 faulty processor 2 rounds of communicationFor m faulty processors m+1 rounds of communicationP: Set of processorsV: Set of values

k≥1: k-level scenario mapping from a set of non-empty strings {p1,p2,p3,…pn} over P of length k+1, to V

Example: For a k-level scenario σ and string w=p1p2…pn σ(w) = the value of pn that pn tells p(n-1) … which p2 tells p1

Procedure for n≥3m+1

For an arbitrary processor p, a non faulty processor q and a string w

σ(pqw) = σ(qw)

The message a processor p receives in a scenario σ are given by the restriction σp of σ to strings beginning with p.

Procedure for n≥3m+1For some subset Q of Psize(Q) ≥ (n+m)/2

If σp (pwq) = v for each string w over Qp records the value of q as v.

Otherwise, the algorithm for m-1, n-1 is recursively applied with P replaced by P-{q} and σp(pwq) by σp(pw). If at least (n+m)/2 of the n-1 elements in the vector obtained by the recursive call agree p records the value of q as v, otherwise it records NIL.

Two Faulty Processors

V1

V3

V2

V4

FaultyNon Faulty

V5

V6

w σ(w)

p1 V1p2 V2p3 V3p4 V9p5 V5p6 V8p7 V7

V7

[v1][v2][v3][v9][v5][v8][v7]

Two Faulty Processors

V1

V3

V2

V4

FaultyNon Faulty

V5

V6

[v1][v2][v3][v8][v5][v0][v7]

[v1][v2][v3][v4][v5][v6][v7]

[v1][v2][v3][v8][v5][v0][v7]

[v1][v2][v3][v8][v5][v0][v7]

[v1][v2][v3][v4][v5][NIL][v7]

w σ(w)

p1p2p1 V1

p1p2p3 V3

p1p2p4 V8

p1p2p5 V5

p1p2p6 V0

p1p2p7 V7

p1p3p1 V1

p1p3p2 V2

… …

p1p7p7 V7V7

[v1][v2][v3][NIL][v5][NIL][v7]

Questions?

Aren’t you glad this is over???