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HCS12DBFAMILYPP/DRev. 0.7, 8/2003
HCS12DB Family Product Proposal
Product Proposal
F
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Freescale Semiconductor, Inc.n
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Introduction
Designed for automotive multiplexing applications, members of the MC9S12DB-Family of 16 bit Flash-based microcontrollers are fully pin compatible and enable users to choose between different memory and peripheral options for scalable designs. All MC9S12DB-Family members are composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM, 8K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), up to two serial peripheral interfaces (SPI), an enhanced capture timer (ECT), two 8-channel, 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM), Byteflight interface and up to two CAN 2.0 A, B software compatible modules (MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the system integration module (SIM). The MC9S12DB-Family has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22 I/O ports are available with Wake-Up capability from STOP or WAIT mode.
Table 1. MC9S12DB Family Members
Flash RAM EEPROM Package Device CAN ByteFlight SCI SPI A/D PWM I/O
128K 8K 2K112 LQFP
MC9S12DB1282 1 2 2 2/16 8 ch 91
80 QFP 0 1 1 2 1/8 7 ch 59
64K 8K 2K 80 QFP MC9S12DB64 0 1 1 1 1/8 7 ch 59
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Motorola, Inc., 2003
For More Information On This Product, Go to: www.freescale.com
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Features
NOTE: Not all features listed here are available in all configurations.
• 16-bit CPU12– Upward compatible with M68HC11 instruction set– Interrupt stacking and programmer’s model identical to M68HC11– 20-bit ALU– Instruction queue– Enhanced indexed addressing
• Multiplexed bus– Single chip or expanded– 16 address/16 data wide or 16 address/8 data narrow modes– External address space 1 MB for data and program space (112 pin
package only)• Wake-up interrupt inputs depending on the package option
– 8-bit port H– 4-bit port J– 8-bit port shared with PWM/SPI
• Memory options– 64K, 128K Byte Flash EEPROM– 2K Byte EEPROM– 8K Byte RAM
• One or Two analog-to-digital converters (ATD)– 1 or 2 times 8-channels, 10-bit resolution depending on the package
option– External conversion trigger capability
• Up to two 1 M bit per second, CAN 2.0 A, B software compatible modules– Five receive and three transmit buffers– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or
8 x 8 bit– Four separate interrupt channels for Rx, Tx, error and wake-up– Low-pass filter wake-up function– Loop-back for self test operation
• Enhanced Capture Timer (ECT)– 16-bit main counter with 7-bit prescaler– 8 programmable input capture or output compare channels; 4 of the
8 input captures with buffer– Input capture filters and buffers, three successive captures on four
channels, or two captures on four channels with a capture/compare selectable on the remaining four
– Four 8-bit or two 16-bit pulse accumulators– 16-bit modulus down-counter with 4-bit prescaler– Four user-selectable delay counters for signal filtering
2 HCS12DB Family Product Proposal MOTOROLA
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HCS12DBFAMILYPP/DFeatures
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• Seven or eight PWM channels with programmable period and duty cycle– 8-bit 4-channel or 16-bit 2-channel (80-Pin Version)– 8-bit 8-channel or 16-bit 4-channel (112-Pin Version)– Separate control for each pulse width and duty cycle– Center- or left-aligned outputs– Programmable clock select logic with a wide range of frequencies
• Serial interfaces– Two asynchronous serial communications interfaces (SCI)– Up to two synchronous serial peripheral interfaces (SPI)
• Byteflight– 10 MBit/s serial protocol
• SIM (system integration module)– CRG (windowed COP watchdog, real-time interrupt, clock monitor,
clock generation and reset)– MEBI (multiplexed external bus interface)– MMC (memory map and interface)– INT (interrupt control)– BKP (breakpoints)– BDM (background debug mode)
• Clock generation– Phase-locked loop clock frequency multiplier– Limp home mode in absence of external clock– Slow mode divider– Low power 0.5 to 40 MHz crystal oscillator reference clock
• Operating frequency– 50 MHz equivalent to 25 MHz bus speed for single chip – 40 MHz equivalent to 20 MHz bus speed in expanded bus modes
• Internal 5 V to 2.5 V regulator
• 112-Pin LQFP or 80-Pin QFP package– I/O lines with 5-V input and drive capability– 5-V ATD inputs– Dual supply (5 V for I/O and ATD, 2.5 V for logic
• Development support– Single-wire background debug™ mode (BDM)– On-chip hardware breakpoints
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Figure 1. MC9S12DB Family Block Diagram
64K or 128K Byte Flash EEPROM
8K Byte RAM
Enhanced Capture
RESET
EXTALXTAL
VDD1,2VSS1,2
SCI0
2K Byte EEPROM
BKGD
R/W
MODB
XIRQ
NOACC/XCLKS
SystemIntegration
Module(SIM)
VDDR
CPU12
Periodic InterruptCOP WatchdogClock Monitor
Single-wire Background
Breakpoints
PLLVSSPLL
XFCVDDPLL
Multiplexed Address/Data Bus
VDDAVSSA
VRHVRLATD0
MultiplexedWide Bus
Multiplexed
VDDX VSSX
Internal Logic 2.5V
Narrow Bus
PPAGE
VDDPLL VSSPLL
PLL 2.5V
IRQ
LSTRBECLKMODA
PA4
PA3
PA2
PA1
PA0
PA7
PA6
PA5
TEST
AD
DR
12A
DD
R11
AD
DR
10A
DD
R9
AD
DR
8
AD
DR
15A
DD
R14
AD
DR
13D
ATA
12D
ATA
11D
ATA
10D
ATA
9D
ATA
8
DAT
A15
DAT
A14
DAT
A13
PB
4P
B3
PB
2P
B1
PB
0
PB
7P
B6
PB
5A
DD
R4
AD
DR
3A
DD
R2
AD
DR
1A
DD
R0
AD
DR
7A
DD
R6
AD
DR
5D
ATA
4D
ATA
3D
ATA
2D
ATA
1D
ATA
0
DAT
A7
DAT
A6
DAT
A5
DAT
A4
DAT
A3
DAT
A2
DAT
A1
DAT
A0
DAT
A7
DAT
A6
DAT
A5
PE3PE4PE5PE6PE7
PE0PE1PE2
AN2
AN6
AN0
AN7
AN1
AN3AN4AN5
PAD03PAD04PAD05PAD06PAD07
PAD00PAD01PAD02
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3IOC4IOC5
PT3PT4PT5PT6PT7
PT0PT1PT2
VRHVRL
VDDAVSSA
VRHVRLATD1
AN2
AN6
AN0
AN7
AN1
AN3AN4AN5
PAD11PAD12PAD13PAD14PAD15
PAD08PAD09PAD10
VDDAVSSA
RXDTXD
MISOMOSI
PS3PS4PS5
PS0PS1PS2SCI1
RXDTXD
PWM2
PWM6
PWM0
PWM7
PWM1
PWM3PWM4PWM5
PP3PP4PP5PP6PP7
PP0PP1PP2
PIX2
PIX0PIX1
PIX3
ECS
PK3
PK7
PK0PK1
XADDR17
ECS
XADDR14XADDR15XADDR16
SCKSS
PS6PS7
SPI0
PJ6PJ7
CAN0RxCANTxCAN PM1
PM0
PM2PM3PM4PM5PM6PM7
KWH2
KWH6
KWH0
KWH7
KWH1
KWH3KWH4KWH5
PH3PH4PH5PH6PH7
PH0PH1PH2
KWJ0KWJ1
PJ0PJ1
I/O Driver 5V
VDDA
VSSA
A/D Converter 5V &
DDRA DDRB
PTA PTB
DD
RE
PT
E
AD
1
AD
0
PT
K
DD
RK
PT
T
DD
RT
PT
P
DD
RP
PT
S
DD
RS
PT
M
DD
RM
PT
H
DD
RH
PT
J
DD
RJ
PK2
Clock andResetGenerationModule
Voltage RegulatorVSSR
Debug Module
VDD1,2VSS1,2
VREGEN
VDDRVSSR
Voltage Regulator 5V & I/O
Not all functionality shown in thisblock diagram is available in all versions.
CAN4RxCANTxCAN
MISOMOSISCK
SSSPI1
PIX4PIX5
PK4PK5
XADDR18XADDR19
Voltage Regulator Reference
KWP2
KWP6
KWP0
KWP7
KWP1
KWP3KWP4KWP5
KWJ6KWJ7
Timer
Sign
als
show
n in
Bol
d ar
e no
t ava
ilabl
e on
the
80 Q
FP P
acka
ge
RX_BFTX_BF
BYTEFLIGHTBF_PSYNBF_PROKBF_PERRBF_PSLM
PWM
4 HCS12DB Family Product Proposal MOTOROLA
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Pin Out Explanations:
• A/D is the number of modules/total number of A/D channels.
• I/O count:– 112 Pin Package:
– Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8,
– PAD = 16 input only.– 22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ,
XIRQ)– 80 Pin Package:
– Port A = 8, B = 8, E = 6 + 2 input only, M = 6, P = 7, S = 6, T = 8, PAD = 8 input only
– 9 inputs provide Interrupt capability (P= 7, IRQ, XIRQ)
• MC9S12DB64 features only one SPI, SPI0
• SPI1 pins are shared with PWM3:0 or Port H3:0 routeable under software control
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Figure 2. Pin Assignments 112 LQFP for MC9S12DB128
VRHVDDAPAD15/AN15/ETRIG1PAD07/AN07/ETRIG0PAD14/AN14PAD06/AN06PAD13/AN13PAD05/AN05PAD12/AN12PAD04/AN04PAD11/AN11PAD03/AN03PAD10/AN10PAD02/AN02PAD09/AN09PAD01/AN01PAD08/AN08PAD00/AN00VSS2VDD2PA7/ADDR15/DATA15PA6/ADDR14/DATA14PA5/ADDR13/DATA13PA4/ADDR12/DATA12PA3/ADDR11/DATA11PA2/ADDR10/DATA10PA1/ADDR9/DATA9PA0/ADDR8/DATA8
PP4/
KWP4
/PW
M4
PP5/
KPW
5/PW
M5
PP6/
KWP6
/PW
M6
PP7/
KWP7
/PW
M7
PK7/
ECS/
ROM
CTL
VDD
XVS
SXPM
0/RX
CAN0
/RXB
PM1/
TXCA
N0/T
XBPM
2/R
X_BF
/RXC
AN0/
MIS
O0
PM3/
TX_B
F/TX
CAN
0/SS
0PM
4/BF
_PSY
N/R
XCAN
0/R
XCAN
4/M
OSI
0PM
5/BF
_PR
OK/
TXC
AN0/
TXC
AN4/
SCK0
PJ6/
KWJ6
/RXC
AN4/
SDA
PJ7/
KWJ7
/TXC
AN4/
SCL
VREG
ENPS
7/SS
0PS
6/SC
K0PS
5/M
OSI
0PS
4/M
ISO
0PS
3/TX
D1PS
2/RX
D1PS
1/TX
D0
PS0/
RXD
0PM
6/BF
_PER
R/R
XCAN
4PM
7/BF
_PSL
M/T
XCAN
4VS
SAVR
L
SS1/PWM3/KWP3/PP3SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1MISO1/PWM0/KWP0/PP0
XADDR17/PK3XADDR16/PK2XADDR15/PK1XADDR14/PK0
IOC0/PT0IOC1/PT1IOC2/PT2IOC3/PT3
VDD1VSS1
IOC4/PT4IOC5/PT5IOC6/PT6IOC7/PT7
XADDR19/PK5XADDR18/PK4
KWJ1/PJ1KWJ0/PJ0
MODC/TAGHI/BKGDADDR0/DATA0/PB0ADDR1/DATA1/PB1ADDR2/DATA2/PB2ADDR3/DATA3/PB3ADDR4/DATA4/PB4
ADD
R5/
DATA
5/PB
5AD
DR
6/DA
TA6/
PB6
ADD
R7/
DATA
7/PB
7KW
H7/P
H7KW
H6/P
H6KW
H5/P
H5KW
H4/P
H4XC
LKS/
NO
ACC
/PE7
MO
DB/
IPIP
E1/P
E6M
ODA
/IPIP
E0/P
E5EC
LK/P
E4VS
SRVD
DR
RES
ETVD
DPL
LXF
CVS
SPLL
EXTA
LXT
ALTE
STSS
1/KW
H3/P
H3SC
K1/K
WH2
/PH2
MO
SI1/
KWH1
/PH1
MIS
O1/
KWH0
/PH0
LSTR
B/TA
GLO
/PE3
R/W
/PE2
IRQ
/PE1
XIR
Q/P
E0
Signals shown in Bold are not available on the 80 Pin Package
MC9S12DB128112LQFP
112
111
110
109
108
107
106
105
104
103
102
101
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
12345678910111213141516171819202122232425262728
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
84838281807978777675747372717069686766656463626160595857
6 HCS12DB Family Product Proposal MOTOROLA
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Figure 3. Pin Assignments MC9S12DB128 in 80 QFP
1234567891011121314151617181920
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
MC9S12DB12880 QFP
VRHVDDAPAD07/AN07/ETRIG0PAD06/AN06PAD05/AN05PAD04/AN04PAD03/AN03PAD02/AN02PAD01/AN01PAD00/AN00VSS2VDD2PA7/ADDR15/DATA15PA6/ADDR14/DATA14PA5/ADDR13/DATA13PA4/ADDR12/DATA12PA3/ADDR11/DATA11PA2/ADDR10/DATA10PA1/ADDR9/DATA9PA0/ADDR8/DATA8
PP4/
KWP4
/PW
M4
PP5/
KWP5
/PW
M5
PP7/
KWP7
/PW
M7
VDD
XVS
SXPM
2/R
X_BF
PM3/
TX_B
FPM
4/BF
_PSY
NPM
5/BF
_PR
OK
VREG
ENPS
7/SS
0PS
6/SC
K0PS
5/M
OSI
0PS
4/M
ISO
0PS
1/TX
D0
PS0/
RXD
0PM
6/BF
_PER
RBF
_PSL
MVS
SAVR
L
SS1/PWM3/KWP3/PP3SCK1/PWM2/KWP2/PP2
MOSI1/PWM1/KWP1/PP1MISO1/PWM0/KWP0/PP0
IOC0/PT0IOC1/PT1IOC2/PT2IOC3/PT3
VDD1VSS1
IOC4/PT4IOC5/PT5IOC6/PT6IOC7/PT7
MODC/TAGHI/BKGDADDR0/DATA0/PB0ADDR1/DATA1/PB1ADDR2/DATA2/PB2ADDR3/DATA3/PB3ADDR4/DATA4/PB4
ADD
R5/
DATA
5/PB
5AD
DR
6/DA
TA6/
PB6
ADD
R7/
DATA
7/PB
7XC
LKS/
NO
ACC
/PE7
MO
DB/
IPIP
E1/P
E6M
ODA
/IPIP
E0/P
E5EC
LK/P
E4VS
SRVD
DR
RES
ETVD
DPL
LXF
CVS
SPLL
EXTA
LXT
ALTE
STLS
TRB/
TAG
LO/P
E3R
/W/P
E2IR
Q/P
E1XI
RQ
/PE0
6059585756555453525150494847464544434241
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Figure 4. Pin Assignments MC9S12DB64 in 80 QFP
1234567891011121314151617181920
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
MC9S12DB6480 QFP
VRHVDDAPAD07/AN07/ETRIG0PAD06/AN06PAD05/AN05PAD04/AN04PAD03/AN03PAD02/AN02PAD01/AN01PAD00/AN00VSS2VDD2PA7/ADDR15/DATA15PA6/ADDR14/DATA14PA5/ADDR13/DATA13PA4/ADDR12/DATA12PA3/ADDR11/DATA11PA2/ADDR10/DATA10PA1/ADDR9/DATA9PA0/ADDR8/DATA8
PP4/
KWP4
/PW
M4
PP5/
KWP5
/PW
M5
PP7/
KWP7
/PW
M7
VDD
XVS
SXPM
2/R
X_BF
PM3/
TX_B
FPM
4/BF
_PSY
NPM
5/BF
_PR
OK
VREG
ENPS
7/SS
0PS
6/SC
K0PS
5/M
OSI
0PS
4/M
ISO
0PS
1/TX
D0
PS0/
RXD
0PM
6/BF
_PER
RBF
_PSL
MVS
SAVR
L
PWM3/KWP3/PP3PWM2/KWP2/PP2PWM1/KWP1/PP1PWM0/KWP0/PP0
IOC0/PT0IOC1/PT1IOC2/PT2IOC3/PT3
VDD1VSS1
IOC4/PT4IOC5/PT5IOC6/PT6IOC7/PT7
MODC/TAGHI/BKGDADDR0/DATA0/PB0ADDR1/DATA1/PB1ADDR2/DATA2/PB2ADDR3/DATA3/PB3ADDR4/DATA4/PB4
ADD
R5/
DATA
5/PB
5AD
DR
6/DA
TA6/
PB6
ADD
R7/
DATA
7/PB
7XC
LKS/
NO
ACC
/PE7
MO
DB/
IPIP
E1/P
E6M
ODA
/IPIP
E0/P
E5EC
LK/P
E4VS
SRVD
DR
RES
ETVD
DPL
LXF
CVS
SPLL
EXTA
LXT
ALTE
STLS
TRB/
TAG
LO/P
E3R
/W/P
E2IR
Q/P
E1XI
RQ
/PE0
6059585756555453525150494847464544434241
8 HCS12DB Family Product Proposal MOTOROLA
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Figure 5. MC9S12DB128 User Configurable Memory Map
$0000
$FFFF
$C000
$8000
$4000
$0400$0800$1000$2000
$FF00
EXT
NORMALSINGLE CHIP
EXPANDED SPECIALSINGLE CHIP
VECTORSVECTORS VECTORS
$FF00
$FFFF
BDM(If Active)
$C000
$FFFF
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$8000
$BFFF
16K Page WindowEight * 16K Flash EEPROM Pages
$4000
$7FFF16K Fixed Flash EEPROM
0.5K, 1K, 2K or 4K Protected Sector
$2000
$3FFF
8K Bytes RAM
Mappable to any 8K Boundary
$0800
$0FFF
2K Bytes EEPROM
Mappable to any 2K Boundary
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
The address does not show the map after reset, but a useful map. After reset the map is:$0000 - $03FF: Register Space$0000 - $1FFF: 8K RAM$0000 - $07FF: 2K EEPROM (not visible)
MOTOROLA HCS12DB Family Product Proposal 9
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Figure 6. MC9S12DB64 User Configurable Memory Map
$0000
$FFFF
$C000
$8000
$4000
$0400$0800
$1000
$3000
$FF00
EXT
NORMALSINGLE CHIP
EXPANDED SPECIALSINGLE CHIP
VECTORSVECTORS VECTORS
$FF00
$FFFF
BDM(If Active)
$C000
$FFFF
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
$8000
$BFFF
16K Page Windowfour * 16K Flash EEPROM Pages
$4000
$7FFF16K Fixed Flash EEPROM
0.5K, 1K, 2K or 4K Protected Sector
$2000
$3FFF
8K Bytes RAM
Mappable to any 4K Boundary
$0800
$0FFF
2K Bytes EEPROM
Mappable to any 2K Boundary
$0000
$03FF
1K Register Space
Mappable to any 2K Boundary
The figure shows a useful map, which is not the map out of reset. After reset the map is:$0000 - $03FF: Register Space$0000 - $1FFF: 8K RAM$0000 - $07FF: 2K EEPROM (not visible)
$0C00
10 HCS12DB Family Product Proposal MOTOROLA
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suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which
the failure of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2003
HCS12DBFAMILYPP/DRev. 0.7
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