Pipelining and number theory for multiuser detection Sridhar Rajagopal and Joseph R. Cavallaro Rice...

Pipelining and number theory for multiuser detection

Sridhar Rajagopal and Joseph R. Cavallaro

Rice University

This work is supported by Nokia, TI, TATP and NSF

Motivation

• Several multiuser detection schemes• Hardware implementation infeasible• Optimize algorithm + hardware

• Design a reduced complexity multiuser detection algorithm and its implementation for 3GPP W-CDMA

Approaches

• Algorithm– parallel interference cancellation– reduced complexity, parallel structure

• Pipelining – bit-streaming, avoid block detection

• Number theory– Most Significant Digit First (MSDF) computation– sign detection

Contributions

• decrease detection latency and storage requirements by window length (12X)

• On-line arithmetic based on MSDF computation– further latency reduction by 1.9X– increase in throughput by 3X– possible savings in area

Outline

• Parallel interference cancellation

• Pipelining

• On-line arithmetic

• Conclusions

• Current research directions

Multiuser detection

ri-2 ri-1 ri ri+1

Interference from previous bits of other

users

Interference fromfuture bits ofother users

Desired user

User 1

User j

ri

bibi+1

time

Multiuser detection

• Optimal - MLSE • Decorrelating• MMSE• Serial/Parallel interference

cancellation

• Top 3 require inversion of matrices• Block based detection

Parallel interference cancellation

)y(signd

d]SAARe[yy1l

lH

AAAAAA

AAAAAAAAAAAA

H1

H00

1H

H0 1

HH00H

H0

H

01

1101

100

00

0

00

d

d

d

d

D,K

D,1

1,K

1,1

Block based detection

Block detection

0 B its 1 -1 0 1 1 0 B its 1 -1 0 1 1 0 B its 1 -1 0 1 1

B its 1 -1 0 de te c te din a blo c k

M a tc he d F ilte r P IC (S ta g e 1 ) P IC (S ta g e 3 )

O ve rhe a d B its D e te c tio n W indo w (D = 1 2 )

Outline

• Parallel interference cancellation

• Pipelining

• On-line arithmetic

• Conclusions

• Current research directions

Parallel interference cancellation

)y(signd

d]SAARe[yy1l

lH

AAAAAA

AAAAAAAAAAAA

H1

H00

1H

H0 1

HH00H

H0

H

01

1101

100

00

0

00

d

d

d

d

D,K

D,1

1,K

1,1

1ii1i RdCdLdyy

Block Toeplitz structure - suitable for pipelining

Pipelined detection

5 6 7 8 9 1 0 1 1 1 21 2 3 4

5 6 7 8 9 1 0 1 1 1 21 2 3 4

5 6 7 8 9 1 0 1 1 1 21 2 3 4

5 6 7 8 9 1 0 1 1 1 21 2 3 4

M atch edF ilter

P IC (S tag e 1 )

P IC (S tag e 2 )

P IC (S tag e 3 )

T im e ( i )

^

^

^

^

d i

d i+ 2

d i-2

d i-4

M atc he d F i l te r

Adde r

L d i -1L T d i + 1 C d i

Si g nD e te c t i o n

Stag e 1

r i + 3 A0 , A1

C LR = L Td i + 2y i + 2

+

- --

^

^ ^ ^

Stag e 2

Ld iy i R = L T^

^ ^

D e l ay

D e l ay y i

R e c e i ve dSi g nal

C hanne lE s t i m ate s

Stag e 3

Cd i -2y i -2 R = L T^

y i -4^d i -4

D e te c te d bi ts

C

L

Being designed as a class project in Elec 422/423VLSI class

Outline

• Parallel interference cancellation

• Pipelining

• On-line arithmetic

• Conclusions

• Current research directions

Redundant number systems

• Conventional systems ( 0.34578, r=10)– radix r has r possible digits

• Redundant (0.34578,0.35578,…. r=10)– >r possible digits.

• Limit carry propagation• Totally parallel addition/subtraction ONLY.

On-line arithmetic

• Uses a redundant number system• Pipelined bit-serial arithmetic• Most Significant Digit First computation• Successive computations as soon as

inputs available ( = 1-4, typically)• Can do operations such as addition,

multiplication, division, square-root etc.

On-line detection and decoding

C h an n e lE s tim a tio n

D e tec tio n D eco d in g

A n ten n a

D eco d edIn fo rm a tio n b its

H ard d ec is io n do r so ft d ec is io n y

R F U nit A /D D em ux

Entire chain can be done on-line

Work with hard decisions (sign of MSD) simple way to use softer decisions (2 or more digits)

On-line arithmetic for detection

d p = s ig n (A H r)

O n-l i ne Si ng l e U s e r D e te c to rC o nve nt i o nal S i ng l e U s e r D e te c to r

A Hp ,1 A H

p ,2 A Hp ,N -1

+

+

+

+

+

A H r

A Hp ,N

* * * *

r0 r1 rN - 1 rN

A Hp ,1 A H

p ,2 A Hp , N -1

+

+

+

+

+

A Hp ,N

* * * *

r0 r1 rN - 1 rN

d p = s ig n (A H r)

L ate nc y = lo g2(d)* t co n v* ( lo g2(N ) + 1 ) L ate nc y = tO L* ( lo g2(N )+ 1 ) + t s t o p

Single user detector using Conventional arithmetic

L ate nc y = Thr o ug hput = lo g2(d)* t co n v* ( lo g2(N ) + 1 )

d i - 1 d i d i +1

N * N /2 + 1 log 2 (d)* tc o n v

Conventional arithmetic - matched filter

Single user detector using On-line arithmetic

N m u ltip lic a tio n s in p ar a lle l ( N * )

N /2 ad d it io n s in p ar a lle l ( N /2 + )

N /4 ad d it io n s in p ar a lle l

N /8 ad d it io n s in p ar a lle l

F in a l ad d it io n b ef o r e s ig n ( 1 )

L ate nc y = tO L* ( lo g2(N )+ 1 ) + t s t o p

Thr o ug hput = m * tO L

T r ee ad d it io n

S to p ! S ig n d ig it d e tec ted

0 < = t s t o p < m * tO L is the t im e fo r the f i r s t no n-ze ro digi tm = d/ lo g2( r ) is the no . o f digi ts

d i - 1 d id i +1

m * tO L

tO L * ( lo g 2 ( N ) + 1 )

t s t o p

tO L

On-line matched filter

M atc he d F il te rtC M F = ( lo g2(N )+ 2 )* lo g2(d) * t co n v

P IC - S tage 1tC P IC = ( lo g2(K )+ 3 )* lo g2(d) * t co n v

P IC - S tage 2tC P IC t im e

P IC - S tage S = 3tC P IC t im e

Bit Parallel Conventional arithmetic

L ate nc y = (2 * S-1 )* tC P IC + 2 * tC M F

Thr o ug hput = tC P IC

d i

d i

d i +1

d i +1

d i

d i

d i +1

d i +1

y i , y i +1 ,

tCMF

tCPIC

Conventional multiuser detection

Digit Serial On-line arithmetic

0 < = t s t o p < m * tO L

L ate nc y = tM F + m * S* tO L+ S* tP IC

Thr o ug hput = m * tO L

d i d i +1y i y i +1

d i

d i

d i

d i +1

d i +1

d i +1

M atc he d F i l te rtM F = ( lo g2(N )+ 2 )* tO L + t s t o p

P IC - S tage 1tP IC = ( lo g2(K )+ 3 )* tO L + t s t o p

P IC - S tage 2tP IC t im e

P IC - S tage S = 3tP IC t im e

m*tOL

tMF

tPIC

ts top

On-line multiuser detection

Comparisons

N = K =32, d = 8, S = 3, r = 4, tol = 2, tconv = 1, tstop = 2

Outline

• Parallel interference cancellation

• Pipelining

• On-line arithmetic

• Conclusions

• Current research directions

Conclusions

• Techniques such as pipelining and on-line arithmetic can be used to implement multi-user detection for W-CDMA.

• Lower latency• Higher throughput• Smaller area• Simple hardware - adders and multipliers

Current research directions

• Reconfigurable computing -RENE

• Chameleon - hardware

• mNIC card