Partially based on Prof . Vishwani D. Agrawal lecture VLSI Testing

Partially based on Prof. Vishwani D. Agrawal lecture VLSI Testing

and book by S. Mourad, Y. Zorian, "Principles of Testing Electronic Systems”

ECE 617 - Fault Testable DesignDr. Janusz Starzyk

School of EECSOhio UniversityAthens, OH, 45701

http://www.arltesting.com/

IC Testing Machine

(IC81-0444-467)

3360-P VLSI Test System

Definition ofTesting

Outline

Reliability and testingDesign ProcessVerification & testingFaults and their detectionFault coverageTypes of testsTest applicationsDesign for TestTest economics

0.18u VLSI silicon neuronshttp://www.ini.uzh.ch/node/21083

Reliability and Testing

Reliability of electronics systems is no longer limited to military, aerospace or bankingUsed by almost everyone in the workplaceApplied to smaller and smaller devicesHave continually new failure modesReliability depending on being error freeFailures in both software and hardwareHere we concentrate on hardware

The goal over time is to reduce the cost of manufacturing the product by reducing the per-part recurring costs:

- reduction of silicon cost by increasing volume and yield, and by die size reduction (process shrinks or more efficient layout)

- reduction of packaging cost by increasing volume, shifting to lower cost packages if possible (e.g., from ceramic to plastic), or reduction in package pin count

Test Objective

- reduction in cost of test by:- reducing the vector data size- reducing the tester sequencing complexity- reducing the cost of the tester- reducing test time- simplifying the test program

Test Objective

Controller(algorithm)

RAM

UDL UDL

RAM

DSP(Netlist)

Micropro.(Layout)

Interface Block(RT Level )

FPGA

A System on a Chip

Verification and Testing

Testing a circuit prior to fabrication is known as design verificationVerification is certainly done at various stages of the design processMost viable design verification is through simulationTesting is identifying that the fabricated circuit is free from errorsNeed to specify what errors testing is looking for

BehaviouralDescription

BehavioralDFT

Synthesis

RTL Description

LogicDFT

Synthesis

Gate Description

Test PatternGeneration

FaultCoverage?

Manufacturing

Good Product

Test Application

Product

TechnologyMapping

Layout

ParameterExtraction

Gate

Libraries

Libraries

low high

DFT Cycle

Test Programming

Types ofLogic Faults

Types ofPhysical Faults

Faults and their Detection

Physical failures are manifested as electrical failures and are interpreted as faults on the logic levelSeveral physical defects may be mapped into few fault typesThe main fault type is Stuck-at FaultA fault is detected by a test patternTest pattern is an input combination that confirms the presence of the fault

ZB

A R 1

R 2

RL

BA Z

ZA

A Z

(a) (b)

Possible Defects

Two technologies, two physical defects map into the same stuck-at zero faultNotation used - A SA0, A@0, or A/0

Inputs FF Faulty ResponseAB Response A/0 B/0 Z/0 A/1 B/1 Z/100 0 0 0 0 101 0 0 0 0 110 0 0 0 1 111 1 0 0 1 1

A

BZ

Detecting Stuck-at Faults

Fill in the blanks in faulty response A/0 and A/1

Inputs FF Faulty ResponseAB Response A/0 B/0 Z/0 A/1 B/1 Z/100 0 0 0 0 0 0 101 0 0 0 0 1 0 110 0 0 0 0 0 1 111 1 0 0 0 1 1 1

A

BZ

Detecting Stuck-at Faults

Detecting Stuck-at FaultsA

BZ

Inputs Fault Free Faulty ResponsesAB Response A/0 B/0 Z/0 A/1 B/1 Z/100 0 0 0 0 0 0 101 0 0 0 0 1 0 110 0 0 0 0 0 1 111 1 0 0 0 1 1 1

Sequential CircuitR

S

QA

2

1

Inputs FF Faulty ResponseSR Response A/0 S/0 R/0 A/1 S/1 R/1

01 0 0 0 X 0 0 100 0 1 0 X 1 0 110 1 1 0 1 0 1 111 0 0 0 1 1 1 1

Types ofTesting

Types of Tests

The exhaustive test used to detect the faults on a 2-input AND gate is not practical for circuits with 20 or more primary inputsPseudo-exhaustive: exhaustive for components in the circuits

segmentation or partitioning

A random test is also viable to detect faults, but pseudo-exhaustive tests are more realistic for Stuck-at FaultsDeterministic or fault oriented tests

Functional Testing

Exhaustive & pseudo-exhaustive testing :

Partial dependence circuits:-a circuit in which primary outputs (PO)

depend on all the primary inputs (PI)- each output tested using 2ni inputs

(ni < n shows inputs affecting PO)

Functional Testing

Example :

Exhaustive & pseudo-exhaustive testing

Exhaustive test for each gate

Functional Testing

the circuit is partitioned into segments such that each segment has small number of inputseach segment is tested exhaustivelyusually inputs & output of each segment are not PIs or POs so we need to control segment inputs using PIs and observe its outputs using PO - this lead to sensitizing partitioning

Exhaustive & pseudo-exhaustive testing Partitioning technique :

Functional Testing

Example : Consider the following circuit :

Functional Testing

Example: the following shows 8 input vectors to test exhaustively h.

Functional Testing

Example: Add vectors 5 - 8 to test exhaustively g and 9 -10 to test exhaustively y

Functional Testing

Example: Add missing combinations to vectors 4 and 9 to test exhaustively x

Types of Testing

Verification testing, characterization testing

Verifies correctness of design and correctness of test procedureMay require correction of either or both

Manufacturing testingFactory testing of all manufactured chips for parametric and logic faults, and analog specificationsBurn-in or stress testing

Acceptance testing (incoming inspection)User (customer) tests purchased parts to ensure quality

Verification Test

Very expensiveApplied to selected partsUsed prior to production or manufacturing test

May comprise:Scanning Electron Microscope testsBright-Lite detection of defectsElectron beam testingArtificial intelligence (expert system) methodsRepeated functional tests

Manufacturing TestDetermines whether manufactured chip meets specificationMust cover high % of modeled faultsMust minimize test time (to control cost)No fault diagnosisTest at rated speed or at maximum

speed guaranteed by supplier

Burn-in or Stress TestProcess:

Subject chips to high temperature and over-voltage supply, while running production tests

Catches infant mortality casesThese are damaged or weak (low reliability) chips that will fail in the first few days of operation Burn-in causes bad devices

to fail before they are shipped to customers

Manufacturing Test Scenarios

Wafer sort or probe test Done before wafer is scribed and cut into chipsTest devices are checked with specific patterns to measure:• Gate threshold• Polysilicon field threshold• Poly sheet resistance, etc.

Packaged device tests

Types of TestsParametric – measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheapFunctional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive

http://www.ece.unm.edu/~jimp/vlsi/slides/c1_intro-8.gif

Functional TestATE and Manufacturing World – any vectors applied to cover high % of faults during manufacturing testAutomatic Test-Pattern Generation World – testing with verification vectors, which determine whether hardware matches its specification – typically have low fault coverage (< 70 %)

Levels of testing

LevelsChipBoardSystem

• Boards put together• System-on-Chip (SoC)

System in field

Cost – Rule of 10It costs 10 times more to test a device as we move to higher levels in the product manufacturing process

Mixed Signal VLSI Circuit

Levels of testing

Other ways to define levels – these are important to develop correct “fault models” and “simulation models”

TransistorGateRTLFunctionalBehavioralArchitecture

Focus: Chip level testing – gate level design

Typical Test Program

1. Probe test (wafer sort) Catches gross defects

2. Contact electrical test3. Functional & layout-related test4. DC parametric test5. AC parametric test

Unacceptable voltage/current/delay at pin Unacceptable device operation limits

Rise/fall Time Tests

Set-up and Hold Time Tests

Propagation Delay Tests

1. Apply standard output pin load (RC or RL)2. Apply input pulse with specific rise/fall3. Measure propagation delay from input to

output Delay between 5 ns and 40 ns (ok) Delay outside range (fails)

Circuit UnderTest

Checker

EncodedOutputN N

N

P

On Line Testing

Embedded checkers – error detectionPeriodic diagnostic programsWatchdog checkers

Analog

Logic

RAM

Embedded testExternal test

High BandwidthLow Bandwidth

Source/sink

Logic

RAM

Analog

Embedded testExternal test

High Bandwidth

On- vs Off-Chip Testing

Off chip test On chip test

Test Specifications & Plan

Test Specifications:Functional CharacteristicsType of Device Under Test (DUT)Physical Constraints – package, pin numbers, etc.Environmental Characteristics – power supply, temperature, humidity, etc.Reliability – acceptance quality level (defects/million), failure rate, etc.

Test plan generated from specificationsType of test equipment to useTypes of testsFault coverage requirement

Test Data Analysis

Uses of ATE test data:Reject bad DUTsFabrication process informationDesign weakness information

Devices that did not fail are good only if tests covered 100% of faultsFailure mode analysis (FMA):

Diagnose reasons for device failure, and find design and process weaknessesImprove logic and layout design rules

Testers cost over $1 000 000

Cost of Testing

VLSI Test System TS600

Cost of Testing

Design for testability (DFT)Chip area overhead and yield reductionPerformance overhead

Software processes of testTest generation and fault simulationTest programming and debugging

Manufacturing testAutomatic test equipment (ATE) capital costTest center operational cost

Cost of Manufacturing Testing

Example test cost:0.5-1.0GHz, analog instruments,1024 digital pins: ATE purchase price

= $4.272M

Running cost (five-year linear depreciation)= Depreciation + Maintenance + Operation

= $0.854M + $0.085M + $0.5M= $1.439M/year

Test cost (24 hour ATE operation)= $1.439M/(365 x 24 x 3,600)= 4.5 cents/second

Good

Bad

PCB for 16 channel pin

card for IC tester henning-eng.com/pcb800.htm

Time in Months

Reve

nues

TTime toMarket

Loss ofRevenues

Time to Market

Test Economics

The life cycle of a product is shorter than its design cycleTime to market needs to be shortenTesting is necessary for reliability and for improving yield

VLSI Defects

Faulty chips

Good chips

Unclustered defectsWafer yield = 12/22 = 0.55

WaferDefects

Clustered defects (VLSI)Wafer yield = 17/22 = 0.77

Smaller dies

Wafer yield = 78/88 = 0.88

Yield and Defect Level

Defect Level

1

0.1

0.01

0.001

%

TT%

DPM

10000

5000

1000

500

100

50

10

.01 0.1 1 1099.99 99.9 99 90

Y=50% Y=90%

C%

Fault coverage

Test transparency

Yield

Multi-site Testing

One ATE tests several (usually identical) devices at the same timeBoth probe and package testDUT interface board has > 1 socketsUsually tests 2 or 4 DUTS at a time Usually test 32 or 64 memory chips at a timeLimits: # instruments available in ATE, type of handling equipment available for package

Example VLSI Test Systems

Advantest T3347BLow-cost Parallel Testing of Four High-end MCU and Testing of Large ASIC

40 MHZ testing speed. Accommodates up to 512 I/O pins. Simultaneous testing of up to four devices per station.

ADVANTEST Model T6682 ATE

T6682 ATE Block Diagram

T6682 ATE Specifications

Uses 0.35 mm VLSI chips in implementation1024 pin channelsSpeed: 250, 500, or 1000 MHzTiming accuracy: +/- 200 psDrive voltage: -2.5 to 6 VClock/strobe accuracy: +/- 870 psClock settling resolution: 31.25 psPattern multiplexing: write 2 patterns in one ATE cyclePin multiplexing: use 2 pins to control 1 DUT pin

T6682 Pattern Generation

Sequential pattern generator (SQPG): stores 16 M vectors of patterns to apply to DUT, vector width determined by # DUT pins

Algorithmic pattern generator (ALPG): 32 independent address bits, 36 data bits

Scan pattern generator (SCPG) supports JTAG boundary scan, greatly reduces test vector memory for full-scan testing

T6682 Test Data Analysis

Uses of ATE test data:Reject bad DUTSFabrication process informationDesign weakness information

Devices that did not fail are good only if tests covered 100% of faultsFailure mode analysis (FMA)

Diagnoses reasons for device failureFinds design and process weaknessesAllows improvement of logic & layout design rules

T6682 Probe Card

Probe card – custom printed circuit board (PCB) on which DUT is mounted in socket

may contain custom measurement hardware

Probe needles come down and scratch the pads to stimulate/read pins

Membrane probe – for unpackaged waferscontacts printed on flexible membrane, pulled down onto wafer with compressed air

LTX FUSION HF ATE

Specifications

Intended for SOC test digital, analog, and memory test supports scan-based test

Modular can be upgraded with additional instruments

enVision Operating Systemmaximum 64 M vectors memory storage

1 or 2 test heads per tester, maximum of 1024 digital pins, 1 GHz maximum test rateAnalog instruments:

DSP-based synthesizers, digitizers, time measurement, power test, radio frequency source and measurement capability (up to 4.3 GHz)

ADVANTEST Model T2000 ATEScalable Architecture

Microsoft Windows 2000

C++(Microsoft Visual Studio Professional)

OTPL(Open Architecture Test System Programming Language)

Re-configurable Program Structure for test data and algorithm

T2000 System Software Emulator

Wave Tool (Logic Analyzer, Oscilloscope).

ADVANTEST T6577

Tests SoC/Mixed-Signal

Devices Supports for a maximum of 1024 logic and/or I/O channels. Performs parallel test of up to 32 devices Supports baseband, DVD read channel, and jitter test At-speed test of high-speed memory interfaces Test rates of up to 667 Mbpsmaximum of eight channels