Overview of Activities at COMSATS Presented by: Team Leader: Hira KhanDr. Arshad S. Bhatti Sujjia...

Overview of Activities at COMSATS

Presented by: Team Leader:

Hira Khan Dr. Arshad S. Bhatti

Sujjia Shaukat

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Inner Tracking System (ITS)Present ITS Upgraded ITS

SSDSDDSPD

New ITS - 7 Layers Silicon Pixel Detector - Monolithic

12.5 G-pixel camera(~10 m2)

Current ITS - 6 Layers 3 different Silicon detectors

Beam pipe

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Technologies for Silicon Pixel Detectors• There are two technology concepts for silicon pixel detectors:

Monolithic Active Pixel Sensor Hybrid Pixel Detector (MAPS)

The sensor and the front end electronics is implemented on separate silicon chips

The pixel detector and the read out electronics is implemented on same silicon chips

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Explorer Series

• They are pixel prototypes developed at CERN as a part of the ongoing research and developments for the ALICE ITS Upgrade to optimize the diode layout, for the charge collection efficiency.

• The detector design motivation is to reduce the power density in the detection layers.

• The Explorer chip is divided into two sub-matrices containing pixels with two different pixel pitches. Each sub-matrix is divided into nine sectors, each having a different pixel variant.

• In Explorer-1, the width allocated for the collection electrode (the n-well diameter plus the spacing) is kept constant at 7.2 μm.

Total number of pixels = 11700 pixelsTotal area of each sub-matrix = 3240000 μm2

Spacing SpacingDiameter

p- p-p+ p+

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Collection diode layouts

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Objective

• To simulate MAPS collecting diodes of different geometric shapes and sizes and then observe their effects on the depletion region.

• To propose diode structures with different doping concentrations to enhance the sensing volume of the device and give better electrical performance.

• To study the effect of radiation on charge density in the diode.

• To study the effect of length of epitaxial layer on doping concentration of the device.

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Simulation Software: Synopsys Sentaurus TCADIndustry-Standard Process and Device Simulators

• Technology Computer Aided Design (TCAD)

• Reduces technology development time and cost

• Supports fast prototyping, development, and optimization of semiconductor technologies with comprehensive physics-based process modeling capabilities

• Provides insight into advanced physical phenomena through self-consistent multidimensional modeling capabilities, improving device design, yield, and reliability

• Provides full-flow 3-D process and device simulation flows, with advanced structure generation, meshing and numeric.

Start

Sentaurus WorkBench

Sentaurus Device Editor

Sentaurus Device

Define Variables

End Simulation

Error in Input command

(Physics) and parameter file

ErrorRun Simulation

Error in Input command and grid file

yesno

View structure and graphs in Sentaurus Visual and INSPECT

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21μm

20μm20μm

Explorer-0 (Sector 4) Explorer-1 (Sector 1)

Doping Profile and parameters of collection electrodes

P-type Epitaxial layer, 1e12cm-3

P-type Substrate, 1e15cm-3

3μm

20μm

21μm

2μm18μm

N type doping, 1e18cm-3,N doped width: 3μm,N contact: 3μm

P-contact: 20 μm

21μm

20μm

20μm

Space, 3.375μm

P-type Epitaxial layer, 1e12cm-3

P-type Substrate, 1e15cm-3

20μm

21μm

N-type doping, 1e18cm-3,N doped width: 0.45μm,N-contact: 0.45 μm

2μm

18μm

P-type doping, 1e18cm-3

3μm

P-contact: 20 μm

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Electric Field Region

Electric Field Region

𝒓 𝒛

𝒓 𝒙𝒓 𝒚¿

Depletion zone volume calculation

Volume Calculation:

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Depletion zone volume calculation

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Electrical characteristics measurements• Current density of each sector of Explorer-1:

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1e15 cm-3

1e14 cm-3

1e13 cm-3

1e12 cm-3

• Variation in doping profiles of MAPS:At constant anode doping, variation in P-type epi-layer doping

profiles of MAPS:

Sector 3 (Explorer-1)Epi-layer Doping:

Optimization of Monolithic Active Pixel Sensors (MAPS)

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Optimization of Monolithic Active Pixel Sensors (MAPS)

• Variation in doping profiles of MAPS:• At constant epi-layer doping, variation in N-type anode doping

profiles of MAPS:

Sector 3 (Explorer-1)N Doping:

0.5e18 cm-3

2e18 cm-3

4e18 cm-3

6e18 cm-3

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• With increase of N doping, the reverse current increases .The increase in doping causes increase in depletion region.

Current - Voltage measurements

Anode doping concentration

(cm-3)

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• Diamond shaped matrix of Sector 1 (Explorer-1)

• Variation in geometry of pixels in submatrix

– Electric Field at reverse biased voltage of 7V(cross-sectional view)

Optimization of Monolithic Active Pixel Sensors (MAPS)

21μm

40μm

40μm

P-type Epitaxial layer, 1e12cm-3

P-type Substrate, 1e15cm-3

20μm

20μm

10μm

10μm

P-type doping, 1e18cm-3

N type doping, 1e18cm-3,N doped width: 0.45μm,N contact: 0.45μm,Space N+ vs. P+, 3.375μm

11.26μm4.35μm

15.03μm7.44μm 7.44μm

Depletion region

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0.69μm4.5μm

6.94μm11. 63μm 11.63μm

Depletion region

20.97 μm

5.64μm

This region can be utilized for VLSI implementation

This region can be utilized for VLSI implementation

• Optimized Diamond shaped matrix of Sector 1 (Explorer-1)

– Electric Field at reverse biased voltage of 7V(cross-sectional view)

Optimization of Monolithic Active Pixel Sensors (MAPS)

12μm

12μm

14μm

14μm

21μm40μm 40μm

N type doping, 1e18cm-3,N doped width: 0.45μm,N contact: 0.45μm,Space N+ vs. P+, 3.375μm

P-type Epitaxial layer, 1e12cm-3

P-type Substrate, 1e15cm

-3

P-type doping, 1e18cm-3

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Available region for front-end complex CMOS circuitry

• Optimized Diamond shaped matrix of Sector 1 (Explorer-1)

Optimization of Monolithic Active Pixel Sensors (MAPS)

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16μmP-type doping, 1e18cm -3

16μm

16μm

N type doping, 1e18cm-3,N doped width: 2 μm,N contact: 2 μm,Space N+ vs. P+, 2.6 μm

18.71μm 9.59μm 18.71μm

6.13μm6.86μm6.86μm

6.13μm

2.36μm

28.34 μm

Depletion Region of optimized Sector 3

Space for VLSI Implementation

Space for VLSI Implementation

• Optimized Diamond shaped matrix of Sector 3 (Explorer-1)

– Electric Field at reverse biased voltage of 7V(cross-sectional view)

Optimization of Monolithic Active Pixel Sensors (MAPS)

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P type doping, 1e18cm-3

P-type Epitaxial layer, 1e12cm-3

P-type Substrate, 1e15cm

-3

16μm

N type doping, 1e18cm-3,N doped width: 2 μm,N contact: 2 μm,Space N+ vs. P+, 2.6 μm

16μm16μm

• Optimized Hexagonal shaped matrix of Sector 3 (Explorer-1)

– Electric Field at reverse biased voltage of 7V(cross-sectional view)

Optimization of Monolithic Active Pixel Sensors (MAPS)

Depletion region of optimized hexagonal shaped Sector 3

Space for VLSI Implementation

Space for VLSI Implementation

18.75 μm 18.75 μm9.75 μm

6.17 μm6.93 μm 6.93 μm

6.17 μm

1.87 μm

28.07 μm

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15.7um

16.5um

16.5um

16.5um

13.26um

10.37um 10.37um10.51um 10.51um

1.45um

45.14um

15.72um

• Extension of optimized Hexagonal shaped matrix of Sector 3 (Explorer-1)

– Electric Field at reverse biased voltage of 7V(cross-sectional view)

Optimization of Monolithic Active Pixel Sensors (MAPS)

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Current - Voltage measurements

• Reversed current was minimized in case of extended hexagonal shaped matrix.

Effect of radiation on Charge Density of the device

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Charge Density of the device when no radiation was passed (at -2V)

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Applying radiation effects in the device

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Irradiating the device diagonally

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Charge Density of the irradiated device (at -2V)

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Charge Density of the device when no radiation was passed (at -3V)

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Charge Density of the irradiated device (at -3V)

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I-V curve of radiated and non-radiated structure

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Charge Density of the device when no radiation was passed (at -7V)

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Charge Density of the irradiated device (at -7V)

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I-V graphs of the structure at different trap densities

Effect of different Epitaxial layer height on doping concentration of Explorer pixel

sensor (ALICE-ITS) using TCAD Sentaurus Process

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Flowchart of Epitaxial growth using Sentaurus Process

Silicon Epitaxial layer growth on low resistive P-type Silicon substrate

P-type doping of Epitaxial layer

Annealing at 1100 °C for activation of Boron Dopants

Etching for Step-like structure

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Epitaxy dimension of different lengths

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Doping profile and dimensions of Epilayer

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Effect of Constant Doping of Boron on different length Epitaxial layer

-50 -40 -30 -20 -10 0 10

1E12

1E13

1E14

1E15

Different length Epitaxy grown for Constant Doping of BoronC

oncentration (cm

-3)

Height (um)

20um 30um 40um

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Dimension of Step-like Structure of Graded Boron Epitaxial growth

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Boron Concentration for Step-like structure

-90 -80 -70 -60 -50 -40 -30 -20 -10 0 10

1E12

1E13

1E14

1E15

1E16

1E17

1E18B

oro

n C

oncentration (cm

-3)

Depth (um)

20um 30um 40um

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• All the diode designs for Explorer-0 and Explorer-1 chip were simulated using Synopsys Sentaurus TCAD tools: SDE, SDEVICE and SVISUAL.

• The depletion regions volumes of sector 3 and 9 were calculated to be maximum of 517.81 μm-3 and 497.85 μm-3 respectively.

• In case of varying the doping profiles of the device, maximum depletion region volume was obtained for P doping of 1e12cm-3 and N doping of 6e18cm-3 as according to following:

• It was found that by shifting the anodes at the center in form of Extended Hexagonal shape enhance the depletion region volume upto 35%. This geometry not only enhance the depletion zone volume but also create more space for complex VLSI implementation.

• An increase in the reverse current was observed when the device was irradiated with a Gaussian profile at trap density of 1e14cm-3.

Conclusion

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• To calculate capture efficiency of the irradiated device.

• To study the effect of radiation when traps are outside the sensitive region of the device.

Future Work

• To apply voltages at etched surfaces

• To calculate resistivity of structure at different points

ALICE ITS Readout Electronics Inner Barrel Emulator card

Group Members: Team Leader:

Hira Ilyas Dr. Arshad S. BhattiMadiha Tajwar

Jibran Ahmed

Raise Akram (carrier board)

Inner Barrel Emulator card

• Each spartan6 will emulate a single chip.

• Each spartan will send data 1.2Gbps on diff line.

• Readout prototype board will receive data on 9 differential lines from 9 spartans.

• Firmware is written for single spartan and it will copy in all nine.

• 8 bit Data, master clock and control lines will be driven by readout prototype board (plus PC through USB controller)

Architecture of IOBE Board

Total Signals Set-up for single Chip (SP6)

SPARTAN 6

Power

USB JTAG

Platform flash

User clockGTP clock

High speed serial data

Controls

SPI header

• Hardware Requirement:

Spartan-6

• Software Requirements:

Vivado

Spartan-6, GTP Transceivers Wizard

System Requirements

Spartan-6, GTP Transceivers Wizard

• Ref_clk=125MHz

• TX Line Rate=1.25 Gbps

• RX Line = 2.5 Gbps

• Data Path Width= 16 bits

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Thank you