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© K.T. Tim Cheng, 02_fault_model, v1.0 1
© K.T. Tim Cheng, 02_fault_model, v1.0 2
Outline – Fault Modeling• Why Model Faults
• Single Stuck-at Faults
• Fault Collapsing
• Fault Detection and Redundancy
• Other Common Fault Models• Transistor faults
• Bridging faults
• Delay faults
• Memory faults
2
© K.T. Tim Cheng, 02_fault_model, v1.0 3
Why Model Faults?
• I/O function tests inadequate for manufacturing (functionality vs. component & interconnection testing)
• Fault model identifies target faults• Fault model makes analysis possible• Effectiveness measurable by
experiments
© K.T. Tim Cheng, 02_fault_model, v1.0 4
Some Real Faults In Chips• Processing faults
– Missing contact windows– Parasitic transistors– Oxide breakdown
• Material defects– Bulk defects (Cracks, Crystal imperfections)– Surface impurities (Ion migration)
• Time-dependent failures– Dielectric breakdown– Electromigration
• Packaging failures– Contact degradation– Seal leaks
3
© K.T. Tim Cheng, 02_fault_model, v1.0 5
Some Fault Models• Single stuck-at faults• Transistor open/short faults• Bridging faults• Delay faults• Memory faults• Analog faults
© K.T. Tim Cheng, 02_fault_model, v1.0 6
Single Stuck-At Faults
Assumptions: 1. Only one line is faulty2. Faulty line permanently set to 0 or 13. Fault can be at an input or output of a gate
11
00
1
0 (1)
0 (1)
TEST VECTOR
TRUE RESPONSE
FAULTY RESPONSE
STUCK - AT - 1
4
© K.T. Tim Cheng, 02_fault_model, v1.0 7
Single Stuck-At Fault• Most widely studied and used
• It represents many different physical faults
• It is independent of technology
• Experience has shown that tests that detect SSFs detect many nonclassical faults as well
• The number of SSFs in a circuit is small.– Moreover, the number of faults to be explicitly
analyzed can be reduced by fault collapsing techniques.
© K.T. Tim Cheng, 02_fault_model, v1.0 8
Role of Fault Collapsing
DUT
Generate fault list
Collapse fault list
Generate test vectors
Fault Model
Requiredfault coverage
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000
5
© K.T. Tim Cheng, 02_fault_model, v1.0 9
Definitions• Given
– T1 is set of all tests for fault F1– T2 is set of all tests for fault F2
• F2 dominates F1
• F1 and F2 are equivalent
T2 T1
T1=T2
© K.T. Tim Cheng, 02_fault_model, v1.0 10
Fault Equivalence•Two equivalent faults are detected by exactly
the same tests
Example : Three faults shown are equivalent
s - a - 0s - a - 1
s - a - 1
6
© K.T. Tim Cheng, 02_fault_model, v1.0 11
Equivalence Fault Collapsing
•N+2 faults in N-input gate
s - a - 1
s - a - 1s - a - 1s - a - 0
s - a - 1s - a - 0
s - a - 0
s - a - 0
© K.T. Tim Cheng, 02_fault_model, v1.0 12
Equivalent Fault Collapsing0
0
0
0
0
0 00
0
00
0
( a )
00
00
( b )
7
© K.T. Tim Cheng, 02_fault_model, v1.0 13
• b s.a.0 & f s.a.0 are equivalent while they cannot be identified by simple structure analysis.
x
xf
s. a. 0
s - a. 0
b
Functional Equivalence
© K.T. Tim Cheng, 02_fault_model, v1.0 14
Dominance Fault Collapsing
• If any test for F1 detects F2 but converse is not true, then F2 dominates F1
• Only N+1 faults in an N-input gate
F1: s - a - 1F2: s - a - 1
x
x
s - a - 1
s - a - 1s - a - 0
T2 T1
8
© K.T. Tim Cheng, 02_fault_model, v1.0 15
Checkpoint Faults• Checkpoints
– Primary inputs– Gate-inputs fed by fanout lines
• Checkpoint faults– Sufficient to model stuck-at faults at checkpoints– Model only input faults in fanout-free circuit
© K.T. Tim Cheng, 02_fault_model, v1.0 16
• Theorem: In a fanout-free combinational circuit C, any test set that detects all single stuck-at faults on the primary inputs of C detects all SSFs in C.
• Theorem: In a combinational circuit, any test which detects all single (multiple) stuck faults on all checkpoints detects all single (multiple) faults in the circuit.
Theory on Checkpoint Faults
9
© K.T. Tim Cheng, 02_fault_model, v1.0 17
Fault Detection• For combinational circuits: A test vector t
detects a fault f iff Zf(t) ≠ Z(t)
Example :
Z (A, B, C) = AC + BCZf (A, B, C) = BC
t = (1, 0, 0) is a test for A s.a.0. fault
As. a. 0
C
B
X
18
Z = (X2 + X3) X1 + X1 X4
Fault: X4 s-a-0 ⇒ Zf = (X2 + X3) X1
⇒ Z(x) ⊕ Zf(x) = X1 X4 = 1
Any of the four tests: 0 0 0 1, 0 0 1 1, 0 1 0 1, 0 1 1 1 detects f
Z
X1
X2
X3
X4
Fault Detection – An Example
10
19
Sensitization
Two basic concepts in fault detection:•Activation: Creating different V & Vf values at
the fault site.– Example: Create a 0 at G2 for G2 s.a.l
V/Vf : V : Signal values in the fault free cktVf : Signal values in the faulty ckt
G1
G3
G4
G5
X2
X1
X3
X4s. a. 1
x0/1
0/1
0/10
000
1
1
G2
20
• Propagating fault effect to a primary output– Example: the fault effect propagates along
the path G2, G4, G5
– A line is sensitized to the fault by the test t if its value in the test t changes in the presence of the fault f• Example: G2, G4 and G5 are sensitized.
– A path composed of sensitized line is called a sensitized path.• Example: path G2-G4-G5 is a sensitized path
Error Propagation
11
© K.T. Tim Cheng, 02_fault_model, v1.0 21
Detectability & Redundancy• A fault f is said to be detectable if there
exists a test t that defects f; otherwise, f is undetectable
• For combinational circuits, an undetectable fault is corresponding to a redundant wire.
• If l s.a.1 is undetectable, the gate can be simplified as
xmn
ls. a. 1
Y Y1
ml
n
Yn
m
© K.T. Tim Cheng, 02_fault_model, v1.0 22
• If l s.a.0 is undetectable, the entire gate can be removed & replaced by a constant 0 wire
xmn
ls. a. 0
Y Y0
ml
n
0 Y
Redundancy
12
© K.T. Tim Cheng, 02_fault_model, v1.0
Example: Redundancy Removal
B
C
A
Conflict!
1
1
1 s.a.00
0
0AB
C
1 Z Z
Z is glitch-free Z may have glitches
• Warning: Redundancy may be required for glitch-free designs!!• If having glitches is not a concern (e.g. synchronous designs),
redundancy can be removed.
© K.T. Tim Cheng, 02_fault_model, v1.0 24
Fault Detection for Sequential Circuits
• Fault detection requires a sequence of vectors, not just one vector.
• Suppose T: A sequence of vectorsR(q,T): Output response w/ initial state being qRf(q,T): Output response w/ initial state being q and
fault f is present.
• T strongly detects the fault f iff R(q, T) ≠ Rf(qf, T)for every possible pair of initial states q & qf.
13
© K.T. Tim Cheng, 02_fault_model, v1.0 25
y1
y1
y2
y2
X
D
D
y1
y2
y1
y2
y2
y1
X
X
Y2
Y1
b
a
y2
y1
X
An Example
© K.T. Tim Cheng, 02_fault_model, v1.0 26
X
0 1 Y 1 Y 2
A A , 0 D , 0 0 0
B C , 1 C , 1 0 1
C B , 1 A , 0 1 1
D A , 1 B , 1 1 0
State table:
I n i t i a l S t a t e
O u t p u t S e q u e n c e t o T = 1 0 1 1 1
F a u l t - f r e e a s - a - 1 b s - a - 0
A 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1
B 1 1 1 0 0 1 1 1 0 0 1 1 1 0 1
C 0 0 0 1 1 0 0 0 1 0 0 1 0 1 0
D 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0
•T strongly detects b s-a-0.•T does not strongly detect a s-a-1.
14
© K.T. Tim Cheng, 02_fault_model, v1.0 27
• Even thought T strongly detects b s-a-0, we cannot say at which time a fault effect (0/1 or 1/0) will appear.
• We must list all possible responses of the fault free circuit and compare the output response of the circuit under test with each of the normal responses to determine the detection of the fault. – Not practical!! – For n FFs, we need to store 2n possible output
responses.
Issues of Strong Detection
© K.T. Tim Cheng, 02_fault_model, v1.0 28
• Practically, we store just one normal response and determine the detection on a vector-by-vector basis.
• Test sequence T detects the fault f iff for every possible pair of initial states q and qf, the output sequences R(q, T) and Rf(qf, T) are different for some specified vector ti ∈T.
Practical Notion of Detection
15
© K.T. Tim Cheng, 02_fault_model, v1.0 29
• Testing experiment is divided into two phases:– Phase 1: Apply an initialization sequence TI
• At the end of TI, both fault-free & faulty circuits are brought to known states qI & qIf.
• Output responses are ignored during TI as they are unpredictable.– Phase 2: Apply a test sequence T’.
• Both R(qI, T’) & R(qIf., T’) are predictable. • ti is the first vector of T’ for which an error is observed.
• The applied sequence is TI-T’ and the stored expected response is don’t cares-R(qI, T’).
• In testing, we compare the output response of the CUT with the stored expected response. – When a mismatch occurs at a care vector, detection is reported.
Fault Detection for Sequential Ckts
© K.T. Tim Cheng, 02_fault_model, v1.0 30
Multiple Stuck-at Faults• A multiple stuck-at fault means that any set of lines
is stuck-at some combination of (0,1) values.• The total number of single and multiple stuck-at
faults in a circuit with k single fault sites is 3k-1.• A single fault test can fail to detect the target
fault if another fault is also present, however, such masking of one fault by another is rare.
• Statistically, single fault tests cover a very large number of multiple faults.
16
© K.T. Tim Cheng, 02_fault_model, v1.0 31
Transistor (Switch) Faults• MOS transistor is considered an ideal switch
and two types of faults are modeled:• Stuck-open - a single transistor is permanently
stuck in the open state.• Stuck-short - a single transistor is permanently
shorted irrespective of its gate voltage.
• Detection of a stuck-open fault requires two vectors.
• Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ).
© K.T. Tim Cheng, 02_fault_model, v1.0 32
Stuck-Open Example
Two-vector s-op testcan be constructed byordering two s-at testsA
B
VDD
C
pMOSFETs
nMOSFETs
Stuck-open
1
0
0
0
0 1(Z)
Good circuit states
Faulty circuit states
Vector 1: test for A s-a-0(Initialization vector)
Vector 2 (test for A s-a-1)
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000
17
© K.T. Tim Cheng, 02_fault_model, v1.0 33
Stuck-Short Example
A
B
VDD
C
pMOSFETs
nMOSFETs
Stuck-short
1
0
0 (X)
Good circuit state
Faulty circuit state
Test vector for A s-a-0
IDDQ path infaulty circuit
Ack: Bushnell and Agrawal, Essential of Electronic Testing, 2000
© K.T. Tim Cheng, 02_fault_model, v1.0 34
Bridging Faults
• Shorting of adjacent lines (layout dependent)– Usually assuming a low resistance path (hard short)
• Faulty value is identical on shorted lines• Faulty value is AND/OR function of shorted
signals• Covering a large % of physical defects• A large # of bridging faults map into SA faults
18
© K.T. Tim Cheng, 02_fault_model, v1.0 35
Delay Faults• Used to test whether device meets performance
specification• Related to propagation delay in combinational circuit
(from inputs/flip-flops to outputs/flip-flops)• Two types of faults
– Path-delay fault– Gate-delay fault
• Details will be introduced later in Delay Testing chapter
© K.T. Tim Cheng, 02_fault_model, v1.0 36
Path-Delay & Gate-Delay Faults
Path-delay-fault:• Propagation delay of path exceeds clock interval• # of paths grows exponentially with number of gates
Only consider long paths or a subset of paths• Tests can detect small distributed failures• Tests for the longest paths can also be used for
speed-sorting
Gate-delay-fault:• A logic model for a defect that delays a rising or a
falling transition• Small distributed timing failures could be missed• #of modeled faults is much smaller and manageable
19
© K.T. Tim Cheng, 02_fault_model, v1.0 37
Transition Faults & Small Gate-Delay Faults
Transition fault (Gross gate-delay fault):• The extra delay caused by the fault is assumed to be large
enough to prevent the transition from reaching any primary output at the time of observation
• Can be tested along any path from the fault site to any PO• The test is a vector pair that creates a transition at the fault
site and the second vector is a test for the stuck-at fault at the fault site
Small gate-delay fault:• Is tested along the longest propagation delay path
© K.T. Tim Cheng, 02_fault_model, v1.0 38
PLA Faults
• Stuck-at faults• Cross-point faults• Bridging faults
20
© K.T. Tim Cheng, 02_fault_model, v1.0 39
Stuck-at Faults In PLA• S-a-0 and s-a-1 on inputs, input inverters,
product lines, and outputs• Easy to simulate in gate model
A B C f1 f2
x
x
P1
P2 x
A
B
C
P2
P1
f2
f1
AND-Array OR-ArrayPLA
• Stuck fault sitesEquivalent logic model
© K.T. Tim Cheng, 02_fault_model, v1.0 40
Missing Cross-Point Faults In PLAA B C f1 f2
x
x
p1
p2 xAND - ARRAY
GROWTHOR - ARRAY
DISAPPEARANCE
00 01 11 10
01
CAB
11
11p2 p1 p1 [ ( C, p1 ) MISSING
• Missing cross-point in AND array– Growth fault– Equivalent to stuck fault
X
B
Cs - a - 1
p1 = B.C. . .p1 = B
• Missing cross-point in OR array- Disappearance fault- Equivalent to stuck fault
Xp1
p2
. . .
. . . f1 = p1 + p2
f1 = p2
21
© K.T. Tim Cheng, 02_fault_model, v1.0 41
Extra Cross - Point Faults In PLAA B C f1 f2
x
x
P1
P2 x
x
SHRINKAGEDISAPPEARANCE APPEARANCE
00 01 11 10
01
CAB
11
11p2 p2 : ( C, p2 ) ADDED
• Extra cross-point in AND array– Shrinkage or disappearance fault– Disappearance equivalent to stuck
fault
• Extra cross-point in OR array– Appearance fault
© K.T. Tim Cheng, 02_fault_model, v1.0 42
Summary of PLA Faults• Cross-point faults
– 80-85% covered by stuck-at fault tests– Layout-dependence in folded PLA
• Bridging faults– 99% covered by stuck-at fault tests– Layout-dependence in all PLAs
22
© K.T. Tim Cheng, 02_fault_model, v1.0 43
Summary: Fault Modeling• Current practice
– Single stuck-at faults– Simple gate delay faults (transition faults)– Limited usage of path delay faults– Various faults for memory
• Other important models– Stuck-open and stuck-short (CMOS)– Interconnect open faults and bridging faults
© K.T. Tim Cheng, 02_fault_model, v1.0 44
Isn’t 99.9% Good Enough?• The alternative to setting the standards at their highest possible
level becomes clear when we look at the consequences of “almost, but not quite” perfect.
If 99.9% is good enough then:• 2 million documents will be lost by IRS this year• 22K checks will be deducted from the wrong back accounts in the next
hour• 12 babies will be given to the wrong parents today• 268K defective tires will be shipped this year• 14K defective PCs will be shipped this year• 2.5 million books will be shipped in the next year with the wrong cover• 2 plane landings daily at LAX airport will be unsafe• 18K pieces of mail will be mishandled in the next hour• 880K credit cards in circulation will have incorrect cardholder information
on their magnetic strips• 315 entries in Websters’s Dictiorary will be misspelled• ...
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