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Introduction to 32 Bit Microcontrollers and its application
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1© 2009, VIT University, Inc. All rights reserved.
“Advanced 32 Bit Embedded system design”
Focus on ARM & Power PC
Necessity of 32-bit Microcontroller
- By V.Mohana
222© 2009, VIT University, Inc. All rights reserved.
Contents
• Mixed Microcontroller Soup
• High End Microcontroller applications
• Computer Architecture taxonomy
• Why 32 Bit Microcontroller?
• Popular 32- bit CPU cores
• Selecting a microcontroller
• Unique architecture features.
333© 2009, VIT University, Inc. All rights reserved.
Mixed Microcontroller Soup
444© 2009, VIT University, Inc. All rights reserved.
Embedded Microcontroller
• Microcontroller
• An application-specific processor
• PIC vs. StrongArm: it all depends on your application
• Typically, microcontrollers...
• Are low cost, lightweight processors
• Require few support components for better system integration
• Come with integrated peripherals
555© 2009, VIT University, Inc. All rights reserved.
Contents
• Mixed Microcontroller Soup
• High End Microcontroller applications
• Computer Architecture taxonomy
• Why 32 Bit Microcontroller?
• Popular 32- bit CPU cores
• Selecting a microcontroller
• Unique architecture features.
666© 2009, VIT University, Inc. All rights reserved.
High-end microcontroller applications
• Consumer Electronics
• Printer.
• Cell phone.
• Automobile: engine, brakes, dash, Safety etc.
• Television.
• Household appliances.
• Medical Electronics eg :-Telemetric
777© 2009, VIT University, Inc. All rights reserved.
High-end microcontroller applications
888© 2009, VIT University, Inc. All rights reserved.
BMW 850i
999© 2009, VIT University, Inc. All rights reserved.
BMW 850i, cont’d.
brake
sensor
brake
sensor
brake
sensor
brake
sensor
ABShydraulic
pump
101010© 2009, VIT University, Inc. All rights reserved.
HP Design Jet drafting plotter
i960KAadrslatch
busif
1 MBROM
2 MBDRAM
proc.supportASIC
||if
RS-422
penctrl
ASIC
swathRAM
servoproc.
(8052)
EEPROM
DRAMctrlfront panel stepper
motor
carriagePC board
111111© 2009, VIT University, Inc. All rights reserved.
Apple Newton
ARM 610 ROM RAM
RuntASIC
LCD
speaker
serial I/F
A/D
tablet
PCMCIA
infrared
121212© 2009, VIT University, Inc. All rights reserved.
Set-top box in system
set-top box
IR
digital TV input
backchannel
131313© 2009, VIT University, Inc. All rights reserved.
Philips fiber-to-curb box hardware
Networkinterface
MPEGdemux
MPEGaudio
MPEGvideo
NTSCCD-I
graphicsPCMCIA
DRAM
I/Okbd
IR
card
NVRAM
DRAM
DRAM
141414© 2009, VIT University, Inc. All rights reserved.
Fiber-to-curb box software
default apps custom apps
OS-9 kernel I/O manager
device driversboot
/mon
itor
sof
twar
e
MPEG2demux
audio/videointerfaces
CD-Igraphics
networkinterfaceprocessor
hardwarelayer
OSlayer
applicationlayer
151515© 2009, VIT University, Inc. All rights reserved.
Contents
• Mixed Microcontroller Soup
• High End Microcontroller applications
• Computer Architecture taxonomy
• Why 32 Bit Microcontroller?
• Popular 32- bit CPU cores
• Selecting a microcontroller
• Unique architecture features.
161616© 2009, VIT University, Inc. All rights reserved.
Von Neumann architecture
• Memory holds data, instructions.
• Central processing unit (CPU) fetches instructions from memory.
• Separate CPU and memory distinguishes programmable computer.
• CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc.
171717© 2009, VIT University, Inc. All rights reserved.
CPU + memory
memoryCPU
PC
address
data
IRADD r5,r1,r3200
200
ADD r5,r1,r3
181818© 2009, VIT University, Inc. All rights reserved.
Harvard architecture
CPU
PCdata memory
program memory
address
data
address
data
191919© 2009, VIT University, Inc. All rights reserved.
von Neumann vs. Harvard
• Harvard can’t use self-modifying code.
• Harvard allows two simultaneous memory fetches.
• Most DSPs use Harvard architecture for streaming data:
• greater memory bandwidth;
• more predictable bandwidth.
202020© 2009, VIT University, Inc. All rights reserved.
Load and Store architecture
• CISC Approach
• The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible
• This is achieved by building processor hardware that is capable of understanding and executing a series of operations.
212121© 2009, VIT University, Inc. All rights reserved.
Load and Store architecture
• RISC Approach
• RISC processors only use simple instructions that can be executed within one clock
• Separating the "LOAD" and "STORE" instructions actually reduces the amount of work that the computer must perform
222222© 2009, VIT University, Inc. All rights reserved.
RISC Vs CISC approach
• CISC Approach
• MULT 2:3, 5:2
• RISC Approach
• LOAD A, 2:3LOAD B, 5:2PROD A, BSTORE 2:3, A
232323© 2009, VIT University, Inc. All rights reserved.
RISC Vs CISC
CISC RISC
Emphasis on hardware Emphasis on software
Includes multi-clockcomplex instructions
Single-clock,reduced instruction only
Memory-to-memory:"LOAD" and "STORE"incorporated in instructions
Register to register:"LOAD" and "STORE"are independent instructions
Small code sizes,high cycles per second
Low cycles per second,large code sizes
242424© 2009, VIT University, Inc. All rights reserved.
The Performance Equation
1. The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction
2. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.
252525© 2009, VIT University, Inc. All rights reserved.
Pipelining
• Execute several instructions simultaneously but at different stages.
• Simple three-stage pipe:fe
tch
deco
de
exec
ute
mem
ory
262626© 2009, VIT University, Inc. All rights reserved.
Pipeline complications
• May not always be able to predict the next instruction:
• Conditional branch.
• Causes bubble in the pipeline:
fetch decodeExecute
JNZ
fetch decode execute
fetch decode execute
272727© 2009, VIT University, Inc. All rights reserved.
Contents
• Mixed Microcontroller Soup
• High End Microcontroller applications
• Computer Architecture taxonomy
• Why 32 Bit Microcontroller?
• Popular 32- bit CPU cores
• Selecting a microcontroller
• Unique architecture features.
282828© 2009, VIT University, Inc. All rights reserved.
Why 32 Bit Microcontroller?
• Performance
• OS support
• Sophisticated Peripherals support
• Real time applications
• Pipelined RISC architecture
292929© 2009, VIT University, Inc. All rights reserved.
Contents
• Mixed Microcontroller Soup
• High End Microcontroller applications
• Computer Architecture taxonomy
• Why 32 Bit Microcontroller?
• Popular 32- bit CPU cores
• Selecting a microcontroller
• Unique architecture features.
303030© 2009, VIT University, Inc. All rights reserved.
Popular 32- bit CPU cores
• ARM (Acorn RISC Machine)
• MIPS (Microprocessor without Interlocked Pipeline Stages )
• PowerPC (Power Performance Computing )
• SH (Super H)
313131© 2009, VIT University, Inc. All rights reserved.
Popular 32 bit microcontroller manufacturers
• Atmel
• Cypress Semiconductor
• Freescale semiconductor
• Infineon
• Intel
• NXP
• Texas Instruments.
• NEC
• Renesas
323232© 2009, VIT University, Inc. All rights reserved.
Contents
• Mixed Microcontroller Soup
• High End Microcontroller applications
• Computer Architecture taxonomy
• Why 32 Bit Microcontroller?
• Popular 32- bit CPU cores
• Selecting a microcontroller
• Unique architecture features.
333333© 2009, VIT University, Inc. All rights reserved.
Selecting a Microcontroller
• Choose the right one for your application
• Software support & development environment, FAE support, and hardware availability
• Choose one with good software development support
• Beware of availability
343434© 2009, VIT University, Inc. All rights reserved.
Contents
• Mixed Microcontroller Soup
• High End Microcontroller applications
• Computer Architecture taxonomy
• Why 32 Bit Microcontroller?
• Popular 32- bit CPU cores
• Selecting a microcontroller
• Unique architecture features.
353535© 2009, VIT University, Inc. All rights reserved.
Unique Architecture features.
• RISC Architecture
• Pipeline
• High speed bus architecture
• In Circuit Emulators (ICE)
• Various power saving mode
• Various clock domain
• Memory Management Unit (MMU)
363636© 2009, VIT University, Inc. All rights reserved.
ARM
• ARM Holdings, plc. is a fabless company which defines and licenses the ARM architecture
• joint venture of Apple, Acorn, and VLSI
• ARM is targeted at
• Portable market: digital cellular phones, pagers and personal organizers
• Embedded market: modems, hard disc drives, printers and Automotive applications
• Consumer multimedia market: sound systems, games, internet access TV, set top box
• ARM tries to provide high MIPS/watt, good code density, and minimal area => minimal cost
373737© 2009, VIT University, Inc. All rights reserved.
ARM
• 32-bit architecture, typ. Harvard - style
• Popular arch. variants include ARM7, ARM9, ARM10, Strong-Arm
• Most ARM implementations include 8-16K separate I/D caches
• Representative ARM: Strong-ARM
• Multiply and barrel shift instructions in hardware
• Processor core consumes roughly 100 mW at top speed
383838© 2009, VIT University, Inc. All rights reserved.
Intel Strong ARM architecture
393939© 2009, VIT University, Inc. All rights reserved.
Strong-ARM
Audiovox Thera PDA-2032
404040© 2009, VIT University, Inc. All rights reserved.
MIPS
• Origins
• Defined by John Hennessey c. 1980
•Turned into a company by John Hennessey, Skip Stritter, and John Moussouris
• Architecture spans several generations, most recent rev of ISA is MIPS IV
• MIPS is currently a fabless company who licenses technology, cores, and IP
•Toshiba, NEC, IDT, LSI Logic, NKK, Philips, and QED (QED is also fabless)
• Range of MIPS varieties
• 32 or 64-bit versions
• 16 MHz to 300 MHz
• 54 mW to 30W
•0.5u to 0.25u processes, 2mm2 to 290 mm2 implementations
414141© 2009, VIT University, Inc. All rights reserved.
MIPS
• Originally targeted for workstation/supercomputer CPU
• Migrated to embedded applications, now one of the most popular embedded architectures
• PowerPC is taking a similar track
• typical MIPS architecture: NEC VR4120
424242© 2009, VIT University, Inc. All rights reserved.
NEC VR4120
434343© 2009, VIT University, Inc. All rights reserved.
VR4120 Block diagram
444444© 2009, VIT University, Inc. All rights reserved.
Hitachi SH
• Hitachi SH is one of many products made by Hitachi
• “Super-H” RISC engine
• Scalable architecture, from SH-1 to SH-4
• Upward code compatible across entire family
• Applications from motion controllers to high-end game decks and windows CE computers
• Targeted at low-power, cost-sensitive applications but still requiring high performance
454545© 2009, VIT University, Inc. All rights reserved.
Hitachi SH
• SH-1 is 20 MHz, highly integrated peripheral set, MAC, cost sensitive apps
• SH-2 is 66 MHz, highly integrated peripheral set, DSP version available, cache
• SH-3 is 133 MHz, DSP version available, MMU, cache
• SH-4 is 200 MHz, integrated FPU, 3-D vector unit, MMU, plus other peripherals, cache
464646© 2009, VIT University, Inc. All rights reserved.
Super H
474747© 2009, VIT University, Inc. All rights reserved.
Power PC
• PowerPC is a RISC architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM
• Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors.
• PowerPC is based on IBM’s POWER Architecture
• The first RISC machine.
• Performance Optimization With Enhanced RISC
484848© 2009, VIT University, Inc. All rights reserved.
MPC5554 Overview
494949© 2009, VIT University, Inc. All rights reserved.
Special Features of ARM (Eg: ARM7TDMI)
• Reduced Instruction Set Computer (RISC)
• Simple instruction set and decode compared to CISC processors
• Allows for high instruction throughput and real-time interrupt response
• 3-stage pipeline
• Fetch, Decode and Execute
• All parts of the processing and memory systems can operate continuously
• Von Neumann architecture
• Single path for Instructions and Data
• Data Bypass buffer of MAM reduces bottlenecks
505050© 2009, VIT University, Inc. All rights reserved.
ARM state and Thumb state
• ARM uses a 32-bit architecture with a subset of 16-bit instructions, still using 32-bit data and registers.
• Set of instructions re-coded into 16 bits
• Improved code density by ~ 30%
• Saving program memory space
• In Thumb state only the program code is 16-bit wide
• After fetching the 16-bit instructions from memory, they are de-compressed to 32 bit instructions before they are decoded and executed
• All operations are still 32-bit operations
515151© 2009, VIT University, Inc. All rights reserved.
8-bit & 16-bit code size vs Thumb
• NXP LPC2000 (Thumb Mode)26796 bytes
• Renesas H8 37921 bytes
• Renesas M16C 26743 bytes
• TI MSP430 26424 bytes
• Atmel AVR 26055 bytes
• Freescale HCS12 23916 bytes
525252© 2009, VIT University, Inc. All rights reserved.
Special features of PowerPC (e200z6)
• PowerPC e200 is a family of 32-bit Power Architecture microprocessor cores developed by Freescale
• Targeted for Automotive and Industrial Control system
• Especially designed for engine management.
• Multipoint fuel injection control
• Direct diesel injection (DDI)
• Gasoline direct injection (GDI)
• Avionics
• Robotics
• Turbine control
• Utilities/Power management
• Alternative energies
• Autonomous vehicles
• Any model-based design using RAppID and Matlab/Simulink
535353© 2009, VIT University, Inc. All rights reserved.
Freescale’s e200z6 Core
• High-performance 132 MHz 32-bit Book E-compliant core built on Power Architecture technology
• SPE (signal processing extension): DSP, SIMD and floating point capabilities
• 40-channel dual enhanced queued analog-to-digital converter (eQADC—up to 12-bit resolution and up to 1.25 uS
• Three controller area network (CAN) modules with 64 buffers each
545454© 2009, VIT University, Inc. All rights reserved.
References
• Computers as Components- By Wayne Wolf
555555© 2009, VIT University, Inc. All rights reserved.
Questions
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