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PWM INVERTER CONTROL
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International Journal of Communications and Engineering
Volume 04– No.4, Issue: 02 March2012
Page 25
FPGA UTILISATION FOR HIGH LEVEL
POWER CONSUMPTION DRIVES BASED
ONTHREE PHASE SINUSOIDAL PWM -
VVVF CONTROLLER
S.Ruhbeena Thamkin Mr.A.Nazar Ali M.E.(Ph.D), Mr.J.Jegatheesan M.E
M.E-Power Electronics &Drives Associate Professor/HOD Assistant Professor/project guide
Department of Electrical & Electronics Engg Department of Electrical & Electronics Engg Department of Electrical & Electronics Engg Annai Mathammal Sheela Engineering College Annai Mathammal Sheela Engineering College Annai Mathammal Sheela Engineering College
mail2ruhbeena@gmail.com naza.annai@gmail.com jega007eee@gmail.com
ABSTRACT
This paper presents a single –Chip IC realization of 3-phase sinusoidal PWM (SPWM) variable voltage
variable frequency(VVVF)controller with constant U/F ratio.The SPWM control in a single FPGA has
been developed and implemented. With VHDL methodology the control IC implemented using only one
single advanced FPGA from SPARTAN XC3S400PQ208 from Xilinx Inc. The simulations are carried
out using ModelSim 5.7 and the implementation is carried out using Xilinx foundation series 9.1i. The
PWM patterns have been achieved for different switching and fundamental frequencies. The output
fundamental can be varied from 0.1 Hz to 1.5 kHz and the PWM switching can be set from 0.2 Hz to 100
MHz. The simulation and experimental results are presented.
Keywords: Sinusoidal PWM, FPGA, VVVF.
I. INTRODUCTION
In the industrial applications, many three-phase
loads require a supply of Variable Voltage
Variable Frequency (VVVF) including fast and
high-efficient electronic control.Predominant
applications are in variable speed AC drives and
power conditioning systems. The conversion of
DC power to three-phase AC power is
exclusively performed in the switched mode.
The temporary connections to the power
semiconductor switches at high repetition rates
between the two DC terminals and the three
phases of the AC drive motor is performed. The
actual power flow in each motor phase
iscontrolled by the on/off ratio, or duty-cycle, of
the respective switches. The desired sinusoidal
waveform of the currents is achieved by varying
the duty-cycles sinusoidally with
time,employing techniques of Pulse Width
Modulation (PWM).The PWM strategy plays an
important role in theminimization of harmonics
and switching losses in these converters,
especially in three-phase applications. In the past
two decades, various PWM strategies, control
schemes, and realization techniques have been
developed. Many PWM schemes have been
developed by many researchers to obtain the
desired performance or to overcome the existing
limitations such as DC bus utilization, linear
operating range, high harmonic contents in the
output, accuracy and speed in the digital PWM
control. In the field of digital control in
electrical systems, advanced microprocessors
and Programmable Logic Devices (PLDs) are
playing a critical role. Due to the higher gate
densities and lower cost, FPGAs can target a
large market of Application Specific Standard
Products (ASSPs). The algorithm is developed
using HDL and the detailed tutorial of Very
High Speed Integrated Circuit (VHSIC)
International Journal of Communications and Engineering
Volume 04– No.4, Issue: 02 March2012
Page 26
Hardware Description Language (VHDL) with
design examples are given in. This method is as
flexible as any software solution. Another
important advantage of VHDL is that it is
technology independent. The real time
implementation of a PWM control scheme
requires high performance digital controllers
such as Digital Signal Processor (DSP), FPGA
and combination of these. During 1980s, the low
performance microprocessors were
used. In late 1990s, the DSPs were used for PE
converter control. DSPs providing the
sequentially executable software solution and
FPGA provide the concurrently executable
hardware solution. Each device is having
specific merits and demerits such as speed,
input/output (I/O) capabilities, and memory
space/ chip resources to store the application
software and data size in signal processing.
Since, FPGAs are executing the control
statements concurrently, they offer the high
speed computation in real time. Therefore,
FPGA has been extensively used in many PEC
control like DC-DC converters, matrix
converters , resonant converters, converters with
power factor correction, AC-DC converters. In
three-phase DC-AC converter (Inverters) control
using SPWM SVPWM, are reported. The host
processors interfaced with FPGA to generate
PWM are presented. The single chip FPGA
based PWM controls using holistic modelling
approach, Xilinx System Generator (XSG) based
design, and modifying the PWM algorithm
suitable for FPGA implementation are
developed the various types electric drive
control are presented in . The feature of dynamic
reconfiguration can be programmed in a single
FPGA].The limitations in the existing FPGA
based PWM control implementations are the
need of a co-processor to compute the
algorithms, operational speed and more
utilization of FPGA resources. This paper
presents the design and implementation
of FPGA based efficient SPWM control through
single FPGA. The paper is organized as follows:
section II describes the principle of SPWM,
Section III presents the FPGA implementation
VLSI architecture for SPWM controller, and
Section IV deals with the implementation of the
SPWM controller.
II. PRINCIPLE OF SPWM
The most widely used method of PWM is carrier
based. Sinusoidal modulation is based on
triangular carrier signal and level comparison
between them produces the PWM gating signal.
The modulating and triangular reference signal
is
shown in Fig. 1 and the procedure to generate
the gating signals are shown in Fig. 2.
Amplitude modulation index is given by
where fcr is the frequency of carrier and fm is
the frequency of modulating wave.The time for
vertex sampling point and the nadir sampling is
t1 and t2 respectively. The sampling points, t1
and t2 are shown in Fig. 2 and they are
calculated using the following relations
Uc is the maximum value of the sine wave. Tt
International Journal of Communications and Engineering
Volume 04– No.4, Issue: 02 March2012
Page 27
represents the period of the triangular carrier,
and ω is the angular frequency of the sine wave.
III. FPGA IMPLEMENTATION VLSI
ARCHITECTURE FOR SPWM
CONTROLLER
The FPGA implementation of SPWM controller
through FPGA is shown in Fig 3.. The single
chip SPWM controller is developed using
VHDL. The designed VLSI Architecture for
SPWM controller is implemented in a
reprogrammable XC3S400PQ208 FPGA. The
internal modules of the architecture are Q –
Format Arithmetic Logic Unit (QALU), clock
divider, frequency selector, sin generator, PWM
controller and dead time module. The QALU
performs all arithmetic and logic functions in Q-
Format representation In the FPGA
implementation the QALU is constructed as
generic library function. Each module is
described with VHDL, compiled and simulated
in the environment of Xilinx.
A. Q –Format Arithmetic Logic Unit (QALU)
The QALU designed performs the data
representation,arithmetic and logic operations in
the SPWM algorithm using Q-Format. The
QALU in FPGA is implemented as generic
library function. The VHDL code for QALU
arithmetic operations like addition and
mltiplication has been developed.
This ALU can be used as core for designing
FPGA based dedicated processors for inverter
and motor control applications .
B. Clock Divider
In the FPGA development board, a common
clock of 10MHz is provided by the oscillator.
But, the operation speed or clock for each
module in the design is varying. Therefore, a
Clock divider is used to generate the clock for
sine wave generator, triangular wave generator
comparator and PWM modules. Foclk is the fo
control clock. To get different frequency ratios
the clock divider is needed to generate 50%
Fig. 3. The VLSI Architecture for SPWM
duty cycle of carrier from the base clock. Fc is
control clock.The output voltage control is
employed for controlling the fundamental.
C. Sine Generator
The three phase sin waves with the 120°
displacement from each other are the reference
waves. This reference waves are generated by
the sin generator module. The sine table is
designed as a look up table which contains the
sine values for 180° of the sin wave for each
phase. The frequency of the sin wave can be
varied.
D. PWM Generator
The PWM pulses are generated by comparing
the sinusoidal referece and triangular carrier
signal. The relation for the vertex sampling point
t1 and the nadir sampling point t2 are evaluated
using the relations (3). The frequency relation
between the reference and carrier should satisfy
the Nyquist theorm. Three comparators and a
counter is used to generate the PWM pulses.
One compare unit with two PWM outputs is
used for each leg in the inverter. The fo can be
varied by changing the Foclk and by adjusting
the clock divider
.
E. Dead time Insertion
The phase legs of the inverter have to be
protected from short circuit. Therefore, a
programmable delay-time controller is
introduced in the designed SPWM architecture.
International Journal of Communications and Engineering
Volume 04– No.4, Issue: 02 March2012
Page 28
The turn-off time of power devices is usually
longer than its turn-on time,and, therefore, an
appropriate delay time must be inserted between
these two gating signals. The length of this delay
time is usually about 1.5 to 2 times the
maximum turn-off time. The output signals ta, tb
, tc and td decides the switching pattern for
positive, negative legs respectively as shown in
Fig.4. The relationship of the gating signal is
given in (5)
IV. IMPLEMENTATION OF THE SPWM
CONTROLLER
In order to evaluate the performance of SPWM
controller, the VSI fed Resistance load is
considered for its implementation. SPWM
controller is simulated using Model Sim 5.7 and
synthesized in Xilinx 9.1i. Its effectiveness is
verified experimentally using Xilinx SPARTAN
XC3S400PQ208 FPGA. A. Simulation Results
The SPWM controller has been simulated using
Model Sim 5.7 and implemented using Xilinx
9.1i. The Q- Format implementation has been
validated with the simulation and
implementation of an arithmetic operation
(multiplication) and the corresponding
implementation report and results are presented
in [15]. The implementation report of the
designed SPWM modulator is shown in Table I.
The Mode lSim 5.7 has been used for simulation
of the SPWM modulator with different
switching frequency (fs) and fundamental
frequency (fo). The simulation results for
SPWM output waveforms for
different fo, fs and M are shown in Fig. 5 to Fig.
7. The PWM waveform with delay time is
shown in Fig.8. The simulation is carried out
with the frequencies from low to high frequency
up to 100 kHz
Fig. 5. Three Phase SPWM waveforms with fs
= 10 kHz, fo = 50 Hz, and M=0.65
V. CONCLUSION
The SPWM control in a single FPGA has been
developed and implemented. The SPWM IP core
International Journal of Communications and Engineering
Volume 04– No.4, Issue: 02 March2012
Page 29
is designed using VHDL and a single FPGA,
SPARTAN XC3S400PQ208 from Xilinx Inc.
The simulations are carried out using Model Sim
5.7 and the implementation is carried out using
Xilinx foundation series 9.1i. The functionality
of the SPWM IP core is verified for different
switching and fundamental frequencies. The
PWM patterns have been achieved for different
fs with fo of 50 Hz. The output fo can be varied
from 0.1 Hz to 1.5 kHz and the PWM switching
can be set from 0.2 Hz to 100 MHz.
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