Multi-Core LTSmin: Marrying Modularity and Scalability

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Multi-Core LTSmin: Marrying Modularity and Scalability. Alfons Laarman Joint work with : Michael Weber Jaco Van de Pol 11/4/201. Nfm 2011. LTSmin Design Multi -Core Backend Concurrent Tree Compression Incremental Algorithms Experiments Future Work. Overview. - PowerPoint PPT Presentation

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MULTI-CORE LTSMIN:MARRYING MODULARITY AND SCALABILITY

ALFONS LAARMAN

JOINT WORK WITH:

MICHAEL WEBER

JACO VAN DE POL

11/4/201

Nfm 2011

• LTSmin Design

• Multi-Core Backend

• Concurrent Tree Compression

• Incremental Algorithms

• Experiments

• Future Work

23/4/2010Shared Hashtables in Parallel Model Checking 2

OVERVIEW

23/4/2010 3

LTSMIN: THE MODULAR PARTLTSMIN

Multi-Core LTSmin: Marrying Modularity and Scalability

DVEPROMELA via NIPS

μCRL1LanguageFrontend:

… ETF

PINSLayer:

Caching Regrouping

Process algebraicState based

muCRL2

Internal(symbolic)

SymbolicSequentialDistributedAlgorithms(backend) Multi-core

POR

23/4/2010 4

THE SCALABLE MULTI-CORE PARTPREVIOUS WORK

Multi-Core LTSmin: Marrying Modularity and Scalability

Worker 1 Worker 2

Worker 3Worker 4

PINS

requ

est

Lock

less h

ash

table

Synchronous Random Polling

23/4/2010 5

MEMORY BECOMES THE PROBLEM (AGAIN)

Multi-Core LTSmin: Marrying Modularity and Scalability

•Store 10^9 state vectors of length up to 10^3 bytes

•With 16 cores the throughput can become 1GB/sec of new state vectors

•States are very similar

Solution:

•Tree compression without losing scalability

•Exploit locality with incremental algorithms

23/4/2010 6

CONCURRENT TREE COMPRESSIONINGREDIENTS

Multi-Core LTSmin: Marrying Modularity and Scalability

Alfons Laarman, Jaco van de Pol and

Michael Weber – Parallel Recursive

State Compression for Free

(submitted)

23/4/2010 7

INCREMENTAL TREE INSERTIONINGREDIENTS

Multi-Core LTSmin: Marrying Modularity and Scalability

•Incremental insertion exploits locality (log2(N) accesses)

23/4/2010 8

MEMORY USAGEEXPERIMENTS

Multi-Core LTSmin: Marrying Modularity and Scalability

23/4/2010 9

MEMORY USAGEEXPERIMENTS

Multi-Core LTSmin: Marrying Modularity and Scalability

23/4/2010 10

AGGREGATE PERFORMANCE

EXPERIMENTS

Multi-Core LTSmin: Marrying Modularity and Scalability

23/4/2010Shared Hashtables in Parallel Model Checking 11

SUMMARY

Scalable memory-efficient reachability (DFS/BFS)

On-the-fly model checking of safety properties

23/4/2010Shared Hashtables in Parallel Model Checking 12

FUTURE WORK

POR PINS layer (benchmarked, published)

Multi-Core NDFS

Case studies

Download LTSmin (open source):

http://fmt.cs.utwente.nl/tools/ltsmin/

23/4/2010 13

INCREMENTAL HASHING BASED ON ZOBRIST HASHING [1]AN INCREMENTAL ALGORITHM

Multi-Core LTSmin: Marrying Modularity and Scalability

[1] Albert Lindsey Zobrist, A New Hashing Method with Application for Game Playing

♘g1-f3

Hx Hy(Hx ⊕ Z ,g,1♘ ) ⊕ Z ,f,3 ♘ =

arguments:Memory none refs

table - - - - - +

tree + + + + +

23/4/2010Shared Hashtables in Parallel Model Checking 14

COMMAND LINE ARGUMENTS AND THEIR EFFECTLTSMIN

arguments:Runtime none refs

table + + + + -

tree + + - + + -

23/4/2010 15

INCREMENTAL HASHING (CONTINUED)INGREDIENTS

Multi-Core LTSmin: Marrying Modularity and Scalability

•Uses dependency matrix

•Z is now limited by L

23/4/2010 16

LTSMIN: THE MODULAR PARTLTSMIN

Multi-Core LTSmin: Marrying Modularity and Scalability

Traditionally in model checking we have states and a next-state function

A state is an array of slots: <s1,….,sN> ∈ S

The next-state() function provides the transition relation: S → S

In LTSmin, we expose static information of the specification.

Partitioned Next-State Interface (PINS): S →K S (K transition groups)

The Dependency Matrix D is a K × N matrix of Booleans relating slots

and groups:

DRi,j indicates whether slot j is read by the transitions of group i.

DWi,j indicates whether slot j is written to by the transitions of group i.

Di,j = DRi,j ∨ DW

i,j

23/4/2010 17

LTSMIN: THE MODULAR PARTLTSMIN

Multi-Core LTSmin: Marrying Modularity and Scalability

DVE

PROMELAμCRL1

ETF

muCRL2

Multi-core

Distributed

Sequential

Symbolic

PINS interface

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