Mixed signal systems and integrated circuits signal_061214.pdf · Mixed signal systems and...

2006.12.14 A. Matsuzawa, Titech 1

Mixed signal systems and integrated circuits

Akira Matsuzawa

Tokyo Institute of Technology

http://www.ssc.pe.titech.ac.jp

2006.12.14 A. Matsuzawa, Titech 2

Over sampling ADC and DAC 2

• Higher order system• Stability

– Stability compensation

• Saturation of integrator– Scaling

• Multi-stage Sigma-delta modulation• Circuit design

– kT/C noise– OP amp. gain– DAC and DEM

• Recent important developments

2006.12.14 A. Matsuzawa, Titech 3

111

−− z 111

−− z 1−z...

Quantizer

Q

( ) ( ) ( ) ( )

( ) )z(Ez)z(X)z(Y

QYzz.....Y

zzY

zzX

zY

k

kkk

1

1

1

11

1

1

1

1

1

11111

−

−

−

−−

−

−

−

−

−+=

∴

+−

−−−

−−

−−

=

111

−− z

3rd-- >10 steps 4 th ---- >30

In OutH

Higher order sigma-delta modulation

Cascade connection of the integrators

The feed back loop becomes unstabledue to large phase delay and system gain,when the order is larger than 2.

Increase the resolution of the quantizerfor stabilization

Higher order sigma-delta modulator falls into unstable state easily.

2006.12.14 A. Matsuzawa, Titech 4

System stability

Quantizer has a gain of k

System expression of quantizer

A gain of 1bit quantizer can be taken zero to infinity!

Small kLarge k

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System model for stability analysis

1

1

n

1i

n

ij

1inii

n

1ii

ni

STF

z1z)z(IallyConvention

)z(Iak1

a)z(Ik)z(H

−

−

= =

+−

=

−=

⋅+

⋅⋅=

∑∏

∏

Gain of quantizer

1bit quantizer

Considering gains of integrator and quantizer.

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Stability in z function

MNazazazbzbzbzb

zAzBzH N

NN

MM

MM ≥

++++++++

== −−

−− ,

........

)()()(

011

1

011

1

Real single pole： ( )npcp →

Complex pole ： ( ) ( )θσσ +Ω→Ω∠±→± ncjba n cos,

Plural poles ： ( ) ( )( ) ( ) ( ) ( )θσ +Ω++++→ ninncnpinncnpi nn cos.....,..... 11

Stable： [ ] Nipnnh i ....,,,,),( 2110 =<⇒∞→→

Meta stable： 1p:plural,1p:Singlen0,c]n[h <≤⇒∞<≤≤ 　

Unstable： ( ) 1p:plural,1pglesinn,]n[h ≥>⇒∞→∞→

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Stability and pole position

System is stable, if the poles locate on inside of the unit circle.

2006.12.14 A. Matsuzawa, Titech 8

Stability of 1st order sigma-delta modulator

1st order system is stable.

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Stability of 2nd order sigma-delta modulator

Split at K=1

UnstableStable

Stable when a1 is less than unity

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Stability of 3rd order sigma-delta modulator

Unstable when k is smaller than the certain value.

UnstableUnstable

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Actual 4th order Sigma-delta ADC

+X +

( )( ) ( ) ( ) ( ) 4

1311

2221

3131

441

41

11111

−−−−−−−−

−

+−+−+−+−

−

zazzazzazzazzNTF :

1

1

1 −

−

− zz

a2a1

+1

1

1 −

−

− zz

1

1

1 −

−

− zz

nQ Y+

a3 a4

1

1

1 −

−

− zz

Needs adjustment of coefficients for system stabilization.

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Feed forward type

( ) ( )

( ) ( )

( ) ( )N

kikk

ii

ikk

ii

k

N

k

ii

i

QAzXa

A

zaY

zazzA

QYzXazaY

1

0

1

1

1

1

11

10

11

11

11

1

−

−−

=

−−

=

−−

−

=−

−+

−=

−+−≡

+−⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

−=

∑

∑

∑

( )N

k

kkc

QazXaY

aAffz1

0

1

1

1−

−

−+≅∴

≅∴<<≅ )(

Feed forward technique is also used for system stabilization.

Quantizer

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SNR at stable condition

M

SNR is degraded when the system becomes stable.In particular, it is heavily degraded at low over sampling rate.

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Local resonator

)()(:

zFzHNTF

+11

Pole s of H(z) become zeroes of NTF

Quantizer

Local resonators are used to make NTF zeroes.

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Zero distribution

1=zDistribute the zeroes on the

Noi

se le

vel (

dB)

Frequency

Poles can’t be changed so much because of stability. Deep notches in pass band

Distribute the zeroes can reduce in-band noise.

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Effect of zero distribution

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MASH (Multi-stage noise shaping)

111

−− z+

1−z

Q1

+

+

11 −− z

111

−− z+

1−z

Q2

+

+

11 −− z

111

−− z+

1−z

Q3

X

-Q1

-Q2

1st

quantization noise

YY1

Y2

Y3

2nd

quantization noise

( )( )( ) 3

123

21

12

11

1

11

1

QZQYQZQY

QZXY

−

−

−

−+−=

−+−=

−+=

( ) ( )( ) 3

31

321

21

1

1

11

QZXY

YZYZYY−

−−

−+=∴

−+−+=

Feed forwarded multi-stage noise shaping architecture is free from instability,however requires good matching.

Realizing the stable 3rd order sigma delta modulation.

2006.12.14 A. Matsuzawa, Titech 18

Design issue: signal saturation at integrator

a1z-1

1

＋Node1 a1

z-1f1

＋1f1

f1

1f1

Node1

Scaling

Systematic Approach for Scaling Coefficients of DiscreteSystematic Approach for Scaling Coefficients of Discrete--Time and ContinuousTime and Continuous--Time SigmaTime Sigma--Delta ModulatorsDelta ModulatorsN. Beilleau, H. Aboushady, M. M. Lou¨erat Universit´e Paris VI, Laboratoire LIP6/ASIM

Signal saturation at integrator degrades SNR so much.

We should reduce the output signal swings of integrators by adjusting gain coefficients.

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MatLab simulation for Scaling

f = [MAXmax3 MAXmax4 MAXmax5 MAXmax6 MAXmax7] / Targethalfswinga5 = [ a5(1)/f(1) a5(2)*f(1)/f(2) a5(3)*f(2)/f(3) a5(4)*f(3)/f(4) a5(5)*f(4)/f(5) ]lfb5 = [ lfb5(1)*f(3)/f(1) lfb5(2)*f(5)/f(3) ]w = [ w(1)*f(1) w(2)*f(2) w(3)*f(3) w(4)*f(4) w(5)*f(5) ]

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Scaling effect

a5 = 0.8106 0.3861 0.2236 0.1280 0.0401lfb5 = 0.0177 0.8412w = 1.0 1.0 1.0 1.0 1.0

a5 = 0.2996 0.3219 0.2811 0.2417 0.1565lfb5 = 0.0169 0.1141w = 2.7054 3.2444 2.5804 1.3670 0.3500

After ScalingBefore Scaling

We can reduce signal swings by scaling

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1bit

Scaling effect

After ScalingBefore Scaling

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5bit

Scaling effect

After ScalingBefore Scaling

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Scaling effect

After ScalingBefore Scaling

SNR is heavily damaged!

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SCF integrator

Comparator

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kT/C Noise effects

1st integrator

5order 1bit 3order 3bit

2nd integrator

3rd integrator

4th and 5th integrator

1st integrator

2nd integrator

3rd integrator

2006.12.14 A. Matsuzawa, Titech 26

kT/C Noise effects

Int. １ Int. 2 Int. 3 Int. 4

DAC

In Out

Pn1 Pn2 Pn3 Pn4

724

6

4N523

4

3N322

2

2N1Ntot_N MA7P

MA5P

MA3P

M1PP πππ

+++=

egratorintth'iuntilGain:Ai

Impacts of kT/C noises on each stage reduces along with increase of integrator number.

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op-amp gain

― 5-order 1-bit― 3-order 3-bit― 2-2 MASH 1-bit

40dB for single loop，60dB for MASH are needed.

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Mismatch effect of DAC

Higher SNR needs smaller mismatch for DAC, even though sigma-delta method is used.

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Dynamic Element Matching (DEM)

ThermometerType

decoderShuffler

Unit Element

Unit Element

Unit Element

+

DigitalInput

2B unity elements

2B

B

AnalogOutput

•Randomization•Clocked Averaging (CLA)•Individual Level Averaging (ILA)•Data Weighted Averaging (DWA)

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Data Weighted Averaging

＋VDACー

＋VDACー

＋VDACー

０１０、１００、０１１

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DEM Comparison

Y.Geerts and M. Steyaert, “Guidelines for implementation of CMOS multibitoversampling modulators”, ESPRIT project: SYSCONV Work Package 2,http://www.imse.cnm.es/esd-msd/deliverables.html

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Continuous time ΣΔADC

L. Breems and J.H. Huijsing,”Continuous-time sigma-delta modulation for A/D conversion in radio Receivers”Kluwer

We can make sigma delta ADC with CT filter.

2006.12.14 A. Matsuzawa, Titech 33

Effect of clock jitter

DAC Pulse

Ts

TΔσ

2281

Tbwit Mf

SNRΔ

≈σlim_

SNR=85dB, M=32, fbw=1.25MHz, 2.8psfbw=12.5MHz, 0.028ps

SNR of CT ΣΔADC is very sensitive to the clock jitter.In contrast, DT type is not so.

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High dynamic range design

P. Balmelli, et al., ISSCC 2004

Sigma delta method with multi-bit quantizer and dynamic element matching technique realized 25MS/s, 80dB ADC.

2006.12.14 A. Matsuzawa, Titech 35

Add new functionSigma-delta ADC can change the performance by changing over sampling ratio and filter characteristics. High DR and narrow BW

Low DR and wide BW Compatible:

T. Burger and Q. Huang, ISSCC 2001

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Add new function

K. Philips, ISSCC 2003

Complex band-pass sigma-delta

gm-C filter5th order complex sigma-delta 1b, @64MHz

Delta-sigma ADC can use complex band-pass filter.Analog filter and VGA can be removed from IF stage.

2006.12.14 A. Matsuzawa, Titech 37

LV and LP design

Low voltage OTA

Conventional SC integrator

2nd order, 16x over sampling ADC

Simple low voltage OTA enabled itT. Ueno, et al., ISSCC 2004

0.8V 1.5mW CT sigma-delta modulator attained 50dB at 2MHz in.

2006.12.14 A. Matsuzawa, Titech 38

References

• J.C. Candy and G.C. Tems, “Oversampling Delta-Sigma Converters,” IEEE Press, 1992.

• S. R. Norsworthy, R. Schreier, and G. C. Tems, “Delta-Sigma data Converters: Theory, Design, and Simulation,” IEEE Press.

• R. Schreier, and G. C. Tems, “Understanding Delta-Sigma Data Converters,” IEEE Press.

• Y. Geerts, M. Steyaert, and W. sansen,” Design of Multi-Bit Delta-Sigma A/D Converters,” Kuluwer.

• Rudy van de Plassche, “ CMOS Integrated Analog to Digital and Digital to Analog Converters,” Kluwer.

• F. Medeiro, A. Perez-Verdu and A. Rodriguez-Vazquez, “Top-Down Design of High-Performance Sigma-Delta Modulators,”, Kluwer.

• C. Toumanzou, G. Moschytz, and B. Bilbert, “Trade-offs in Analog Circuit Design,”Kluwer.

• 岩田 「CMOSアナログ回路設計技術」 トリケップス