Memristors - fp7-nanotec.eu€¦ · Memristors directly implement the synaptic plasticity • v =...

J. GrollierUnité Mixte de Physique CNRS/Thales

Palaiseau, France

Memristors

Nanobrain

L. O. Chua, “memristor – the missing circuit element” IEEE Trans. Circuit Theory (1971)

v = M(q) i

pinched IV loops

M=aq+b

v

0

ROFF

RON

i

Memristor

M is a resistance that “remembers” how much current was injected, and how longcontinuously tunable between RON and ROFF

1

L. O. Chua, “memristor – the missing circuit element” IEEE Trans. Circuit Theory (1971)

Memristor

v = M(q) i

pinched IV loops

M=aq+b

v

0

ROFF

RON

the HP memristor

0 x L

V-V+Pt PtTiO2TiO2-x

ions electromigration

Yang et al., Nature Nano (2008)

i

Memristor

M is a resistance that “remembers” how much current was injected, and how longcontinuously tunable between RON and ROFF

1

Pt PtTiO2

ROFF

Pt PtTiO2-x

RON

qx ∝ ⎥⎦⎤

⎢⎣⎡ −≅ q

LRRqM ON

OFF 21)( μ

Pt PtTiO2-x TiO2

0 x (t) L

⎟⎠⎞

⎜⎝⎛ −+=

LxR

LxRR OFFON 1

V

displacement proportional to the charge

Strukov, Snider, Stewart & Williams, Nature 453 (2008)

Hewlett‐Packard Memristor

migration of oxygen vacancies < 30x30 nm2

1000>ON

OFF

RR

2

‐ non‐volatile digital memories(ROFF/RON>1000)

‐ logic functions (no transistors)Kuekes et al., JAP 2005Borghetti et al., Nature 2010

‐ Reconfigurable Architectures(Field Programmable Gate Arrays)Snider et al., Nanotechnology 2007 Field Programmable Nanowire Interconnect

Memristor applications

3

wij

synapseneuron

inpu

ts

outp

uts

xjxi

• wij : synaptic weights - network memory- efficiency to transmit information- adjustable = plasticity = learning

• hugeinterconnectivity

Bio-inspired computing architectures

biological synapse : synaptic plasticity

change in strength in response to either use or disuse of transmission

key to the development of hardware Artificial Neural Networks

Memristors directly implement the synaptic plasticity• v = M(q) i • sub-µm size

Memristors : artificial synapses

4

speed, low energy consumption, defect tolerance

8.104 neurons5.1010 synapses

1 GHz40 kW

digital

super-computers slower than mouse (×10)

1011 neurons1015 synapses

parallel architecture• Human brain

10 Hz20 W

• Advantages of parallel, analog architecture

• Simulations of mouse cortex on Blue Gene L

analog

Von-Neumann architecture

Von Neumann vs. Neuromorphic computing

5

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Machine learning

Hardware ANNs

Applications

Constraints

Nanotechnology

Convergence of trends

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Machine learning

Hardware ANNs

Applications

Constraints

Nanotechnology

Convergence of trends

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Machine learning

Hardware ANNs

Applications

Constraints

Nanotechnology

Convergence of trends

• power limita‐‐tions : Multi‐cores• defects• heterogenerous multi‐cores

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Machine learning

Hardware ANNs

Applications

Constraints

Nanotechnology

Convergence of trends

• power limita‐‐tions : Multi‐cores• defects• heterogenerous multi‐cores

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Machine learning

Hardware ANNs

Applications

Constraints

Nanotechnology

Convergence of trends

• power limita‐‐tions : Multi‐cores• defects• heterogenerous multi‐cores

Intel 2005 :• Recognition• Mining  • Synthesis

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Applications

Constraints

Machine learning

Hardware ANNs

Nanotechnology

Convergence of trends

• power limita‐‐tions : Multi‐cores• defects• heterogenerous multi‐cores

Intel 2005 :• Recognition• Mining  • Synthesis

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Applications

Constraints

Machine learning

Hardware ANNs

Nanotechnology

Convergence of trends

• power limita‐‐tions : Multi‐cores• defects• heterogenerous multi‐cores

Intel 2005 :• Recognition• Mining  • Synthesis

• brain reverse enginering• visual cortexex : T. Poggio 

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Machine learning

Applications

Constraints

Hardware ANNs

Nanotechnology

Convergence of trends

• power limita‐‐tions : Multi‐cores• defects• heterogenerous multi‐cores

Intel 2005 :• Recognition• Mining  • Synthesis

• brain reverse enginering• visual cortexex : T. Poggio 

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Machine learning

Applications

Constraints

Hardware ANNs

Nanotechnology

Convergence of trends

• power limita‐‐tions : Multi‐cores• defects• heterogenerous multi‐cores

Intel 2005 :• Recognition• Mining  • Synthesis

• brain reverse enginering• visual cortexex : T. Poggio 

• deep networks• powerfull classifiers 

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Machine learning

Applications

Constraints

Nanotechnology

Hardware ANNs

Convergence of trends

• power limita‐‐tions : Multi‐cores• defects• heterogenerous multi‐cores

Intel 2005 :• Recognition• Mining  • Synthesis

• brain reverse enginering• visual cortexex : T. Poggio 

• deep networks• powerfull classifiers 

6

O. Temam, The rebirth of Neural Networks, Proc. ISCA’2010

Neurobiology

Machine learning

Applications

Constraints

Nanotechnology

Hardware ANNs

Convergence of trends

• power limita‐‐tions : Multi‐cores• defects• heterogenerous multi‐cores

Intel 2005 :• Recognition• Mining  • Synthesis

• brain reverse enginering• visual cortexex : T. Poggio 

• deep networks• powerfull classifiers 

• 1 memristor = 1 synapse

• 3D stacking• 104 synapses/neuron

6

• Hardware ANNs accelerators(heterogenous multi-core, embedded applications)

Memristors synapses : applications

• Large scale hardware simulations of the human brain ?

7

Memristors : artificial synapses

• Memristors directly store the synaptic weights (w = conductance)

Non-volative multi-valued resistances No need for space consuming SRAM banks

FACETS chip

Schemmel et al., IJCNN 20068

Memristors : artificial synapses

• Memristors are small (< 50 x 50 nm2)

interconnection issue : about 104 synapses per neuron in the brain

ex : CMOS “neurons” + memristive “synapses”

Xia et al., Nanoletters (2010)

HP

memristor crossbar arrays

to be solved : cross-talk, sneak paths, lithography

No demonstration yet of operational mixed memristor/CMOS cognitive chip

9

• Memristors directly implement the synaptic plasticity

• v = M(q) i

Memristors : artificial synapses

change in strength in response to either use or disuse of transmission

No need for space consuming complicated CMOS circuits

FACETS chip

Schemmel et al., IJCNN 2006 10

Hebbian learning

« Neurons that fire together wire together » Hebb, 1949

• Learning rule :

• Spike timing dependent plasticity :

presynapticneuron

postsynaptic neuronsynapse

- causality is important:transmission enhanced if post-neuron fires after pre-neuron- timing is important :−ΔT small, large transmission changes

11

Spike timing dependent plasticity

enables learning

• change of conductance vs. applied voltage :

V

low vnegligiblechange

high vrapid changedt

dw

Vthreshold

presynapticneuron

postsynaptic neuron

Vpre

wconductance

Vpost

V = Vpost-Vpre

general shape for memristors

Snider et al., Nanotechnology 2007 12

Spike timing dependent plasticity

v

dtdw

vth

Memristor change of conductance (synapse weight)

Linarres-Barranco et al., frontiers in Neuroscience, 2011

conductance increase conductance decrease

potentiation depression

Vpre

Vpost

V = Vpost-Vpre

Vpre

Vpost

V = Vpost-Vpre

13

STDP curve vs action potential shape

Linarres-Barranco et al., frontiers in Neuroscience, 2011

possibility to implement different kinds of STDP with a single device

14

STDP allows unsupervised learning (image recognition etc.)

STDP : experimental implementation

Jo et al., Nanoletters 2010

presynapticneuron

postsynaptic neuron

V = Vpost-Vpre

15

STDP : experimental implementation

Bi & Poo 1998

16

Jo et al., Nanoletters 2010

Memristor STDP curve

Which memristor ?

Classification : • Organic memristors

Erokhin et al., Surface and thin films (2007) PANIA.A. Zakhidov et al., Organic elec. (2009) metal/mixed conductor/metalF. Alibart et al., Advanced Func. Mater. (2009) Pentacene + gold particlesBen Jamaa et al., IEEE Nano (2009) Poly-cristalline Si nanowiresDerycke et al., TNT (2009) Carbone nanotubesDriscol et al., APL (2009) Phase change materialGergel et al., IEEE EL (2009) flexible TiO2Jo et al., Nanoletters (2009) Ag/SiWang et al., IEEE EL (2009) spintronicsKim et al., Nanoletters (2009) nanoparticle assembliesJeong et al., Nanoletters (2010) grapheneLee et al., Nature Materials (2011) Ta2O5Ohno et al., Nature Materials (2011) atomic switchesChanthbouala, Grollier et al., Nature Physics (2011) spintronics….

17

After (and even before) Hewlett‐Packard TiO2 memristor was proposed, many other very different memristor concepts were identified :

• Most Resistive Switching memristors

Organic memristors

• Organic memristors : NOMFET (polymer), CNT-FET, PANI….

- additional functionalities ex : interaction with light

-bottom up approachex : self-organization

• Very promising• time scale > 10 years

Erokhin et al., NanoNet 2009

FP7 Bion & Nabab projects

- high density

18

Resistive switching memristors

“easy” implementation in crossbar arrays – top down approach

Waser et al., Nature Materials 2007

‐ large local heating ‐ physics not understood‐ need of a forming step

• defect‐mediated : thermal effects, ionic motion

Ex : HP memristor based on electromigration : reliability / endurance issues

• the most mature existing technology

- Strukov et al., Nature 2008 (TiO2)- Jo et al., Nanoletters 2010 (Ag/Si, no forming step) 19

Resistive switching memristors

good cyclability > 1012, fast (10ns) and reduced power consumption

Lee et al., Nature Materials 2011 (Ta2O5-x/Ta2-x)

20

Resistive switching memristors

Short AND long term potentiation ! STDP ? Cyclability ?

Ohno et al., Nature Materials 2011 (Ag2S atomic switch)

21

Resistive switching memristors

Phase change : unipolar switching. STDP = yes, complicated ?

Kuzum et al., Nature Materials 2011 (Phase change)see also : Wright et al., Advanced Materials 2011

22

Resistive switching memristors

Waser et al., Nature Materials 2007

• defect‐mediated : thermal effects, ionic motion

• our work : purely electronic resistive switching

1 example :  “spintronic” memristor WO 2010/ 142762 A1

23

A. Chanthbouala, J. Grollier, R. Matsumoto, V. Cros, A. Anane, A. V. Khvalkovskiy, A. Fert

Unité Mixte de Physique CNRS/Thales, France

K.A. ZvezdinA.M. Prokhorov General Physics Institute of RAS, Russia

Istituto P.M. s.r.l., Italy

K. Nishimura, Y. Nagamine, H. Maehara, K. TsunekawaProcess Development Center, Canon ANELVA Corporation, Japan

A. Fukushima, and S. YuasaNational Institute of Advanced Industrial Science and Technology (AIST), Japan

Spintronic memristor 

24

Tunnel MagnetoResistance (TMR)Anti‐parallel state (AP)

MRAM building block = Magnetic Tunnel Junction Magnetic metal/Insulator/Magnetic metal

Magnetic Random Access Memory (MRAM)

RAP

NS N

S

Parallel state (P)

RP

NSNS

RAP

RP

-1000 -800 -600 -400 -200 0 200 400 600 800 1000

160.0

180.0

200.0

220.0

240.0

260.0

280.0

resi

stan

ce (Ω

)

magnetic field (G)

25

Tunnel MagnetoResistance (TMR)Anti‐parallel state (AP)

MRAM building block = Magnetic Tunnel Junction Magnetic metal/Insulator/Magnetic metal

RAP

NS N

S

Parallel state (P)

RP

NSNS

RAP

RP

-1000 -800 -600 -400 -200 0 200 400 600 800 1000

160.0

180.0

200.0

220.0

240.0

260.0

280.0

resi

stan

ce (Ω

)

magnetic field (G)

• Resistance: proportion of parallel and anti‐parallel domains

Domain RPDomain RAP

Domain Wall

Magnetic Random Access Memory (MRAM)

25

MRAM building block = Magnetic Tunnel Junction Magnetic metal/Insulator/Magnetic metal

• Resistance variation: Spin Transfer Torque (STT)

e‐

Tunnel MagnetoResistance (TMR)Anti‐parallel state (AP)

RAP

NS N

S

Parallel state (P)

RP

NSNS

RAP

RP

-1000 -800 -600 -400 -200 0 200 400 600 800 1000

160.0

180.0

200.0

220.0

240.0

260.0

280.0

resi

stan

ce (Ω

)

magnetic field (G)

Magnetic Random Access Memory (MRAM)

25

MRAM building block = Magnetic Tunnel Junction Magnetic metal/Insulator/Magnetic metal

e‐

Tunnel MagnetoResistance (TMR)Anti‐parallel state (AP)

RAP

NS N

S

Parallel state (P)

RP

NSNS

RAP

RP

-1000 -800 -600 -400 -200 0 200 400 600 800 1000

160.0

180.0

200.0

220.0

240.0

260.0

280.0

resi

stan

ce (Ω

)

magnetic field (G)

• Resistance variation: Spin Transfer Torque (STT)

Magnetic Random Access Memory (MRAM)

25

-10 -5 0 5 10

15

16

17

-4 -2 0 2 4

resi

stan

ce (Ω

)

dc current (mA)

current density (106 A/cm2)

Bidirectionnal DW motionCurrent densities lower than previous DW motion experiments

A. Chanthbouala et al., Nature Phys., 2011

01

2

DW displacement by vertical DC current

0 Side view

1 Side view

2 Side view

26

Δt2

j

Concept of the spintronic memristor

R

e‐e‐

Δt1j

Synaptic weight

t

x0’

Positive current pulse: Depression

R

t

x0’ x1’

Negative current pulse: Potentiation

R

tx1’x2’

e‐

qtJx ∝Δ∝Δ• Resistance: DW position• DW position: charge injected

Wang et al., IEEE, 2009 27

Conclusion on the spintronic memristor

‐ Understanding of the underlying mechanisms: key to further improvements and tuning of the synapse transfer function

‐ Fast: sub‐ns write process

‐ Purely electronic effect: high reliability and endurance

Advantages

‐ ON/OFF (RAP/RP) ratio now max = 6  Theoretical limit 100

‐ Connectivity: perpendicularly magnetized materials

Scalable below 50x100 nm

Perspectives

International Technology Roadmap for Semiconductors identified Spin Transfer Torque‐RAM as one of the two most promising emerging memory devices: Spintronic memristor will benefit from these developments

28

Benchmarking memristors ?

29

Technology memristors

GainSignal/Noise ratioNon-linearity

SpeedPower consumption

Architecture/Integrability(Inputs/outputs, digital, multilevel, analog, size etc.)

Other specific properties

Manufacturability(Fabrication processes needed, tolerances etc.)

Timeline(When exploitable or whenforeseen in production)

Benchmarking memristors ?

Technology memristors

GainSignal/Noise ratioNon-linearity

SpeedPower consumption

Architecture/Integrability(Inputs/outputs, digital, multilevel, analog, size etc.)

Other specific properties

Manufacturability(Fabrication processes needed, tolerances etc.)

Timeline(When exploitable or whenforeseen in production)

depends on the application

29

Memristors  as 2 states digital memories

• ITRS table 2010

30

Memristors  as artificial synapses

organic memristors ?

Endurance / cyclability / low power consumption / OFF-ON ratio / small : yes

speed, retention time : ?

Criteria issue

31

• US : 2009 DARPA “SyNAPSE” program

- Hewlett-Packard (memristors) - HRL labs (memristors) - IBM (?)

define a new path forward for creating useful, intelligent machines

Memristors around the world

3 funded projects (~ 5 M$ each for the first phase)

Systems of Neuromorphic Adaptive Plastic Scalable Electronics

• Europe : FP7 Nabab, FP7 Bion (ended)ERC NanoBrain & ERC Femmes projects, Chist-Era PNEUMA

32

Conclusion & perspectives

• State of the art memristor : exciting potential of memristor devices as artificial synapse

• spintronic memristor : resistance switching based on purely electronic effects 

very promising : endurance, speed, power consumption

• Young topic : no demonstration yet of a cognitive chip based on memristors

• Dedicated architectures and programmation schemes to be developed

•Which type of memristor for which application ?

Acknowledgements

Funding :

‐ ERC Starting Grant 259068 Nanobrain

‐ ANR P2N MHANN « Memristive Hardware Artificial neural Networks Accelerators »

‐ PEPS project ACME « Memristive Accelerators »

R. Waser, ISIF 2011