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Si2 - Innovation Through Collaboration
Steven E. SchulzPresident and CEO
May 20th, 2008
DVclub – Austin, TX
Low-Power Design and Verification
2Si2 – Innovation Through Collaboration
Today’s Agenda
3Si2 – Innovation Through Collaboration
Today’s Agenda
• Why Low-Power Now?
• Design and Verification
Flow Challenges / Reqts
• Common Power Format
Introduction / Examples
• Industry / Market Adoption
and Silicon Benefits
• Introduction to the Low
Power Coalition
• 2008 Roadmap / Plans
• Q & A
Page 3
Here W
e are
2001 International Technology Roadmap for Semiconductors
P = ACV2f + VIleak
JunctionLeakage
Possible kink in dynamic power Dynamic power
Sub-thresholdGate
Junction
Page 2
Power Motivation and Requirements
Mobile applications trends:
• Leakage is significantly increasing due to process scaling
• Active power increases due to application integration (with the subsequent exponential increase in leakage). Current density is also on the increase.
• Active leakage is now a significant portion of SoC active power budget.
• Sleep mode techniques need to be enhanced and enabled in a consistent fashion throughout the design flow
• We need a concerted effort applied to leakage minimization at the micro-architectural, system and software level.
• Process variation now limits how much we can voltage scale and how we do our power accounting, and therefore new strategies need to be develop to capture these constraints, and enhance our current scaling approaches/methodologies.
© 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 18
Ultra-Low-Power ApplicationsAddressing a Wide Range of RequirementsUltra-Low-Power ApplicationsAddressing a Wide Range of Requirements
Excel Your Idea to Silicon 10
PowerSmart™ -- Low Power Design Methodology
Power switch1.5V OP buffer
1.5V OP
D Q
ck
Vdd_UPSVdd
Retentionflip-flop
Isolation cell
Power Islands
Multi-Vtlibrary
Multi-Vth (Fusion)
clk
eno
Integratedclock gated cell
Clock Gating
Level shifterLevel shifter
Multi-outputregulator
Regulator1.2V
1.0V
0.8V
3.3V
Multi-VDDMulti-VDDlibrary
1.2V1.0V
0.8V Low powerIP
SRAM
Low Power IP
October 5, 20063
Processor design for Power Efficiency: Different needs for different markets• Server market:
– Defining property: Server processors are rarely idle. – Power goal: Increase MIPS/Watt in Power State C0 (ACPI).
• Mobile market:– Defining property: Laptop processors are mostly idle.– Power goal: Reduce power in C2/C3 power states.
• Techniques:– Clock gating– Multiple power domains– Multiple threshold voltages– Headers/footers – Operand Isolation (holding cell inputs stable when output is unused)– Dynamic voltage and frequency scaling– And others…
October 5, 20064
Power analysis challenges:More complex than timing analysis
• It is pattern-dependent.– Circuit and gate-level power analysis require good RTL-level patterns for accurate
results.
• It is a balancing act. (power efficiency) – Performance per watt (efficiency) is the metric, not Watts. Need to find blocks or
nets that consume power without appropriate performance benefit.– Many tools sort blocks and nets by total power consumption not
performance/watt. (E.g. clock nets burn a lot of power, but we already knew that)
• It is an aggregate (time and space) and a user-defined constraint.
– Power analysis types: average power (for budgeting & package selection), energy (for battery life), peak power (IR drop analysis), etc.
– E.g. Briefly higher localized power consumption can be tolerated for package selection, unless it exceeds limits.
• It requires coordination of data from physical design, gate design, RTL, and verification domains.
– It requires knowledge in all these domains to cross-check results.
• Must allow for accuracy to be improved over time. – Detailed circuit-level power analysis data often comes too late in the design cycle.
October 5, 200611
Other related issues: DFT and Timing
• Are scan paths hooked up in the RTL? Are they simulated in the Verilog? How are they verified?
• How do you analyze power consumption in scan mode?
• Timing also needs to know about the multiple voltage domains and operating points.
• Need to work on timing and power in one environment to achieve correct optimization and trade-offs.
Slide 8
System Aspects require differing viewsLayoutAlgorithmBus ArchitectureImplementationPowerSourceTemperatureRefinementSecurityAddress SpaceDocumentation
Slide 9
Address spaceLayoutAlgorithmBus ArchitectureImplementationPowerSourceTemperatureRefinementSecurityAddress SpaceDocumentation
Slide 10
Aspect View: Bus Architectural layout
CPUCPUCPUFLASHFLASH
USBUSB UARTUART GPIOGPIO
PLLPLL
Peripheral Bus
Processor Bus
BridgeBridge SRAMSRAM
EthernetEthernet……
DMADMA
DMADMA
LayoutAlgorithmBus ArchitectureImplementationPowerSourceTemperatureRefinementSecurityAddress SpaceDocumentation
Slide 17
Hierarchical view of Energy Conservation
Software Definitions
Dynamic system monitoring and intelligent control of energy savings, work load profiling, [dvfs], profiling and partitioning
Architectural Definitions
Heterogeneous processing resource optimization: MCU, DSP, accelerators, functional processing units, memory usage optimization
Design Definitions
Hardware support for voltage islands, power gating, low-power idle modes, SRPG, AWB, DVFS, DPTC, clock gating
PROCESS node Definitions
Transistor design, Vt Optimization, memory bitcell design. Special circuits, libraries, custom and analog blocks, SOI
Power Trees/Voltage islands, Connectivity of components & consistent platform power modes, intelligent bus coding, dependency discovery/optimization
Platform Definitions
Thanks to Milind Padhye, Freescale Semiconductor, Austin Wireless Design Center
Slide 18
Low Power Design NeedsSupport Low Power Design Techniques thru the entire design flow using a single file format.
Design Representation– Accurately define and capture the low power design intent, modes and
constraints.
Design Implementation– Floorplan and power grids.– Common constraints for all tools (Synthesis, APR, timing, DFT)– Design analysis tools with single power constraints.– Accurate power estimation and measurements
Design Verification– Voltage oriented simulators– Various static power technique modeling and simulations.– Silicon validation and correlation.
Page 5
The verification flows need to enable:
• a voltage aware simulation method for logic problems due to voltage island partitioning
• a method for full design multi-voltage domain analysis and reporting
• a vector-less rule driven analysis of architecture, RTL, and gate correctness
• a method for equivalence checking (i.e. across voltage states )• a method that captures Island ordering• a method that incorporates early detection of micro-architecture
sequence errors
Flow and Methodology Requirements
Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
3
Low power implementation : What’s new ?Becoming mainstream:
– For 65nm and below , Low power is crucial for low/high performance.
So far:– For dynamic power
• Reducing power dissipation source when not needed. • Minimize switching capacitances.
– For static power • Use of multiple Vt(s) synthesis / optimization
More recently: – Reducing supply reduces power, but also makes circuit slower. To meet both
chip performance requirements and power goals, use voltage islands and voltage and frequency scaling.
– Leakage can also be addressed by suppressing current when not needed.
Island of voltages increases the difficulty on implementation techniques.Intrusive on functionalityImpact across design tasks ( Design-In and Implementation )
Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
4
Design implementation challenges New cells and their use model
– Level Shifters – Retention logic– Isolation logic– Micro Switches
Impacts at all levels of the design flow– Interface logic design, partitioning– Verification of power modes– Checks on interfaces between Power domains– Placement of IP in context voltage islands– Floorplanning with switches, Irdrop across switches, transient
behavior.– DFT– Verification (STA, LVS, analysis)
Conceptual shift : Power nets become functional signals
Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
6
Methodology and design flow impacted
Si2-Accelera Low Power Workshop, CTO/SoCDT, Herve Menager, October 5th, 2006
10
Short Term need ( 2) – Fill hole in Verification
Low leakage design techniques have created a real paradigm shift.
Power and ground nets are now becoming functional nets.
They are not all explicitly in RTL or netlist levels.
Proper connection of any other functional nets is verified by functional simulation….against the RTL or netlist.
Being able to verify the power down modes , retention, recovery at power-on, etc in the context of RTL simulation is becoming mandatory.
Verification tools should be power modes aware.
6
For IP, context is keyMemory
Processor
SoC
“Always-on” depends on context
Buffer within CPUSoC buffer routed across CPU
Characterization range is important
Cells, memory could be different
Complex featuresMultiple VDD, VSS pinsMultiple operating voltagesVoltage dependent behaviorClosed-loop behavior (tunable voltage)
Don’t want formats limiting IP features
2
Canonical design to argue over…….Start with a realistic example to exercise interfaces and control
Power and Ground are signals – but not as we know them……..Power Gating, Retention, (Dynamic) Voltage Scaling, Level shifters, Memory…Isolation clamps across boundaries, a number of supply voltages
e.g. a SOC with always powered logic plus:
VSOC
RAM
with Core Retention
(& additional power rail?)
VRAM
PG
sub-system
RETAIN
SRPG
subsystem
RETAIN
CPU
DVFS (& LV
retention?)
VCPU
14
Addressing power management challengesOperational and Standby (leakage)
Active power + leakage
Power gating/voltage scalingOn-chip – fast but with care to avoid dI/dt problemsOff-chip – may add latencies as long as 100’s of microseconds
Need to be able to quantifyReal-time cost (e.g. interrupt latency) in “wake-up” timesEnergy cost functions getting into/returning from power saving states
4 © NOKIA UPF Workshop / Oct 2006 /Naula
Current state …• Debugging capabilities are very poor
• Capacity issues• Complexity issues• Reporting weak and misleading
• Functional correctness difficult to verify• Tools are mostly in Gatelevel, should be in RTL
• Important is to have accuracy for RTL or otherwise it is not useful• All tools using different description for PM
• PM configurations currently having thousands of statements in SoC level• No automation; It is designers responsibility to verify that all definitions are
done correctly• Because updates for these definitions are done quite seldom, it is difficult to
keep in mind complex configurations• There is no automation for PM definitions verification
• Design hierarchy presentation varies in configuration files between tools, also between RTL and gate in same tool. Syntax is effected by scripting languages like perl and tcl
© 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 7
Traditional Design FlowTraditional Design Flow
HW/SW Co-Design
Architecture Design
RTL Design
Placement & Optimization
Floorplanning
Synthesis
Clock Synthesis
Optimization
Routing & Optimization
Sign-off: DRC/LVS
TimingVerification
Logic Verification
© 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 9
Techniques Relevant To IPTechniques Relevant To IP
Right size libraries– Smaller transistors lead to smaller parasitics– Performance trade-off
Multi-Vt libraries– Right Vt for the right paths at the right performance– Effectively used to control leakage– Increases the number of libraries needed to implement the design
Voltage Islands– Requires updates to deal with multiple power supplies and associated conditions– Requires special level shifting components to implement
Power Gating/On-Chip Regulation– Requires special power gating cells/regulation cells– Need to deal with “derived” power nets– Need to deal with POR cycle
Substrate Bias– Requires dealing with multiple power supplies and possibly “negative” power supplies– Requires special level shifting components to implement
© 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 10
So What Changes? … Everything …So What Changes? … Everything …
Low Power Core
Voltage IslandSupport
Voltage Island&
State RetentionSupport
On ChipRegulation Support
Voltage Island &Back Bias Support
VDD
VSS
VDD1
VSS
VDD2
VDD
VSS1
VSS
VSS
VDD
© 2006 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 12
So What Changes? … Everything …So What Changes? … Everything …
HW/SW Co-Design
Architecture Design
RTL Design
Placement & Optimization
Floorplanning
Synthesis
Clock Synthesis
Optimization
Routing & Optimization
Sign-off: DRC/LVS
TimingVerification
Logic Verification
PowerSign-off Spec
– 4 –Innovation Through Collaboration – 4 –Innovation Through Collaboration – Low Power Coalition
LibrariesIP
What Was the Problem?
LogicInformation
(Verilog)
Synthesis
Test
SVP
FormalAnalysis Simulation
ParserParser
Parser
Logic is “Connected”
P+R
Parser
Pars
er
ParserCan be Automated
Hardware
Parser
EquivalenceChecking
Parser
Management
Parser
PowerInformation
(CPF)
Power is Not “Connected”
Very Difficult to Automate
PowerInformation(no consistency)
LibrariesIP
Synthesis
Test
SVP
FormalAnalysis Simulation
ParserParser
Parser
P+R
Parser
Pars
er
Parser
Hardware
Parser
EquivalenceChecking
Parser
Management
Parser
– 8 –Innovation Through Collaboration – 8 –Innovation Through Collaboration – Low Power Coalition
● Dec 4, 2006 Cadence contributed CPF v1.0 to Si2
● January 12, 2007 LPC members unanimously voted and approved CPF v1.0 as Si2 Specification for low power standard
● January 17, 2007Cadence contributed CPF v1.0 parser source code to Si2
● March 5, 2007CPF 1.0 available to everyone at no cost as a Si2 standard
Si2 CPF Standardization
– 10 –Innovation Through Collaboration – 10 –Innovation Through Collaboration – Low Power Coalition
Common Power FileASCII file to capture
● Design intent and constraintsPower domain
Logical: instances as domain membersPhysical: power/ground nets and connectivityAnalysis view: timing library sets for power domains
Power LogicLevel Shifter LogicIsolation LogicState-Retention logicSwitch Logic & Control Signals
Power modeMode definitionsMode transition definitions
● Technology informationLevel Shifter Cells, Isolation Cells, State-Retention Cells, Switch Cells, Always On Cells
– 11 –Innovation Through Collaboration – 11 –Innovation Through Collaboration – Low Power Coalition
CPF Language● CPF is TCL-based.● CPF Language = TCL commands + CPF objects + Design objects
Power domainAnalysis view Delay corner Library set Operating condition
● Design objects: objects that already exist in the RTL/gate netlistModule, Instance, Net, Pin, Port
● Commands – 42 commandsset_* commands [version, scope, and general commands]define_*_cell commands [library cell description]create_*_rule commands [design intent]update_*_rules commands [implementation directives]
– 12 –Innovation Through Collaboration – 12 –Innovation Through Collaboration – Low Power Coalition
Minimal Command Set For Different Design Stages
create_power_domaincreate_nominal_conditioncreate_power_modecreate_state_retention_rulecreate_isolation_rulecreate_level_shifter_rule
define_library_setupdate_nominal_conditionupdate_power_mode
create_ground_netscreate_power_netsupdate_power_domaincreate_power_switch_rulecreate_analysis_viewcreate_operating_corner
Specify power intentsverification and simulationdesign explorationearly power estimation
More implementation detailssynthesisformal verificationDFT, ATPG, gate level power estimation
Complete physical implementation details
silicon virtual prototypingpower planningphysical synthesisstructural verificationsign-off power analysis
– 24 –Innovation Through Collaboration – 24 –Innovation Through Collaboration – Low Power Coalition
Specify Power Mode Transitions
create_mode_transition -name PM1toPM2 –from_mode PM1 –to_mode PM2 \-start_condition { pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }-clock_pin { pcu_inst/clk } –cycles 100
create_mode_transition -name PM2toPM3 –from_mode PM2 –to_mode PM3 \-start_condition { pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }-clock_pin { pcu_inst/clk } –cycles 1000
create_mode_transition -name PM3toPM4 –from_mode PM2 –to_mode PM3 \-start_condition { !pcu_inst/ctrl[0] & pcu_inst/ctrl[1] }-clock_pin { pcu_inst/clk } –cycles 1000
create_mode_transition -name PM4toPM1 –from_mode PM2 –to_mode PM3 \-start_condition { !pcu_inst/ctrl[0] & !pcu_inst/ctrl[1] }-clock_pin { pcu_inst/clk } –cycles 200
PDcore PDau PDlu PDalu PDrfPM1 1.2v
0.8vPM3 0.8v off off off 1.2PM4 0.8v 1.2v 1.2v 1.2v off
1.2v 1.2v 1.2vPM2
1.2v1.2v 1.2v 1.2voff
PM1
PM2
PM3
PM4
– 27 –Innovation Through Collaboration – 27 –Innovation Through Collaboration – Low Power Coalition
Low Power Design Verification Using CPF
● No need to specify power or ground nets at RTL stage● No need to specify implementation related constraints at this stage such
as library, timing constraints etc● Minimal set of CPF commands for front-end designers to use
Simulation toolsto simulation power domain on and off to simulate power mode transitions for DVFS
Coverage toolsto check power mode coverageto check power mode transition coverage
Assertion toolsto generate power domain and mode aware assertions
Verification toolsto check for the correctness and completeness of CPF
– 33 –Innovation Through Collaboration – 33 –Innovation Through Collaboration – Low Power Coalition
Low Power Logic Implementation and Verification Using CPF
● Still, no need to specify power or ground nets at this design stage● Minimal set of CPF commands for designers to use
Logic synthesis toolsto synthesize isolation, level shifter and state retention logicto perform power domain aware logic synthesisto perform power mode aware (DVFS) synthesis
Test synthesis toolsto perform power domain and power mode aware DFT synthesisto generate power domain aware test control logic
Formal Verification toolsto check the correctness of low power structural implemented by synthesis toolsto perform low power equivalency checking (RTL+CPF vs Netlist)
Simulation toolsto perform power aware gate level simulation to generate additional assertions for gate level simulation
Analysis toolsto perform power domain aware and power mode aware power analysis
– 45 –Innovation Through Collaboration – 45 –Innovation Through Collaboration – Low Power Coalition
?
CPF Enabled Low Power Design Flow
Design Creationb
Synthesis
ConstraintGeneration
Design for Test
SVP
Equivalence Checking
Constraint Validation
SpecificationFunction, timing, power
RTL Coding
RTL + CPFCoding
Iterate
Quick architectural explorationRe-use pre-verified IPInstantiate single
RTL with different power profiles
Hand off to drive physical implementation
Physical ImplementationChip Integration
Prototyping
Physical Synthesis
Routing
DFT A
nalysis
Sign-off
ATPG
Constraint Validation
Equivalencechecking
LVS/DR
C/Ext
GDSII
Constraints CPF Netlist
Golden specification eliminates
assumptions and miscommunications
Automatic partitioning of power domains
Automatic scheduling of test modes
Single power specification used from specification to GDSII
Verif
icat
ion
Cov
erag
e
Test
benc
h A
utom
atio
n
Verification
Structural &Funct. Checks
FormalAnalysis
Simulation
Acceleration& Emulation
Functionally verify advanced power implementation
techniques Iterate
Power Forward Initiative Continues Growth 24 companies across the design chain
www.powerforward.org
26
– 48 –Innovation Through Collaboration – 48 –Innovation Through Collaboration – Low Power Coalition48
TSMC 8.0 Low Power Reference Flow
CPF
CPF
CPF Quality CheckConformal Low PowerCPF Quality Check
Conformal Low Power
CPF-Enabled Functional simulationIncisive Design Team SimulatorIncisive Design Team Manager
CPF-Enabled Functional simulationIncisive Design Team SimulatorIncisive Design Team Manager
CPF-Enabled Logic Synthesis & DFTEncounter RTL Compiler
CPF-Enabled Logic Synthesis & DFTEncounter RTL Compiler
CPF-Enabled LEC + Power ChecksConformal Low Power
CPF-Enabled LEC + Power ChecksConformal Low Power
CPF-Enabled LEC + Power ChecksConformal Low Power
CPF-Enabled LEC + Power ChecksConformal Low Power
CPF-Enabled Timing & SI signoffEncounter Timing System
CPF-Enabled Timing & SI signoffEncounter Timing System
CPF-Enabled Physical implementationSoC Encounter
CPF-Enabled Physical implementationSoC Encounter
CPF-Enabled Logic simulationIncisive Design Team Simulator
CPF-Enabled Logic simulationIncisive Design Team Simulator
CPF-Enabled ATPGEncounter Test
CPF-Enabled ATPGEncounter Test
CPF-Enabled IR drop & Power signoffVoltageStorm-DG
CPF-Enabled IR drop & Power signoffVoltageStorm-DG
CPF-Enabled Leakage & Thermal AnalysisEncounter Timing System
CPF-Enabled Leakage & Thermal AnalysisEncounter Timing System
www.tsmc.com
Confidential
ARM1176-IEM iRM Features
Automated RTL to GDS Multi Supply Voltage Implementation flowCPF based flow
CPF file is used to describe the low power intent and to drive implementation and verification flow
Multi Mode Multi Corner (MMMC) analysis and optimization
Ensures design is optimized across complete voltage and frequency range
Tri-lib based flowProvides accurate interpolation for DVFS and IR drop analysisECSM extensions to .lib
Confidential
CPF Flow Availability
VRAM
VDDCORE VDDRA
M VSS
VRAM
VCORE
VSOC
ARM1176-IEM iRMavailable now from ARMShipped along with standard ARM1176 RTL deliverablesIncludes CPF, scripts, documentation and front end libraries (130G)Port to ARM Advantage 65GP in H108
– 49 –Innovation Through Collaboration – 49 –Innovation Through Collaboration – Low Power Coalition49
ARC Proof Point Project Using CPF Based Low Power Solution
● Simulation with CPF identifies problems that you will not otherwise identify
● CPF aids communication of power intent across team boundaries, ensuring accurate implementation at all flow stages
● Significant power savings results using these techniques
Always On
SCQSCQSCQ
SCQ SCM SDMSIMD
SCM SDM
I$ D$ SCQARC700
I$ D$
Clock Gating Domains
Power DomainsFunctional Blocks
ARC700 with SIMD Co-Processor
• For high bit-rate data streams, both the ARC and the SIMD run flat out
• For lower bit-rate data stream, the subsystem can be run at a lower frequency
• For generic processing, the SIMD can be inactive
Power Forward low-power implementation & verification project results
Copyright© 2007. ARC International. All rights reserved.
• ARC Energy PRO: new active power management technology– Reduces power by as much as four fold – End-to-end fully verified power management solution –
reduces TTM– Ideal for battery-operated portable applications
• Integrated with Cadence Low-Power Solution and CPF to ensure accurate implementation at all flow stages
• Energy PRO technology will be included in future ARC processor cores and multimedia subsystems
51
©20
08S
eque
nce
Des
ign,
Inc.
CPF Out Current Status and Next StepsReleased to customers on Feb 11th, 2008
An official part of the PowerTheater 2008.1 releaseCPF Out marked as beta in the releaseTested the flow using RC on numerous small tests and the Nano CPU example from Cadence
Next StepsGet feedback from key customers over the next month
Verify interpretation of create_global_connection, create_power_nets and create_power_switch commands
Do a CPF-In for power verification flow
Leadership in Design for Power (DFP)
– 51 –Innovation Through Collaboration – 51 –Innovation Through Collaboration – Low Power Coalition51
Power DomainPower Mode
PD0 PD1 PD2 PD3 PD4 PD5
PM1 1.2V 1.2V 1.2V 0.74V 0.74V 0.74V
PM2 1.2V PSO 1.2V 0.74V 0.74V 0.74V
PM3 1.2V 1.2V PSO 0.74V 0.74V 0.74V
PM4 1.2V 1.2V 1.2V PSO 0.74V 0.74V
PM5 1.2V PSO PSO PSO 0.74V PSO
Driver
PD4:0.74V
PD0: 1.2V(Default, Always On)
PD5:0.74V
PD3:0.74V
PD2:1.2V
PD1:1.2V
PSOcntl
PSGcntl
ISOcntl
Validated CPF and CPF-based flow for major low power methodologies in NEC Electronics386 checkpoints evaluated successfullyCPF describe-abilityMulti-Supply-Voltage (MSV)Power Shut Off (PSO)State Retention Logic (SRL)Variable Voltage Library (VVL)Clock Tree Gating (CTG)
CPF based flow will be in use from Q3/2007
NEC Proof Point Project Using CPF Based Low Power Solution
NEC Electronics NEC Electronics Corporation Corporation
65nm 6 Power Domains5 Power Modes2 Supply Voltage
– 50 –Innovation Through Collaboration – 50 –Innovation Through Collaboration – Low Power Coalition50
Fujitsu Proof Point Project Using CPF Based Low Power Solution
CPU1 CPU2peripherals
Power Switch
90nm 940K instances11 Power Domains19 Power Modes
Power Domains
● Verified with test designPSO functional verification with simulationLow power structural and physical check (Shifters/Isolators/Power switches)Domain aware place and route
● ConclusionFunctional verification is necessary for complex PSO design for design bugsStructural check with CPF could verify LP designFujitsu will support CPF-based ASIC flow for their customers Silicon Proven September ‘07Silicon Proven September ‘07
DVFS
– 52 –Innovation Through Collaboration – 52 –Innovation Through Collaboration – Low Power Coalition52
Power Forward low-power platform SoC results
● CPF-based functional verification (using simulation) catches system level power issues early in the flow
● Use of CPF ensured what implementation built was what was verified
• SoC consists of 11 islands • 3 major power consumers -RISC
CPU, VLIW DSP & L2 System Cache are controlled using DVFS
• High bandwidth expansion ports enable extension, with graphics or cellular modem subsystems
NXP Proof Point Project Using CPF Based Low Power Solution
Low-Power Methodology
A Practical Case Study in Low-Power Methodology
• Special thanks to NXP Semiconductors
Si2 – Innovation Through Collaboration
Low-Power Methodology
• New! Educational eBook resource for industry… no-cost download (168pp.)• Contents include:
– LP Techniques - Design / Verification / Implementation w/ CPF– Real end-user chip design experiences
courtesy, PowerForward.org
Additional Chapters in the pipeline
• Low power test - Cadence
• TSMC –Reference Flow 8.0, 9.0, Low Power Physical IP
• ARM (3) – 1176 RM, Cortex A8, historical LP collaboration in SDC, How to use ARM LP IP
• UMC – Ulterior PPP (with ARM)
• Sequence -- Architectural power exploration
• Faraday – Low power service success
• GUC - success story
• AMD – PPP
Raising The Low-Power Debate
What Is The Low-Power Coalition?
● Flow-based solutions
Standards to promote integration of open technologies into cohesive flows CPF was contributed to LPC 4Q'06, approved as Si2 standard in March 2007
CPF is fully open to the entire industry at no cost – anyone can influence direction
Analyze / develop semantic consistency across data exchanges
● User-centric and comprehensive
Focused on user needs for faster adoption into production chip design flows
Owns the industry's low-power roadmap of requirements
Comprehensive: enabling software, training & educational materials, articles, books, conferences, press coverage, etc.
LPC Member Companies
● Advanced Micro Devices*
● ARM
● Atrenta
● Azuro
● Cadence Design Systems
● Calypto Design Systems
● Chipvision Design Systems AG
● Entasys Design
● Freescale Semiconductor
● IBM Corporation
● Intel Corporation
● LSI
● NXP Semiconductors
● Sequence Design
● Virage Logic
• 6 End-Users• 7 EDA Companies• 2 IP Providers
(*) = LPC Chair
LPC Structure, Working Groups
● Full LPC membership (AMD, Chair) Business/policy & standards approvals
● Technical Steering Group (TSG): charters working groups, owns the low-power technology roadmap Includes 3 Chief Architects (Cadence, IBM, LSI)
● Active and completed working groups: Flow WG – align on low-power reference design flow and design
techniques to drive clarity for enhancements Data Model and API WG – map clear semantics and data
relationships in CPF, add API interface support to CPF Format WG – define priorities and detailed requirements (RFT);
define the next revision of CPF (v1.1) > 100 pp. of (backward-compatible) enhancements
Format Comparison WG – report on technical comparison of CPF and UPF (Done, results widely shared)
LPC Structure
Full LPC Membership
Technical Steering Group
3 Chief Architects
Flow WG Format WG
Format Comparison WG
Data Model & API WG
LPC Working Groups
● Flow Working Group Definition of complete reference flow from ESL to GDSII
Target completion date: 2Q08 Analysis of power stimuli for SoC power estimation
Target completion date: 2Q08 Compilation of all known low power design techniques
Target completion date: 2Q08
LPC Working Groups
● Data Model Working Group LP Glossary v1.0 completed and posted for download Developing UML-based models to support enhanced power-aware design
Will be based on OpenAccess data model Target date: 1H08
LPC Working Groups
● Format Working Group Develop format extensions requirements document
Target date: 1Q08 (DONE) Open RFT, receive contributions
DONE CPF 1.1 standardization target: Aug '08 CPF roadmap alignment across both Flow and Data Model WGs
Recent LPC / CPF Publicity
Recent LPC / CPF Publicity
– 1 –Innovation Through Collaboration – 1 –Innovation Through Collaboration – Low Power Coalition
Format Enhancement Requirements
Immediate - Requirements for Version 1.1 (extension to 1.0)Hierarchical flow Support.Memory modeling styles and support. Gatelevel verification Flow CPF support.Power estimation SupportClocking and related updates are required to drive power optimization.
Medium Term – Requirement for CPF 1.2Pre-Si and post_Si power modeling and budgeting.Test power definitions not represented in CPF.Investigate Load_foreign.IO modeling and representation.
Long term - Next GenerationCPF needs to drive debug related to power.CPF based system level definition.
1.1
1.2
2.0
– 3 –Innovation Through Collaboration – 3 –Innovation Through Collaboration – Low Power Coalition
Hierarchical Flow – Bottom Up
Chip Level power StructureCPF
Memories Hard IP with(Behavioural)
Hard IP withRTL or Gates
Soft IPRTL
Multiple CPF Multiple CPF Multiple CPF Multiple CPF
– 64 –Innovation Through Collaboration – 64 –Innovation Through Collaboration – Low Power Coalition: Si2 Confidential
Soft IP Reuse
● IP is defined with multiple power structures and functionalities● At chip level, part of the power structures or functionality will be used● Need to
Merge power domainsReconfigure power domains Reconfigure power rulesMerge rules and resolve precedenceIntegrate power modes
Need to be capable of composing modes description from combination of power supplies and other modes.Allow block level configurations to refine top level power mode..Should be capable of specifying the performance parameter.
– 62 –Innovation Through Collaboration – 62 –Innovation Through Collaboration – Low Power Coalition: Si2 Confidential
Hierarchical Flow Requirements
● PerspectiveEnable IP reuseReuse Design Hierarchy and better organization.Enable Low power Custom IP Integration and verification.Support Bottom-up and Top Down Flow
● EnsuresConsistent RepresentationConsistent Integration styleConsistent VerificationConsistent Rules, semantics, precedence policy.
– 67 –Innovation Through Collaboration – 67 –Innovation Through Collaboration – Low Power Coalition: Si2 Confidential
Custom IP Support Requirements
● A Hard IP can be connected to multiple power ports and significant logic may belong to multiple domains.
Assigning the entire component to single domain may create incorrect representation.
● Support integration of custom IP. To most of the flow it is considered a blackbox
● Support Verification of Custom IP using CPFIP may have non-trivial power structuresIP has a behavioral model with no relation to hierarchy of power domains.
● Need toMaintain IP level power control sequence.Define the power structure using only boundary ports and registers.Provide hooks to use the behavioral model Integrate power connections at chip level
– 74 –Innovation Through Collaboration – 74 –Innovation Through Collaboration – Low Power Coalition: Si2 Confidential
Power Network Component Models
● Power Network ComponentSwitchesRegulatorsConverters
● Provide an approach to model the power network components.Component inputComponent outputComponent EfficiencyComponent Electrical Characteristics
● Need recommendations from flow group and other working groups.
– 77 –Innovation Through Collaboration – 77 –Innovation Through Collaboration – Low Power Coalition: Si2 Confidential
Proposed CPF Roadmap
2.0
1.2
1.1
Start H1/09Start Q1/08 Start H2/08
Si2 – Innovation Through Collaboration
Summary of Low-Power Collateral
1. CPF v1.0 Standard2. CPF v1.0 Parser software3. CPF Pocket Reference Guide4. CPF On-line Tutorial - both in English and Mandarin (2.5 hrs)5. Low-Power Glossary of Terms6. CPF v1.1 Requirements Document (and RFT)7. Low-Power Industry Roadmap8. “A Practical Guide to Low Power Design” (168pp. ebook)
For downloads, go to:
www.si2.org/?page=726
Silicon Integration Initiative 1
DFMC
New... CPF
Relational Analyzer
Silicon Integration Initiative 2
Why
• Structured, Low Power design methodology is currently the exclusive and elite domain of a few “Power Users”
The CPF Relational Analyzeris for everybody else
• Simple, Interactive Training Tool
• Realizes in open source software the key concepts of the CPF Format
• Accelerates the CPF learning curve LP Design Using CPF - Who me?
Silicon Integration Initiative 4
Plenty of Room for Confusion (and Errors)
Multiple SourceFiles
Multiple GroupsTop LevelPower Targets
Power
Domains
Multiple Levelsof hierarchy
Same DomainConstraints
Level Shift
RulesMultiple Libraries w/ Multiple Variants
Power UnitmW
Power UnituW
Incremental
Changes
Silicon Integration Initiative 6
set_design top# Set up logic structure for all power domainsset_time_unit usset_power_unit uWcreate_power_domain -name PDcore -defaultcreate_power_domain -name PDalu -instances {inst_A inst_B} -shutoff_condition {!pm_inst.pse_enable[0]}create_power_domain -name PDrf -instances inst_C -shutoff_condition {!pm_inst.pse_enable[1]}create_power_domain -name PD4 -instances inst_D -shutoff_condition {!pm_inst.pse_enable[2]}# Define static behavior of all power domains and specify timing constraintscreate_nominal_condition -name high -voltage 1.2create_nominal_condition -name medium -voltage 1.1create_nominal_condition -name low -voltage 1.0create_power_mode -name PMhot -domain_conditions {PDcore@high PDalu@medium PDrf@high PD4@low} -defaultcreate_power_mode -name PMcool -domain_conditions {PDcore@high PDrf@high PD4@low}create_power_mode -name PMsleep -domain_conditions {PDcore@high PD4@low}create_power_mode -name PMhibernate -domain_conditions {PDcore@low}# Set up required isolation and state retention rules for all domainscreate_state_retention_rule -name sr1 -domain PDalu -restore_edge {!pm_inst.pge_enable[0]}create_state_retention_rule -name sr2 -domain PDrf -restore_edge {!pm_inst.pge_enable[1]}create_state_retention_rule -name sr3 -domain PD4 -restore_edge {!pm_inst.pge_enable[2]}create_isolation_rule -name ir1 -from PDalu -isolation_condition {pm_inst.ice_enable[0]} -isolation_output highcreate_isolation_rule -name ir2 -from PDrf -isolation_condition {pm_inst.ice_enable[1]} -isolation_output highcreate_isolation_rule -name ir3 -from PD4 -isolation_condition {pm_inst.ice_enable[2]} -isolation_output lowcreate_level_shifter_rule -name lsr1 -to {PDcore PDrf}end_design
CPF Format Concepts
DefinePDs
DefineNominals
PMsBind PD & NC
Ru
les and
mo
re rules
What if this command was in a different file and the IP in PDcore had not been characterized at the “low” nominal condition?
Silicon Integration Initiative 7
CPF Relational Analyzer
• Each object in the CPF hierarchy is tracked separately via metadata• Architecture handles hierarchy merging, module cloning & port mapping
• Broad analysis – Analyze all objects and all O2O relationships
• Deep analysis – Every attribute, every object with every update
Interactive and Incremental:
Designed for “Hands-on” learners with English as a Second Language
Exposes the final state of the design intent compiled from many sources
Search and Report capabilities:
All searches can use standard wildcards of *, ?, [a-z], [0-9]
Any combination of CPF Objects, Property Names and Property Values
Silicon Integration Initiative 5
CPF Information Model
Si2 – Innovation Through Collaboration
Si2 - Innovation Through Collaboration
Thank You!
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