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Low-Frequency Harmonic Reduction in Single-Phase
Power Supply Systems
Javier Sebastián
Universidad de OviedoSpain
CIEP’98-1
Focusing the presentation
{• Single-Phase
• Three-PhaseLine
Power {• High power
• Low power (110-220V, <16A)
Energy{• Recovery to line
• No recovery
Philosophy {• Modifying conv. topology
• External connection
Converter {• Ac-to-dc
• Ac-to-ac
CIEP’98-2
Power Factor (PF) and Total Harmonic Distortion (THD)
PF=Input power
Input voltage, rms X Input current, rms
THD=(Input current, rms)2 - ( Its 1ST harmonic, rms)2
Its 1ST harmonic, rms
CIEP’98-3
Questions (Q) & Answers (A):• Q: Actually, are PF and THD the most important parameter from the point of view of regulations?
• A: No, they are not
• Q: What do regulations say about PF and THD?
• A: Almost NOTHING. They only speak about the maximum value of each harmonic
• Q: Frequently, what is the most usual objective designing?
• A: To comply with regulations at as a low cost as possible. Neither PF=1 nor THD=0 are the main objectives
CIEP’98-4
Suggestion: to change words and concepts
Power Factor Correction
Low-Frequency Harmonic Reduction
•To comply with regulations•Low efficiency penalty•Low cost penalty
Objectives:
CIEP’98-5
Balanced3 equipment?
Portable tool?
Lightingequipment?
EspecialWaveform &P<600 W?
Motor driven, control?
ClassA
ClassB
ClassC
ClassD
Yes
No
No
No
No
No
Yes
Yes
Yes
Yes
35%
igpeak
/3 /3 /3Clase D Template
IEC 1000-3-2IEC 1000-3-2
CIEP’98-6
Special wave shape for Class D equipement
35%
igpeak
/3 /3 /3
“Each half cycle of input current is within the envelope for at least 95% of the time; peak of current coincides with center line”
CIEP’98-7
IEC 1000-3-2: Harmonics limitsn Class A
(A rms)Class B(A rms)
Class C(% fun.)
Class D(mA/W)
3 2.3 3.45 30PF 3.4
5 1.14 1.71 10 1.9
7 0.77 1.155 7 1.0
9 0.40 0.60 5 0.5
2 1.08 1.62 2 -
4 0.43 0.645 - -
6 0.30 0.45 - -
8<n<40 1.84/n 2.76/n - -
CIEP’98-8
Type of solutions
Input current waveform
sinusoidal non-sinusoidal
Dev
ices p
assi
veac
tive
passive & sinusoidal
passive & non-sinusoidal
active & sinusoidal
active & non-sinusoidal
CIEP’98-9
Passive solutions
Robust & reliable
Cost effective
Low power
No preregulation
High weight & big size
Start-up problems
Medium quality of input current *
Active solutions Preregulation
Small size & low weight
No start-up problems
Either low & high power
High quality of input
current *
More expensive
Less robust & reliable
* It depends on the input current goalCIEP’98-10
Sinusoidal input current
Ideal operation
Universal compliance
High power
Expensive
Useless at 50-60Hz if passive
Lower efficiency
Non-sinusoidal input current
Higher efficiency
Cheaper
Either passive or active
Compliance depending on regul.
Low power
CIEP’98-11
Type of solutions
Input current waveform
sinusoidal non-sinusoidal
Dev
ices p
assi
veac
tive
passive & sinusoidal
passive & non-sinusoidal
active & sinusoidal
active & non-sinusoidal
CIEP’98-12
Series-resonant tank
High PF, low THD
Very bulky elements at 50-60Hz
Useful at HF(e.g. 20 kHz)
Current
Voltage
Eitherdc-to-ac
or dc-to-dcconverter
LR
CR
CB VB
IB
CIEP’98-13
Design trade-offQ= Z/RZ=(LR/CR)1/2
R=VB/IBCurrent
Voltage
Voltage
Current
High Q
Low Q The higher Q is: The higher PF is
The lower THD is
The higher stresses in devices are
The bulkier the inductor is
CIEP’98-14
Type of solutions
Input current waveform
sinusoidal non-sinusoidal
Dev
ices p
assi
veac
tive
passive & sinusoidal
passive & non-sinusoidal
active & sinusoidal
active & non-sinusoidal
CIEP’98-15
LC input filter with dc-side inductor (I)
Eitherdc-to-ac
or dc-to-dcconverter
LF
CB
• Up to 300W• Design in Class D• Different results if ac-
side inductor
CIEP’98-16
Current
Voltage
LC input filter with dc-side inductor (II)
35%
igpeak
/3 /3 /3
Class D template
200W, 180-260V
23.3mH, EI-62.5, 0.58lb, 1.1W (losses)
200W, 90-260V
23.3mH, EI-87, 1.57lb, 2.74W (losses)
CIEP’98-17Current
LCC input filter with dc-side inductor & capacitor (I)
Eitherdc-to-ac
or dc-to-dcconverter
LFCF
CB
• Up to 300W• Design in Class A• Different results if ac-
side inductor LF & CF
Current
Voltage
CIEP’98-18
LCC input filter with dc-side inductor & capacitor (II)
35%
/3 /3 /3
igpeak
Class D template
Class D template
Designing for Class A operation
CIEP’98-19
Type of solutions
Input current waveform
sinusoidal non-sinusoidal
Dev
ices p
assi
veac
tive
passive & sinusoidal
passive & non-sinusoidal
active & sinusoidal
active & non-sinusoidal
CIEP’98-20
Resistor Emulator concept
Resistor Emulator
(dc-to-dcconverter)
pg(t)
vg(t)
ig(t)
pO(t)
PO
iO(t)
VO
IO
VO
iO(t) IO
ig(t)
vg(t)
CIEP’98-21
Resistor Emulator’s properties (I)
VOconst.
Resistor Emulator
(dc-to-dcconverter)
VOvg(t)
•The voltage conversion ratio m(t) changes from VO/ Vg to infinity
m(t)=VO
=VO/ Vg
vg(t) sin(t)vg(t)
CIEP’98-22
VO
Resistor Emulator
(dc-to-dcconverter)
iO(t) IO
iO(t)
VO
IO
r(t)=VO
= R
iO(t) 2sin2(t)
R=VO/IO
•The load resistance seen by the converter, r(t), changes from R/2 to infinity
Resistor Emulator’s properties (II)
CIEP’98-23
Consequences of these properties (examples) (I)
VOvg
ig
Buck off
Buck working
VO
vg
ig
From property #1
A Buck conv. cannot work as resistor emulator
CIEP’98-24
Consequences of these properties (examples) (II)
•Series Resonant Converter (SRC) cannot be used as Resistor Emulator (from property #1)
•Zero-Voltage-Switched Quasi Resonant Converters (ZVS QRC) cannot be used as Resistor Emulator (from property #2), because they cannot operate at no load.
CIEP’98-25
Consequences of these properties (examples) (III):
Study of the current conduction mode (I)
Ac-to-dc
k[r(t)]=2L/[r(t)T]
m(t)=VO/vg(t)
k[r(t)]>kcrit[m(t)] CCMk[r(t)]<kcrit[m(t)] DCM
VO
ResistorEmulator
L
Rr(t)vg(t)
K(R)=2L/(RT)M=VO/Vg
K(R)>Kcrit(M) CCMK(R)<Kcrit(M) DCM
VgStandar
ddc-to-dc
LR
Dc-to-dc
VO
CIEP’98-26
Consequences of these properties (examples) (IV):
Study of the current conduction mode (II)
k[r(t)]>kcrit[m(t)] CCMk[r(t)]<kcrit[m(t)] DCM
Kapparent(R)=2L/(RT)k’crit[m(t)]= kcrit[m(t)]/[2sin2(t)]
Kapparent(R) >k’crit[m(t)] CCMKapparent(R) <k’crit[m(t)] DCM
CIEP’98-27
Consequences of these properties (examples) (V):
Study of the current conduction mode (III)
Kapparent(R) >k’crit[m(t)] CCMKapparent(R) <k’crit[m(t)] DCM
max. of {k’crit[m(t)]} = k’crit max
min. of {k’crit[m(t)]} = k’crit min
ALWAYS CCM ALWAYS CCM Kapparent(R) > k’crit max
ALWAYS DCM ALWAYS DCM Kapparent(R) < k’crit min
CIEP’98-28
Consequences of these properties (examples) (VI):
Study of the current conduction mode (IV)
K’crit max K’crit min
Buck-Boost,SEPIC, Cuk
1/(2M2) 1/(2M+1)2
Boost 1/(2M2) (M-1)/(2M3)
M=VO/Vg PEAKvg(t)= Vg PEAK sin(t)
ALWAYS CCM ALWAYS CCM Kapparent(R) > k’crit max
ALWAYS DCM ALWAYS DCM Kapparent(R) < k’crit min
CIEP’98-29
Control of Resistor Emulators (I)Multiplier approach control (I)
dc-to-dcconverter
Input current fixed by the reference
CIEP’98-30
Control of Resistor Emulators (I)
dc-to-dcconverter
Multiplier approach control (II)
Input current sinusoidal & its value fixed by the reference
CIEP’98-31
Control of Resistor Emulators (I)
Low-passfilter
dc-to-dcconverter
Multiplier approach control (III)
Input current sinusoidal & its value fixed by the voltage feedback loop CIEP’98-32
Control of Resistor Emulators (II)
Controller fordc-to-dc conv.
dc-to-dcconverter
Low-passfilter
Filter Bulk
Voltage-follower approach control
CIEP’98-33
Either low or high output-impedance topologies
Perfect PF & THD
Lower losses in the transistor
Current sensor
Multiplier
More expensive
No current sensor
No multiplier
Cheaper
Lower losses in the diode
Only high output-impedance topologies
Sometimes THD
Voltage-Follower Multiplier
Control of Resistor Emulators (III)Multiplier vs. Voltage-Follower
CIEP’98-34
Control of Resistor Emulators (IV)
Low-passfilter
dc-to-dcconverter
New block
Improving THD in some converters with voltage-follower control
CIEP’98-35
Resistor emulator topologies (I)One switch, no isolation (I)
Boost
Buck-boostCIEP’98-36
Resistor emulator topologies (II)One switch, no isolation (II)
SEPIC
Cuk
CIEP’98-37
Resistor emulator topologies (III)
stress insemic.
inductor atthe input
switch toGND
VO/ Vg galv.isolation(possibl.)
Protection
Boost Low Yes Yes >1 No No
Buck-Boost
High No No <1, >1 Yes Yes
SEPIC &Cuk
High Yes Yes <1, >1 Yes Yes
Comparing basic topologies
CIEP’98-38
Resistor emulator topologies (IV)
SEPIC
Cuk
Flyback
•One switch
• Isolation
CIEP’98-39
Resistor emulator topologies (V) Voltage-Follower control (I)
Buck-Boost in DCM
ig av
ig av
ig aviS
iSiL
iL
Ideal Resistor Ideal Resistor EmulatorEmulator CIEP’98-40
Resistor emulator topologies (VI)Voltage-Follower control (II)
Boost in DCM, fS=const.
ig av
ig av
iL
iL
Non-ideal Resistor Non-ideal Resistor EmulatorEmulator
ig av
CIEP’98-41
Resistor emulator topologies (VII)Voltage-Follower control (III)
ig av
iL
iL
Ideal Resistor Ideal Resistor EmulatorEmulator
ig av
ig av
Boost in the boundary DCM/CCM
• ton const. each cycle
• toff depends on vg=(t)
• Therefore, fS=variable
ton toff
CIEP’98-42
Resistor emulator topologies (VIII)
SEPIC & Cuk in DCM
Voltage-Follower control (IV)
ig av
ig av
iL ig av
iL
Ideal Resistor EmulatorIdeal Resistor Emulator(very low input current ripple)(very low input current ripple)
CIEP’98-43
Resistor emulator topologies (IX)Two switches, no isolation
Buck Boost
Boost=swt.Buck=on
Boost=offBuck=swt.
VO
VO
Vg
Vg
CIEP’98-44
Resistor emulator topologies (X)Two switches, isolation
Current-Fed Push-Pull
To avoid starting-up & stopping problems
CIEP’98-45
Resistor emulator topologies (XI)High-frequency topologies (I)
Integration of parasitics
Only one switch
Either ZCS or ZVS
High output impedance (voltage-follower control)
Higher stress (conduction losses)
Frequency modulation
Resonant Soft-switchingPWM
Stress similar to PWM
Constant frequency
Either ZCS or ZVS
Several switches
Complex controller
CIEP’98-46
Resistor emulator topologies (XII)High-frequency topologies (II): parasitic
integration
ZCS-QRSEPIC
LR
CR CB
TransformerDiode
C’R
LRCB
CIEP’98-47
Resistor emulator topologies (XIII)High-frequency topologies (III): parasitic
integration
TransformerDiodesSwitches
C’R
LR
PRC
CIEP’98-48
Resistor emulator topologies (XIV)High-frequency topologies (IV):
voltage-follower control in resonant converters
ZCS-QR SEPIC
Current
Voltage
Current
Voltage
PRC
CIEP’98-49
Resistor emulator topologies (XV)High-frequency topologies (V): Zero Voltage
Transition topologies
ZVT Boost
Main diode
LRCR
CB
CD
CS
Main switch Aux. devices
CIEP’98-50
Resistor emulator topologies (XVI)High-frequency topologies (VI): Zero Voltage
Transition in IGBT using a MOSFET
Current-fed Push-Pull
S1CB
MainswitchesAux. switch
S2Saux
S2
S1
Saux
CIEP’98-51
Dynamic problems in Resistor Emulators
With multiplier approach control
Low-passfilter
dc-to-dcconverter
High gain at 100-120Hz
10dB lower20dB lower
Input currentfor different filters
sin
Same case with Voltage-Follower CIEP’98-52
PFC based on an one-stage Resistor Emulator
Cheap
Efficient
Poor dynamics
Big bulk
capacitor
power
voltage
LOSSES
voltage
power
Resis.Resis.Emul.Emul.
CIEP’98-53
Fast-response topologies
•Topologies with double power-processing
•Topologies with power processing lower than double
•Two stages in cascade
•Two-stage integrated topologies
•“Charge Pump” or “Line-Voltage Augmentation” type
•Parallel PFC’s
•Based on High-Efficient Post-Regulators CIEP’98-54
Two-stage PFC (I)
power
LOSSES
voltage
LOSSES
voltage voltage
* In comparison with one-stage Resistor Emulators
Good dynamics
Smaller bulk
capacitor*
Lower efficiency*
Expensive
22ndnd S. S.Resis.Resis.Emul.Emul.
CIEP’98-55
Two-stage PFC (II)
Resistor Emulator (Boost)
Dc-to-dc converter (Phase-Shifted Full Bridge)
Example
CIEP’98-56
Two-stage integrated topologies (I)
High stress
Low efficiency
Good dynamics
Smaller bulk capacitor
Cheaper
voltage
voltage
voltage
power
LOSSES
Fast-PFCFast-PFCFast-PFC
CIEP’98-57
Two-stage integrated topologies (II)
Resistor Emulator (DCM Boost)
Dc-to-dc converter (Either DCM or CCM Flyback)
CIEP’98-58
Two-stage integrated topologies (III)
ig av
ig av
•DCM Boost + Flyback
•If Flyback in DCM, lower voltage variation across CB
•Quasi-sinusoidal input current
High voltage & current stress in the transistor
CIEP’98-59
Two-stage integrated topologies (IV)
ig av
ig av•DCM SEPIC + Flyback
•If Flyback in DCM, lower voltage variation across CB (even no variation)
•Sinusoidal input current
High current stress in the transistorCIEP’98-60
Two-stage integrated topologies (V)Boost Integrated with Flyback Rectifier/Energy
storage/Dc-to-dc converter (BIFRED)
ig av
ig av
•Almost the same as DCM Boost + Flyback
CIEP’98-61
Two-stage integrated topologies (VI)
ig av
ig av
•DCM Boost Resistor Emulator + Half-Bridge Parallel Resonant inverter
Fluorescent Lamp
Integrated Resistor Emulator + inverter
CIEP’98-62
“Charge Pump” or “Line-Voltage Augmentation” type topologies (I)
Complex
Double control (for perfect input current)
Good dynamics
Small bulk capacitor
Higher efficiencyvoltage
voltage
voltagepower
LOSSES
Fast-PFCFast-PFC
voltage
CIEP’98-63
“Charge Pump” type topologies (II)
ig(t)
vS(t)
vS(t)
VB
VB
VS(t)
ig(t) dc-to-dcdc-to-dcoror
dc-to-acdc-to-acconverterconverter
ig(t)
vS(t)
vg(t) pg(t)
pS(t)pS(t)
pg(t)
vg(t)
ig(t) pS(t)=0.27pg(t)
CIEP’98-64
“Charge Pump” type topologies (III)
ig(t)
vS(t)
vS(t)
ig(t)
VB
pS(t)>0.27pg(t)
•vS(t) operates in DCM•vS(t) controlled by FM
pS(t)
pg(t)
Example:double Forward-Flyback
CIEP’98-65
“Charge Pump” type topologies (IV)Example:Full-Bridge + FM PRC
ig(t)
vS(t)
pS(t)>0.27pg(t)pS(t)
pg(t)
vS(t)
VB/2
VB/2
+-
Full BridgeFM PRCCIEP’98-66
Parallel PFC (PPFC) (I)
Input power
Output power
Power undergoing only 1 transformation (68%)
Power undergoing 2 transformations (32%)
CIEP’98-67
Parallel PFC (PPFC) (II)
LOSSES
Good efficiency
Several Saux
High stress Saux
Difficult design and control68%
power
Main stg.Main stg.
22ndnd stg. stg.
power
powerpower
CIEP’98-68
PPFC (III): Example
CBForwardForward
Current-fed Full BridgeCurrent-fed Full BridgeCIEP’98-69
High-Efficient Post-Regulators Concept
VBus
+-LOW-PASS
FILTER
+-PWM
Line
One-stage PFC
High-Efficient Post-Regulator
> 95%
PFCCONTROLLER
1.15·VBus - 0.87·VBus
No galvanic isolation
•Two-Output One-stage PFC + Two-Input Buck (TIBuck)
• Standard One-Stage PFC + Series-Switching Post-Regulator (SSPR) CIEP’98-70
High-Efficient Post-Regulators (I)Two-Output Resistor Emulator + Two-
Input Buck (TIBuck)
TIBuck
V1
V2
+-PWMPFC
CONTROLLER
+-LOW-PASS
FILTER
Two-outputResistor Emulator
POST-REGULATOR
Line Bus
CIEP’98-71
High-Efficient Post-Reg. (II): TIBuck
V1-V2VO-V2
V2V2
V1
V2
VOV1-V2
V2
VO
V2 V2
V1-V2
VO-V2
V2IO undergoing no power processing, (VO-V2)IO undergoing power processing CIEP’98-72
Computing TIBuck’s efficiency
HB=50%
75%
90%
85%
0.4 0.6 0.8 1
100
80
60
TIBUCK EFFICIENCY
V2/VO
is TIBuck efficiency
HB is Buck Half--Converterefficiency
TB
HBTB
HB2
O
1 (1 )VV
CIEP’98-73
High-Efficient Post-Regulators (III)Power processing in a PFC based on a TIBuck
P1
P2PO2
PO
PO1V1
V2
powerP1
P2
voltages
V2
V1VO
VO
PO2 PO1
powerPO
LOSSESLOSSES
R.Em.R.Em. TIBuckTIBuck85-90%
TB=99-97%CIEP’98-74
High-Efficient Post-Regulators (IV)Example: Two-output Flyback + TIBuck
+-
+-
PFCCONTROLLER
LOW-PASSFILTER
PWM
TIBuckTIBuckR. Em.R. Em.
V1=62V VO=54V
V2=47V
=85-82%, vg=85-264V rmsCIEP’98-75
VOC
Isolated dc-to-dc
converter
PWM +-
One-stage PFC
(Resistor Emulator)
PFCCONTROLLER
+-LOW-PASS
FILTER
VO VOSS
+ ++
- -
-
VOC<< VOPconv.<<PPFC
(non-isolated )SSPR
High-Efficient Post-Regulators (V)Series-Switching Post-Regulator (I)
CIEP’98-76
Computing SSPR efficiency (I) VOC
Dc-to-dcconverter
C
PWM +-
VOSS
+
+
-
-
VO
IO
IO1
IO2IO2
+
-
SSPRss
VOSS= VO+ VOC
IO= IO1+ IO2
C=VOC·IO2
VO·IO1
SSPR efficiency:
SS=VOSS·IO2
VO·IO
=1+KO
1+KO
CKO=VOC/VOCIEP’98-77
Computing SSPR efficiency (II)
60 70 80 90 10080
85
90
95
100
KO=0.3
0.20.1
KO=VOC/VO
Conv. efficiency, c [%]
SS [%]
C=80%KO=VOC/VO=0.1 ss=97.7%
Vo
ltag
es
vOSS
vO
Time
ALWAYSVOSS>VO
Transient response
Steady state
vOC
CIEP’98-78
High-Efficient Post-Regulators (VI)Series-Switching Post-Regulator (II)
power
voltage
LOSSESLOSSES
R. Em.R. Em.
DC/DCDC/DC
SSPRSSPR
vOSSvO
vOC
voltage & power
vO
vOSS
vOC
85-90%
SSPR=97-98%
Power processing
CIEP’98-79
High-Efficient Post-Regulators (VII)Series-Switching Post-Regulator (III)
Dc-to-dcconverter
Dc-to-dcconverter
Dc-to-dcconverter
Dc-to-dcconverter
Dc-to-dcconverter
n co
nverters
One-stage PFC
SSPR
Dynamic response improves by using n+1 converters instead of n
Same type of converter
CIEP’98-80
High-Efficient Post-Regulators (VIII)Series-Switching Post-Regulator (IV)
*For discharging CB in short-circuit
VOC=7V
VO=47V
VOSS=54V
+
+
+
- -
-
*
Implementation based on a Forward converter
CIEP’98-81
High-Efficient Post-Regulators (IX)Setting voltages
v1
vO
v2Vo
ltag
es
Time
ALWAYSV1>VO>V2
Transient response
Steady state
A good trade-off:V2 0.7-0.8V1
VO (V1+V2)/2
TIBuckTIBuck
Vo
ltag
es
vOSS
vO
Time
ALWAYSVOSS>VO
Transient response
Steady state
A good trade-off:VO 0.7-0.8VOSS
SSPRSSPR
CIEP’98-82
Topologies based on TIBuck (I)
TIBuck
Current-Fed Push-Pull
CIEP’98-83
Topologies based on TIBuck (II)
TIBuck
2xBoost
CIEP’98-84
Topologies based on SSPR
Boost
ForwardSSPR
Flyback
ForwardSSPR
CIEP’98-85
Forward
Current-fed Full Bridge
Forward SSPRCurrent-fed Full Bridge
PPFC versus 1 stg. PFC + SSPR
1 stg. PFC + SSPR
PPFC
CIEP’98-86
PPFC versus 1 stg. PFC + SSPR
power
power
powerLOSSES
Main stg.
2nd stg.
power
68%power
Smaller capacitor
LOSSES PdLOSSES
SSPR
85-90%
power
Pd POC
POSS
POSS
POC
Higher %
Simpler controlCIEP’98-87
DC/DC
1-stg.PFC
Type of solutions
Input current waveform
sinusoidal non-sinusoidal
Dev
ices p
assi
veac
tive
passive & sinusoidal
passive & non-sinusoidal
active & sinusoidal
active & non-sinusoidal
CIEP’98-88
VOvg
ig
Example: Buck PFCOne switch, no isolation, slow response
ig
vg
ig
vg
VOBuck off
Buck working vg
No start-up problems
Low stress in devices
Slow transient response
Always:VO<Vg peak
CIEP’98-89
Objectives for many new converters
Small size Reactive elements at switching frequency
Cheap Only one transistor & controller
Efficient Less than two power conversions
Always complying with the regulations (IEC 1000-3-2)
PF=1 & THD=0 is not the main worry!
CIEP’98-90
“Line-voltage augmentation” based on an additional output in dcm
Additional output in dcm
Line Load
Bulk cap.
Conventional dc-to-dc
converter
To help input rectifier to start conducting
iLine
vLine
CIEP’98-91
Example I
Additional output in dcm
Bulk cap.
Filter cap.
FlybackLine
iLine
vLine
Bulk cap.
Filter cap.
LineLoad
iLine
vLine
INTELEC’96
CIEP’98-92
Additional output in dcm
2 Switch Forward
Line
iLine
vLine
INTELEC’96
Example II
CIEP’98-93
CB
DCM Flyback
Forward with additional DCM Flyback-type output
Example III
CIEP’98-94
is
vO(is)Equivalent circuit with
additional output in dcm
+- vO(is)
is
iLine
vLine
Line LoadBulk cap.
dc-to-dc
standard
converter
Non-linearLoss-Free Resistor
Characteristic
Much energy re-cycledHigh current stress (dcm)Large variation in cap’s voltage
CIEP’98-95
+- vO(is)
iLine
vLine
Line LoadBulk cap.
dc-to-dc
standard
converter
LinearLoss-Free Resistor
Less energy re-cycledLower current stress (ccm)Smaller variation in cap’s voltage
is
vO(is)Characteristic Desired equivalent
circuit
is
CIEP’98-96
How can it be implemented?Forward with LD and with L in ccm
D2
iLDiL iO
VOVi
1:1 : n
D1
LDL
Driver
Voltage across D2
iLD
iL iO
td
t=d/fS 1/fSiO
vO(iO)Characteristic
VS
VS/RLF
VO=n·Vi·d - LD·fS·iO
VO=VS - RLF·iO
{ {
CIEP’98-97
Circuit proposed this year
(APEC’98)
Bulk cap.
Line
Load
iLine
vLine
Forward with LD & with L in ccm
Bulk cap.
Filter cap.
Flyback
Line
iLine
vLine LDL
L
LD
CIEP’98-98
Active Input-Current Shaper (AICS)
AICS
nS n2
n1vO(is)is
VO(0)=VS
VS can be freely chosen
With extra tap
AICS
n1 n2
vO(is)
VS depends on the duty cycle
Without extra tap
CIEP’98-99
Generalization of the AICS concept
AICS
AICS
Forward converter(conventional)
Forward converterwith active clamp
CIEP’98-100
Designing the Active Input-Current Shaper
vg=Vgsint
VS(Vg,PO) RLF
VC(Vg,PO)PO
dc-to-dcconverter
Vg min
Vg max
PO max
VS min(Vg min , PO max)
RLF to minimize re-cycled energy
VC(Vg,PO)
C(Vg,PO)
iLine
vLine
C
CIEP’98-101
Determining “Class” and compliance (IEC 1000-3-2)
Special wave shape
Class A: C>86.3ºcompl. up to high power levels (1kW)
Class D: C<86.3º
compl. if C>67.4ºBoundary between Class A & Class D
C=86.3º
2.5% 2.5%
CIEP’98-102
Design example 1
0 0.5 1
0º
60º
120º
180º
Class D
Class A
boundary
Normalized power
Vgmin
Vgmax
C
0.5 10
1
2
3
0
Vgmin
Vgmax
VC/Vg
Normalized power0 /3 2/3
0
0.5
1 Vgmin,PmaxVgmax,
Pmax
Vgmin, Pmax/2
Vgmax,Pmax/2
Input current
Line angle
High PF & low THDHigh VC variation
VS min= Vg min
d max=0.66
Vg max=1.2· Vg min
CIEP’98-103
Design example 2
VC/VgInput current
Line angle
Lower VC variation Lower PF & higher THD
0
0.5
1
0/3 /3
Vgmin,PmaxVgmax,
Pmax/2
Class D
Class A
boundary
Vgmin
Vgmax
C
0 0.5 1Normalized power
0º
60º
120º
180º
0
1
2
3
Vgmin
Vgmax
0.5 10Normalized power
VS min= Vg min/2
d max=0.66
Vg max=1.4· Vg min
CIEP’98-104
Experimental results: prototype
VC
Line
OutputBulkcap.
430H
1.4mH
Vg=190V-250VVO=50V, IO=0.5-2AfS=100kHz
Without extra tap
CIEP’98-105
Efficiency in the prototype
As dc-to-dc converter (voltage source across
the bulk capacitor)
As ac-to-dc converter with Input-Current
Wave-Shaping.3-7 points lower
25 50 75 10090
92
94
Output Power [Watts]
Eff
icie
ncy
[%
]
270 V dc355 V dc
310 V dc
25 50 75 10080
84
88 190 V rms
220 V rms
250 V rms
Output Power [Watts]
Eff
icie
ncy
[%
]
CIEP’98-106
2 3 4 5 6 7 8 9 10 11 12 13 140
0.1
0.2
0.3
0.4
0.5
IEC 1000-3-2
Measured
Pinput=121 WPF =0.845THD=52%
nth Harmonic
Inp
ut
curr
ent
[A]
ENVELOPE
ENVELOPE
Current 0.87 A/div
Current 0.43 A/div
PO=100W
PO=50W
Input current waveforms & harmonics
CIEP’98-107
Input current (transformer with extra tap)
voltage (100V/div)
220V, 100W
current (0.67AV/div)
Class D
voltage (50V/div)
envelope
current (0.67AV/div)
110V, 100W
Class A
CIEP’98-108
AICS: Conclusions•Main conventional topologies (no extra switches)
•Only 2 additional inductors and 2 additional diodes
•High-frequency filtered input current (ccm)
•Low “extra” stress (ccm & low capacitor voltage change)
•Main converter either in ccm or dcm
•Trade-off between harmonics and re-cycled energy (efficiency)
•Compliance with IEC 1000-3-2 with low efficiency penalty
CIEP’98-109
Other types of “shapers”(I) (APEC’97)
Either ccm or dcm.If ccm, leakage inductance is needed
CIEP’98-110
Other types of “shapers”(II) (Magnetic switch, INTELEC’95)
dcm
CIEP’98-111
Conclusions
•Passive, non-sinusoidal solutions are very interesting for low-power applications.
•Topologies based on Resistor Emulators need topological transformations in order to improve dynamic response.
•Active, non-sinusoidal solutions are very interesting from the point of view of cost. This is a promising field for researching.
CIEP’98-112
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