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Digital PWM Controlled DC-DC Switching Power SupplyPresenter: Koichi Shigematsu, Ph.D.Ansoft Japan KK
Contribution Author: Yoichi IshizukaNagasaki University
Distributed Power Supply
3.3V
1.8V
1.5V
1V-1.3V
0.8V- 2.5V
48V5V
3.3V
AC-DCConverter
DC-DCConverter
DC-DCConverter
DC-DCConverter
DC-DCConverter
POLDC-DC
POLDC-DC
POLDC-DC
POLDC-DC
POLDC-DC
12V
3.3V
100～240V
IC
1.5V，1.2V，0.8V･･･
POLDC-DC
LSI
Io
eo
1.5V，1.2V，0.8V･･･
POLDC-DC
LSI
Io
eo
1.5V，1.2V，0.8V･･･
POLDC-DC
LSI
Io
eoPOL
DC-DCLSILSI
Io
eo
Through rate and voltage
Analog and Digital Control
Analog PWM Conventional Digital PWM
Merit：Low Cost，SimpleDemerit：Weak from noise
Merit：Flexible，Advanced ControlDemerit：High Cost, Low Speed
Drive Circuit
Ei
L
RCOCO
eO
SW1
SW2
OSC
Vg
iO
LCO
Vcomp
RO( )
FPGA MPU DSP
Vref
DriveCircuit
Ei
L
eO
SW1
SW2
Vg
iO
CO
ADCADCDigitalControllerDigitalController
iL
RO( )
FPGA MPU DSP
Difficult for Advanced Control Slow Response Time
We propose new Digital controlled PWM
Common digital PWM control POLCommon analog PWM control POL
MeritsRobustness or flexible controls for versatile conditions
Programmability
Demerits ( especially large problems for point of load(POL))Delay time (Conversion time of ADC, Operation time of controller)
Cost rise
Preventing adoption of digital control for POL
Low-cost and high-speed response TRADE-OFF
Preventing incrementation of the switching frequency
Digital Control PWM
DigitalController
DigitalController
Common digital control DC-DC converter
Proposed Digital PWM Control DC-DC converter
Main Improved Points
•ADC → DAC & Analog Comparator(Cost Suppression)•Serial Operation → Parallel Operation(Delay Time Suppression)•Real Time PID Operation
Proposed System
c(m
) [de
cim
al]
0 256
Memory1：A digital staircase waveform data
V ref’[V
]
0 256
Vref +α eo
V com
p[V]
0 256
DAC：reference voltageVcomp ：comparing output voltage
on-termTon(( )( )o n
C L K
u kT kf
=
Ei
L
eO
SW1
SW2
Vg
iO
CO
RO
iL
DriveCircuit
DACVref’
PWM c(m)
Vcomp
FPGA MPUDSP
()
DigitalController
Ei
L
eO
SW1
SW2
Vg
iO
CO
RO
iL
DriveCircuit
DACDACVref’
PWM c(m)
Vcomp
FPGA MPUDSP
()
FPGA MPUDSP
()
DigitalController
ATCFrom output voltage of POL
0 t
u(k)
0 t
UpCounter
DPWM
u(k+1)
Ton(k+1)Ton(k)
Proposed System
Eo
0 time
0 time
Vref’
u(k)
0 time
UpCounter
DPWM
Vref’Eo [V]
0 time
Vcomp
u(k+1)
y2(k)
0 time
Address of Mem.2
y2(k+1)
k k+1k-1
Ton(k+1)Ton(k)
Theoretical Waveforms
memory2(PID LUT)
call
read
C(z) G(z)
H(z)
Base Signal
r(k)e(k)
Input u(k)
Output y1 (k)
y2 (k)
PID control with Look-up Table
( ) ( ) ( ) ( ) ( )( )Ref P I I Du k u K e k K n k K e k - e k - 1= + + +
uRef : a reference value of u(k)e(k) : an digitalized error value(eo and Vref )nI (k)=nI (k-1)+e(k):an integral data of e(k)KP :a proportional gainKI : an integral gainKD : an derivative gain
P I D
General digital PID control law
Experimental ResultsV:200mV/div.
V:2V/div.
e o[V
]P
WM
[V]
0
1.5
H:20μs/div.
90μs
188mV
V:200mV/div.
V:2V/div.
e o[V
]P
WM
[V]
0
1.5
H:20μs/div.
90μs
188mV
V:200mV/div.
V:2V/div.
e o[V
]P
WM
[V]
0H:20μs/div.
88μs
168mV
V:200mV/div.
V:2V/div.
e o[V
]PW
M[V
]
0
1.5
H:20μs/div.
69μs
172mV
V:200mV/div.
V:2V/div.
e o[V
]PW
M[V
]
0
1.5
H:20μs/div.
69μs
172mV
Dynamic Characteristics(0.5A→3A)
(a) KP =5
(c) KP =5，KD =4,KI =0.45
20
(b) KP =5，KD =5
The Propagation Delay ReductionC
m[d
ecim
al]
Vre
f’[V
]
Td
eo
0
0
addr
ess
[dec
imal
]
eo
0
0(a) 補正なし (b) 補正あり
Td=0
Cm
[dec
imal
]V
ref’[
V]
Td
eo
0
0
addr
ess
[dec
imal
]
eo
0
0(a) 補正なし (b) 補正あり
Td=0
Shift forward for address Information of memory1
d CLKshifting quantity T f= ×
How to Reduce?How to Reduce?
Shift to memory：shifting quantity
UpCounter Memory1 DACSystem
CLK
Vref +α
Vref ’
Eo
+-
8 8
c(m)
(a) Without compensation (b) With compensation
V:1V/div.
H:100ns/div.0
0
V:2V/div.
V com
p[V]
Cm[0
] Td=130ns
V:1V/div.
H:100ns/div.0
0
V:2V/div.
V com
p[V]
Cm[0
] Td=130ns
The Propagation Delay Reduction
19memory1
d CLKshifting quantity T f= ×
methodmethod
Shifting quantity: shifting memory address
shifting quantitiy = 130[ns] * 33.3[MHz] ≈ 4
Experimental Results
V:1V/div.
H:100ns/div.0
0
V:2V/div.
V com
p[V]
Cm[0
] Td=130ns
V:1V/div.
H:100ns/div.0
0
V:2V/div.
V com
p[V]
Cm[0
] Td=130ns
H:100ns/div.
V:1V/div.
V:2V/div.
0
0
Vco
mp[V
]C
m[0
]
H:100ns/div.
V:1V/div.
V:2V/div.
0
0
Vco
mp[V
]C
m[0
](a) Without Delay control (a) With Delay control
Input voltage Ei 2-8V
Output voltage Eo 1.5V
Output current Io 0-5A
Switching frequency fs 120kHz
Choke inductor L 17μF
Output capacitor Co 500μF
Proportional gain KP 1-5
Derivative gain KD 1,3,5
Integral gain KI 0.1-0.5
vref+α 1.7V
System CLK 33.3MHz
Experimental Conditions
FPGA
D/A Comparator
MOS-FET
Driver
PC I/F
DC-DC Converter
Prototype Circuit Experiments
H
Simulation Model (SIMPLORER)
Ei
L
eO
SW1
SW2
Vg
iO
CO
RO
iL
DriveCircuit
DACVref’
PWM c(m)
Vcomp
FPGA MPUDSP
()
DigitalController
Ei
L
eO
SW1
SW2
Vg
iO
CO
RO
iL
DriveCircuit
DACDACVref’
PWM c(m)
Vcomp
FPGA MPUDSP
()
FPGA MPUDSP
()
DigitalController
ATC
Experimental
Simulation Model
DC-DC ConverterUp Counter
DAC(DPWM)
ComparatorDown Counter
Look Up Table
DAC
H:33.3μs H:33.3μs
1.5
V:50mVeo [V]
PWM
53．
78μs
65mV
1.5
V:50mVeo [V]
PWM
50．0μs
63.8mV
(a) Without Delay control (a) With Delay control
Load Ro was changedHeavy Load 0.5Ω⇒Light Load 3Ω
Simulation Results
Conclusion
• The effectiveness of the proposed digital PWM for DC-DC converter without A/D converter is described.
• From the experimental results with prototype circuit, the total propagation delay time was suppressed to 30ns. And it was shown that the digital PID control was achieved within this time.
• We are planning to design a custom digital LSI of the control circuit with an appropriate size and cost, and to apply to high speed switching control or multi-phase control.
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