Lecture #25a

Lecture 25a, Slide 1EECS40, Fall 2004 Prof. White

Lecture #25aOUTLINE

• Interconnect modeling• Propagation delay with interconnect • Inter-wire capacitance• Coupling capacitance effects – loading, crosstalk• Transistor scaling• Silicon-on-insulator (SOI) technology• Interconnect scaling

Reading (Rabaey et al.): Sections 3.5, 3.6.

Note that he has an entire chapter (4 – The Wire) devoted to interconnects in which he elaborates on some of the slides in this lecture.

Note also pp. 229-232 – Perspective and Summary

Lecture 25a, Slide 2EECS40, Fall 2004 Prof. White

Interconnects• An interconnect is a thin-film wire that electrically

connects 2 or more components in an integrated circuit.

• Interconnects can introduce parasitic (unwanted) components of capacitance, resistance, and inductance. These “parasitics” detrimentally affect– performance (e.g. propagation delay)– power consumption– reliability

• As transistors are scaled down in size and the number of metal wiring layers increases, the impact of interconnect parasitics increases.→ Need to model interconnects, to evaluate their impact

Lecture 25a, Slide 3EECS40, Fall 2004 Prof. White

Metal lines run over thick oxide covering the substrate contribute RESISTANCE & CAPACITANCE to the output node of the driving logic gate

Interconnect Resistance & Capacitance

VDD

GND

PMOS

NMOS

Lecture 25a, Slide 4EECS40, Fall 2004 Prof. White

Wire Resistance

W

LH

WLR

WHLR swire

Lecture 25a, Slide 5EECS40, Fall 2004 Prof. White

Typical values of Rn and Rp are ~10 k, for W/L = 1

… but Rn, Rp are much lower for large transistors (used to drive long interconnects with reasonable tp)

Compare with the resistance of a 0.5m-thick Al wire:

R� = / H = (2.7 -cm) / (0.5 m) = 5.4 x 10-2 /

Example: L = 1000 m, W = 1 m

Rwire = R (L / W)

= (5.4 x 10-2 /)(1000/1) = � 54

Interconnect Resistance Example

Lecture 25a, Slide 6EECS40, Fall 2004 Prof. White

Wire Capacitance: The Parallel Plate Model

WLt

Cdi

dipp

electric field lines

tdiRelative Permittivities

single wire overa substrate:

Lecture 25a, Slide 7EECS40, Fall 2004 Prof. White

Parallel-Plate Capacitance Example

• Oxide layer is typically ~500 nm thick

• Interconnect wire width is typically ~0.5 m wide (1st level)

capacitance per unit length = 345 fF/cm = 34.5 aF/m

Example: L = 30 m

Cpp 1 fF (compare with Cn~ 2 fF)

Lecture 25a, Slide 8EECS40, Fall 2004 Prof. White

Fringing-Field Capacitance

Wire capacitance per unit length:

2HWw

)/log(2

Httwccc

di

di

di

difringeppwire

For W / tdi < 1.5, Cfringe is dominant

Lecture 25a, Slide 9EECS40, Fall 2004 Prof. White

Problem: Wire resistance and capacitance to underlying substrate is spread along the length of the wire

Modeling an Interconnect

“Distributed RC line”

We will start with a simple model…

Lecture 25a, Slide 10EECS40, Fall 2004 Prof. White

Model the wire as single capacitor and single resistor:

• Cwire is placed at the end of the interconnect adds to the gate capacitance of the load

• Rwire is placed at the logic-gate output node adds to the MOSFET equivalent resistance

Lumped RC Model

Cwire

Rwire

substrate

Lecture 25a, Slide 11EECS40, Fall 2004 Prof. White

Cascaded CMOS Inverters w/ Interconnect

Using “lumped RC” model for interconnect:

Vin

CfanoutCintrinsic

(rwire, cwire, L)

wirewiredrfanoutwiredrintrinsicdr

fanoutwirewiredrintrinsicdrD

CRRCRRCR

CCRRCR

)()(

)(

Equivalent resistance Rdr

Cintrinsic Cwire Cfanout

Rdr Rwire

Lecture 25a, Slide 12EECS40, Fall 2004 Prof. White

2

)/log(2 L

HtLWL

tWHLCR di

di

di

di

diwirewire

• Interconnect delay scales as square of L

minimize interconnect length!

• If W is large, then it does not appear in RwireCwire

• Capacitance due to fringing fields becomes more significant as W is reduced; Cwire doesn’t actually scale with W for small W

Effect of Interconnect Scaling

Lecture 25a, Slide 13EECS40, Fall 2004 Prof. White

Propagation Delay with Interconnect

wirewiredr

fanoutwiredrintrinsicdrp

CRR

CRRCRt

)38.069.0(

)(69.069.0

wirewiredr

fanoutwiredrintrinsicdr

Dp

CRR

CRRCR

t

)(69.0

)(69.0 69.0

69.0

Using the lumped-RC interconnect model:

In reality, the interconnect resistance & capacitance aredistributed along the length of the interconnect. The interconnect delay is actually less than RwireCwire:

The 0.38 factor accounts for the fact that the wire resistance and capacitance are distributed.

Lecture 25a, Slide 14EECS40, Fall 2004 Prof. White

B

Wire B has additional sidewall capacitance to neighboring wires

C

Wire C has additional capacitance to the wire above it

Interconnect Wire-to-Wire Capacitance

Wire A simply has capacitance (Cpp + Cfringe) to substrate

A

Si substrate

oxide

Lecture 25a, Slide 15EECS40, Fall 2004 Prof. White

Wiring Examples - Intel Processes

Intel 0.25µm Process (Al)5 Layers - Tungsten Vias

Source: Intel Technical Journal 3Q98Intel 0.13µm Process (Cu)

Source: Intel Technical Journal 2Q02

k=3.6

TungstenPlugs

TungstenPlugs

Advanced processes: narrow linewidths, taller wires, close spacing relatively large inter-wire capacitances

Lecture 25a, Slide 16EECS40, Fall 2004 Prof. White

Effects of Inter-Wire Capacitance

• Capacitance between closely spaced lines leads to two major effects:1. Increased capacitive loading on driven nodes

(speed loss)2. Unwanted transfer of signals from one place to

another through capacitive coupling “crosstalk”

• We will use a very simple model to estimate the magnitude of these effects. In real circuit designs, very careful analysis is necessary.

Lecture 25a, Slide 17EECS40, Fall 2004 Prof. White

Silicon substrate

SiO2

ground

1. Increase inter-wire spacing (decrease CC)

2. Decrease field-oxide thickness (decrease CC/C2)

…but this loads the driven nodes and thus decreases circuit speed.

3. Place ground lines (or VDD lines) between signal lines

Approaches to Reducing Crosstalk

Lecture 25a, Slide 18EECS40, Fall 2004 Prof. White

Transistor Scaling

• Steady advances in manufacturing technology (particularly lithography) have allowed for a steady reduction in transistor size.~13% reduction/year (0.5 every 4-6 years)

• How should transistor dimensions and supply voltage (VDD) scale together?

Average minimum L of MOSFETs vs. time

Lecture 25a, Slide 19EECS40, Fall 2004 Prof. White

Scenario #1: Constant-Field Scaling• Voltages and MOSFET dimensions are scaled

by the same factor S >1, so that the electric field remains unchanged

tox / S

VDD / SVDD

L / S

xj / Sxj

NA S Doping NA

Lecture 25a, Slide 20EECS40, Fall 2004 Prof. White

(a) MOSFET gate capacitance:

SC

StS

WSLCWLC gate

ox

oxoxgate

Impact of Constant-Field Scaling

(b) MOSFET drive current:

SI

SVV

SLS

WSCVV

LWCI DSATTDD

oxTDDoxDSAT

2

2

Circuit speed improves by S

(c) Intrinsic gate delay :

SIVC

SISVSC

IVC

DSAT

DDgate

DSAT

DDgate

DSAT

DDgate 1/

//

Lecture 25a, Slide 21EECS40, Fall 2004 Prof. White

(e) Power dissipated per device:

2SP

SV

SIVIP peakDDDSAT

DDDSATpeak

Impact of Constant-Field Scaling (cont’d)

(f) Power density:

WLP

SLSWSP

LWP peakpeakpeak

//11

2

Power consumed per function is reduced by S2

(d) Device density:LW area required per transistor

# of transistors per unit area WLS

SLSWLW

2

//11

Lecture 25a, Slide 22EECS40, Fall 2004 Prof. White

• Low VT is desirable for high ON current:

IDSAT (VDD - VT) 1 < < 2

• But high VT is needed for low OFF current:

VT Scaling?

• Low VT is desirable for high ON current:

IDSAT (VDD - VT) 1 < < 2

High VT

IOFF,high VT

IOFF,low VT

VT cannot be aggressivelyscaled down!

Low VT

VGS

log IDS

0 VDD

Lecture 25a, Slide 23EECS40, Fall 2004 Prof. White

• Since VT cannot be scaled down aggressively, the power-supply voltage (VDD) has not been scaled down in proportion to the MOSFET channel length:

Lecture 25a, Slide 24EECS40, Fall 2004 Prof. White

Scenario #2: Generalized Scaling• MOSFET dimensions are scaled by a factor S >1;

Voltages (VDD & VT) are scaled by a factor U >1

L = L / S ; W = W / S ; tox = tox / S

VDD = VDD / U

(a) MOSFET drive current:

2

22

USI

UVV

SLS

WSCVV

LWCI DSATTDD

oxTDDoxDSAT

(b) Intrinsic gate delay:

22///

SU

IVC

USIUVSC

IVC

DSAT

DDgate

DSAT

DDgate

DSAT

DDgate

Note: U is slightly smaller than S

Lecture 25a, Slide 25EECS40, Fall 2004 Prof. White

(c) Power dissipated per device:

32 USP

UV

USIVIP peakDDDSAT

DDDSATpeak

Impact of Generalized Scaling

(d) Power dissipated per unit area:

WLP

WLP

US

SLSWUSP

LWP peakpeakpeakpeak

3

3

3 //11

• Reliability (due to high E-fields) and power density are issues!

Lecture 25a, Slide 26EECS40, Fall 2004 Prof. White

VDD=0.75V0.85V

Intrinsic Gate Delay (CgateVDD / IDSAT)

Lecture 25a, Slide 27EECS40, Fall 2004 Prof. White

Silicon-on-Insulator (SOI) Technology

• Transistors are fabricated in a thin single-crystal Si layer on top of an electrically insulating layer of SiO2 Simpler device isolation savings in circuit layout area Low pn-junction & wire capacitances faster circuit operation No “body effect” Higher cost

TSOI

Lecture 25a, Slide 28EECS40, Fall 2004 Prof. White

• For global interconnects (long wires used to route VDD, GND, and voltage signals across a chip), the wire resistance dominates the resistance of the driving logic gate

(i.e. Rwire >> Rdr)

RwireCwire L2

• The length of the longest wires on a chip increases slightly (~20%) with each new technology generation. In order to minimize increases in global interconnect delay, the cross-sectional area of global interconnects has not been scaled, i.e. W and H are not scaled down for global interconnects

=> Place global interconnects in separate planes of wiring

Global Interconnects

Lecture 25a, Slide 29EECS40, Fall 2004 Prof. White

• Reduce the inter-layer dielectric permittivity– “low-k” dielectrics (r 2)

• Use more layers of wiring− average wire length is reduced− chip area is reduced

Interconnect Technology Trends

Intel 0.13µm Process (Cu)Source: Intel Technical Journal 2Q02

wire delaygate delay increases