View
224
Download
0
Category
Preview:
Citation preview
8/2/2019 Iwai IW-FNERC 2011
1/88
Future of Nano CMOSTechnology
December 26, 2011
Hiroshi Iwai,
Tokyo Institute of Technology 1
International Workshop onThe Future of Nano Electronics
Researchand Challenges Ahead
8/2/2019 Iwai IW-FNERC 2011
2/88
y gy
Founded in 1881, Promoted to Univ. 1929
Tokyo Institute of Technology
8/2/2019 Iwai IW-FNERC 2011
3/88
8/2/2019 Iwai IW-FNERC 2011
4/88
International StudentsInternational Students
Asia847
Europe 78 NorthAmerica 12
SouthAmerica 24
Oceania 5
Africa 16
Total 982
Country Students
China 403
S. Korea 130
Indonesia 64
Thailand 55
Vietnam 60
Malaysia 28
(As of May. 1,2005)
8/2/2019 Iwai IW-FNERC 2011
5/88
8/2/2019 Iwai IW-FNERC 2011
6/88
6
8/2/2019 Iwai IW-FNERC 2011
7/88
Lee De Forest
Electronic Circuits started by the
invention of vacuum tube
(Triode) in 1906
Cathode(heated) Grid
Anode(Positive bias)
Thermal electrons from cathode
controlled by grid bias
Same mechanism as that of transistor
8/2/2019 Iwai IW-FNERC 2011
8/88
t Computer Eniac: made of huge number of vacuum tubes 1ig size, huge power, short life time filament
Today's pocket PCmade ofsemiconductor hasmuch higherperformance withextremely lowpower consumption
dreamed of replacing vacuum tube with solid-state devic
8
8/2/2019 Iwai IW-FNERC 2011
9/88
J.E.LILIENFELD
J. E. LILIENFELD
DEVICES FOR CONTROLLED ELECTRIC CURRENT
Filed March 28, 1928
9
8/2/2019 Iwai IW-FNERC 2011
10/88
Electron
Semiconductor
Gate Electrode
Gate Insulator
Negative bias
Positive bias
Capacitor structure with notch
No current
Current flows
Electricfield
10
8/2/2019 Iwai IW-FNERC 2011
11/88
Source Channel Drain
0VN+-Si P-Si
N-Si
0V
1V
Negative
Source Channel Drain
N-Si
1VN+-Si P-Si
Surface Potential (Negative direction)
Gate Oxd
ChannelSource
Drain
Gate electrode
S D
G
0 bias for gate Positive bias for gate
Surface
Electron flow
Mechanism of MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
8/2/2019 Iwai IW-FNERC 2011
12/88
However, no one could realizeMOSFET operation for more than
30 years.Because of very bad interfaceproperty between the semiconductor
and gate insulatorEven Shockley!
12
8/2/2019 Iwai IW-FNERC 2011
13/88
Very bad interface property betweenthe semiconductor and gate insulator
Even Shockley!
e
Ge
GeOElectric
Shielding
CarrierScattering
InterfacialCharges
Current was several orders of magnitude sexpected
13
8/2/2019 Iwai IW-FNERC 2011
14/88
1947: 1st transistor W. Bratten,
W. ShockleyBipolar using Ge
However, they found amplification phenomenon when investigatingGe surface when putting needles.This is the 1st Transistor:Not Field Effect Transistor,But Bipolar Transistor (another mechanism)
J. Bardeen
14
8/2/2019 Iwai IW-FNERC 2011
15/88
1960: First MOSFET
by D. Kahng and M. Atalla
op View
AlGate
Source
Drain
Si
Si
Al
SiO2
Si
Si/SiO2Interface is
exceptionally15
8/2/2019 Iwai IW-FNERC 2011
16/88
1970,71: 1st generation of LSIs
1kbit DRAM Intel 1103 4bit MPU Intel 4004
16
8/2/2019 Iwai IW-FNERC 2011
17/88
17
2011
Most recent SD Card
8/2/2019 Iwai IW-FNERC 2011
18/88
18
Most Recent SD Card
128GB (Bite)= 128G X 8bit = 1024Gbit
= 1.024T(Tera)bit
1T = 1012 = Trillion
Brain Cell 10 100 BillionWorld Population 7 Billion
Stars in Galaxy 100 Billion
8/2/2019 Iwai IW-FNERC 2011
19/88
19
Most Recent SD Card
8/2/2019 Iwai IW-FNERC 2011
20/88
20
2.4cm X 3.2cm X 0.21cm
Volume 1. 6cm Weight 2g
Voltage 2.7 - 3.6V
Old Vacuum Tube 5cm X 5cm X 10cm, 100g,100W
1Tbit = 10k X10k X 10k bit
Volume = 0.5km X 0.5km X 1km
= 0.25 km3 = 0.25X1012cm3
Weight = 0.1 kgX1012 = 0.1X109ton = 100 M ton
Power = 0.1kWX1012=50 TW
Supply Capability of Tokyo Electric Power Company: 55 BW
8/2/2019 Iwai IW-FNERC 2011
21/88
So, progress of ICtechnology is most
important for the
power saving!
8/2/2019 Iwai IW-FNERC 2011
22/88
1900 1950 1960 1970 2000
Vacuum
Tube
Transistor IC LSI ULSI
10 cm cm mm 10 m 100 nm
In 100 years, the size reduced by one million times.
There have been many devices from stone age.
We have never experienced such a tremendous
reduction of devices in human history.
10-1m 10-2m 10-3m 10-5m 10
-7m
Downsizing of the componentshas been the driving force for
circuit evolution
22
i i
8/2/2019 Iwai IW-FNERC 2011
23/88
sizingeduce CapacitanceReduce switching time of MOSFETs
Increase clock frequency Increase circuit operation speedncrease number of Transistors
Parallel processing Increase circuit operation speed
us, downsizing of Si devices is
most important and critical is23
Downsizing contribute to the performance increase
in double ways
8/2/2019 Iwai IW-FNERC 2011
24/88
How far we can go
with downscaling?
Question:
8/2/2019 Iwai IW-FNERC 2011
25/88
Late 1970s 1m: SCE
arly 1980s 0.5m: S/D resistance
rly 1980s 0.25m: Direct-tunneling of gate
te 1980s 0.1m: 0.1m brick wall(variou
000 50nm: Red brick wall (various
00 10nm: Fundamental?
Period Expected Causelimit(size)
Many people wanted to say aboutthe limit.
Past predictions were notcorrect!!
25
Hi t i ll di ti f th li it f
8/2/2019 Iwai IW-FNERC 2011
26/88
Historically, many predictions of the limit ofdownsizing.VLSI text book written 1979 predict that
0.25 micro-meter would be the limitbecause of direct-tunneling currentthrough the very thin-gate oxide.
8/2/2019 Iwai IW-FNERC 2011
27/88
VLSI textbook
Finally, there appears to be afundamental limit 10 ofapproximately quarter micronchannel length, where certainphysical effects such as thetunneling through the gateoxide ..... begin to make thedevices of smaller dimension
unworkable. 27
8/2/2019 Iwai IW-FNERC 2011
28/88
Potential Barrier
Wave function
irect-tunneling effect
28
G
S
D
Gate Oxide
Gate OxideGate
Electrode
Si
Substrate
Direct tunneling leakage
current start to flow whenthe thickness is 3 nm.
Direct tunneling
current
Lg
8/2/2019 Iwai IW-FNERC 2011
29/88
Direct tunneling leakagefound to be OK! In 1994!
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
1.6
1.2
0.8
0.4
0.0
-0.4
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.4
0.3
0.2
0.1
0.0
-0.1
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.08
0.06
0.04
0.02
0.00
-0.02
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.03
0.02
0.01
0.00
0.01
-0.4
0.0 0.5 1.0 1.5
Vd (V)
Id(mA/
m)
Lg = 10 m Lg = 5 m Lg = 1.0 m Lg = 0.1m
Gateelectrode
Sisubstrate
Gateoxide
MOSFETs with 1.5 nm gate oxide
29
G
S D
Lg
8/2/2019 Iwai IW-FNERC 2011
30/88
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
1.6
1.2
0.8
0.4
0.0
-0.4
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
1.6
1.2
0.8
0.4
0.0
-0.4
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.4
0.3
0.2
0.1
0.0
-0.1
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.4
0.3
0.2
0.1
0.0
-0.1
0.0 0.5 1.0 1.5
Vd (V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.08
0.06
0.04
0.02
0.00
-0.02
0.0 0.5 1.0 1.5
Vd(V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.08
0.06
0.04
0.02
0.00
-0.02
0.0 0.5 1.0 1.5
Vd(V)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.03
0.02
0.01
0.00
0.01
-0.4
0.0 0.5 1.0 1.5
Vd(V)
Id(mA/
m)
Vg = 2.0V
1.5 V
1.0 V
0.5 V
0.0 V
0.03
0.02
0.01
0.00
0.01
-0.4
0.0 0.5 1.0 1.5
Vd(V)
Id(mA/
m)
Lg = 10 m Lg = 5 m Lg = 1.0 m Lg = 0.1m
Gate leakage: Ig Gate Area Gate length (Lg)
Id
Drain current: Id 1/Gate length (Lg)
Lg small,
Then, Ig
small, Id
large, Thus, Ig/Id
very small
30
G
S D
Ig Id
8/2/2019 Iwai IW-FNERC 2011
31/88
Never Give Up!
There would be a solution!
Think, Think, and Think!
Or, Wait the time!
Some one will think for you
No one knows future!
Do not believe a text book statement, blindly!
31
8/2/2019 Iwai IW-FNERC 2011
32/88
Qi Xinag, ECS 2004, AM32
8/2/2019 Iwai IW-FNERC 2011
33/88
what is the limitation
for downsizing?
So,
8/2/2019 Iwai IW-FNERC 2011
34/88
Source Channel Drain
N+-Si P-Si
N-Si
0V
1V
Negative
Surface Potential (Negative direction)
Gate Oxd
Channel
Source
Drain
Gate electrode
0 bias for gate
Surface
34
Tunneling
3nm
@Vg=0V,
Transistor cannotbe switched off
8/2/2019 Iwai IW-FNERC 2011
35/88
Tunnelingdistance
3 nm Lg = Sub-3nm?
Below this,no one knows future!
Prediction now!
Limitation for MOSFET operation
H f f
8/2/2019 Iwai IW-FNERC 2011
36/88
How far can we go forproduction?
0m 8m 6m 4m 3m 2m 1.2m 0.8m 0.5m0.35m 0.25m 180nm 130nm 90nm 65nm 45nm 32nm
1970
(28nm) 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm
Past 0.7 times per 3 years NowIn 40 years: 18 generations,Size 1/300, Area 1/100,000
Future
ver oxide thickness is now around 1n
8/2/2019 Iwai IW-FNERC 2011
37/88
By Robert Chau, IWGI 20
ver, oxide thickness is now around 1n
.8 nm: 2 mono-layer thickness!!
37
8/2/2019 Iwai IW-FNERC 2011
38/88
So, we are now
Facing the limi
of downsizing?38
h i l i K Di l i C
8/2/2019 Iwai IW-FNERC 2011
39/88
here is a solution!o use high-k dielectrics
Thin gate SiO2Thick gate high-k dielectri
Almost the sameelectric characteristics
owever, very difficult and big challenge!
Remember MOSFET had not been realize
without Si/SiO2!
K: Dielectric Constan
Physical
ly thick
39
K=4K=20
Sameelectric
al
5 nm gate length CMOS
8/2/2019 Iwai IW-FNERC 2011
40/88
5 nm gate length CMOS
H. Wakabayashiet.al, NEC
IEDM, 2003
ngth of 18 Si atoms
Is a Real Nano Device!!
5nm
40
8/2/2019 Iwai IW-FNERC 2011
41/88
how far we can go
with downscaling?
So, again,
H f f
8/2/2019 Iwai IW-FNERC 2011
42/88
How far can we go forproduction?
0m 8m 6m 4m 3m 2m 1.2m 0.8m 0.5m0.35m 0.25m 180nm 130nm 90nm 65nm 45nm 32nm
1970
(28nm) 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm
Past 0.7 times per 3 years NowIn 40 years: 18 generations,Size 1/300, Area 1/100,000
Future
At least 4,5 generations to 8nm
Hopefully 8 generations to 3nm
8/2/2019 Iwai IW-FNERC 2011
43/88
43
Vg
Id
Vth
(Threshold Voltage)
Vg=0V
Subthreshould
Leakage Current
Subtheshold leakage current of MOSFET
ONOFF
Ion
Ioff
Subthreshold
region
Log scale Id plotVth cannot be decreased anymore
8/2/2019 Iwai IW-FNERC 2011
44/88
4444
Vg (V)
10-7A
Vg = 0V
Vth = 300mVVth
= 100mV
Vth
down-scaling
Subthreshold slope (SS)
= (Ln10)(kT/q)(Cox+CD+Cit)/Cox> ~ 60 mV/decade at RT
SS value:
Constant and does not become small with down-scaling
10-3A
10-4A
10-5A
Vdd=0.5V Vdd=1.5V
Ion
Ioff
Ioff
10-6A
10-8A
10-9A
10-10ALogIdperunitgatewidth(
=1
m)
Vdd
down-scaling
Log scale Id plot
Ioff increaseswith 3.3 decades
(300 100)mV/(60mv/dec)
= 3.3 dec
Vth cannot be decreased anymore
Vth: 300mV100mV
significant Ioff increase
8/2/2019 Iwai IW-FNERC 2011
45/88
45
Vg
Id
Vth
(Threshold Voltage)
Vg=0V
Subthreshould
Leakage Current
Subtheshold leakage current of MOSFET
Subthreshold Current
Is OK at Single Tr. level
But not OKFor Billions of Trs.
ONOFF
Ion
Ioff
Subthreshold
region
The limit is deferent depending on application
8/2/2019 Iwai IW-FNERC 2011
46/88
46
Subthreshold Leakage (A/m)
OperationFrequency
(a.u.)
e)
100
10
1
Source: 2007 ITRS Winter Public Conf.
The limit is deferent depending on application
Th d li f MOSFET i till ibl f t
8/2/2019 Iwai IW-FNERC 2011
47/88
The down scaling of MOSFETs is still possible for at
least another 10 years!
1. Thinning of high-k gate oxide thickness
beyond 0.5 nm
2. Metal S/D
3. Wire channel
3 important technological items for down scaling.
New structures
New materials
8/2/2019 Iwai IW-FNERC 2011
48/88
1. High-k
beyond 0.5 nm
Choice of High-k elements for oxide
8/2/2019 Iwai IW-FNERC 2011
49/88
R. Hauser, IEDM Short Course, 1999
Hubbard and Schlom, J Mater Res 11 2757 (1996)
Gas or liquid
at 1000 K
H Radio active He
Li
Be
B C N O F Ne
Na
Mg Al Si P S Cl Ar
KCaSc Ti V Cr MnFc Co Ni Cu Zn Ga Ge As Se Br Kr
Rh SrYZr NbMo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe
Cs BaHf
Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
Fr Ra Rf HaSg Ns Hs Mt
LaCePrNdPmSmEuGdTbDyHoErTmYLu
Ac Th Pa U NpPu AmCmBk Cf Es FmMdNo Lr
Candidates
Na Al Si P S Cl Ar
K Sc Ti V Cr MnFc Co Ni Cu Zn Ga Ge As Se Br Kr
Ac Th Pa U NpPu AmCmBk Cf Es FmMdNo Lr
Unstable at Si interfaceSi + MOX M + SiO2
Si + MOX MSiX + SiO2Si + MOX M + MSiXOY
Choice of High-k elements for oxide
HfO2 based dielectrics
are selected as the
first generationmaterials, because of
their merit in
1) band-offset,
2) dielectric constant
3) thermal stability
La2O3 based
dielectrics are thought
to be the next
generation materials,
which may not need a
thicker interfacial
layer
49
Conduction band offset vs Dielectric Consta
8/2/2019 Iwai IW-FNERC 2011
50/88
0 1 0 2 0 3 0 4 0 5 0
D i e l e c t r i c C o n s t a n t
4
2
0
- 2
- 4
- 6
S i O2
B
a
n
d
D
is
c
o
n
tin
u
ity
[e
V
]
S i
XPS measurement by Prof. T. Hattori, INFOS 2003
Conduction band offset vs. Dielectric Consta
Bandoffset
Oxide
Leakage Current by Tunneling
50
igh-k gate insulator MOSFETs for Intel: EOT=1nm
8/2/2019 Iwai IW-FNERC 2011
51/88
51
PMOS
igh-k gate insulator MOSFETs for Intel: EOT=1nm
HfO2 based high-k
(Sc MetalF th t 45
8/2/2019 Iwai IW-FNERC 2011
52/88
52Year
P
owerperM
OSFET(P)
P
L
g 3
Scaling)
EOT Limit
0.7~0.8 nm
EOT=0.5nm
Today
EOT=1.0nm
Now
45nm node
One order of Magnitude
Si
HfO2
Metal
SiO2/SiON
Si
High-k
Metal
Direct Contact
Of high-k and Si
Si
Metal
SiO2/SiON
0.5 0.7nm
Introduction of High-k
Still SiO2 or SiON
Is used at Si interface
For the past 45 years
SiO2 and SiON
For gate insulator
EOT can be reduced further beyond 0.5 nm by using direct contact to Si
By choosing appropriate materials and processes.
8/2/2019 Iwai IW-FNERC 2011
53/88
SiO IL th t HfO /Si I t f
8/2/2019 Iwai IW-FNERC 2011
54/88
54
1837184018431846
Binding energy (eV)
Intensity(a.u
)
Si sub.
Hf SilicateSiO2
500 oC
1837184018431846
Binding energy (eV)
Intensity(a.u
)
Si sub.
Hf SilicateSiO2
500 oC
SiOx-IL
HfO2
W
1 nm
k=4
k=16
SiOx-IL growth at HfO2/Si Interface
HfO2 + Si + O2 HfO2 + Si + 2O*HfO2+SiO2
Phase separator
SiOx-IL is formed after annealing
Oxygen control is required for optimizing the reaction
Oxygen supplied from W gate electrode
XPS Si1s spectrum
D.J.Lichtenwalner, Tans. ECS 11, 319
TEM image 500 oC 30min
H. Shimizu, JJAP, 44, pp. 6131
La Silicate Reaction at La O /Si
8/2/2019 Iwai IW-FNERC 2011
55/88
55
La-Silicate Reaction at La2O3/Si
La2
O3
La-silicate
W
500 oC, 30 min
1 nm
k=8~14
k=23
1837184018431846
Binding energy (eV)
Intensity
(a.u
)
as depo.
300
o
C
La-silicate
Si sub.
500 oC
1837184018431846
Binding energy (eV)
Intensity
(a.u
)
as depo.
300
o
C
La-silicate
Si sub.
500 oC
La2O3 + Si + nO2 La2SiO5, La2Si2O7,
La9.33Si6O26, La10(SiO4)6O3,
etc.La2O3 can achieve direct contact of high-k/Si
XPS Si1s spectra TEM image
Direct contact high-k/Si is possible
8/2/2019 Iwai IW-FNERC 2011
56/88
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
0 0.5 1 1.5 2 2.5 3
EOT ( nm )
Currentdensity(A/cm
2)
Al2O3
HfAlO(N)
HfO2HfSiO(N)
HfTaO
La2O3
Nd2O3
Pr2O3
PrSiO
PrTiO
SiON/SiN
Sm2O3
SrTiO3
Ta2O5
TiO2
ZrO2(N)
ZrSiO
ZrAlO(N)
Gate Leakage vs EOT, (Vg=|1|V)
La2O3
HfO2
56
L O t 300oC k b 0 4 EOT MOSFET
8/2/2019 Iwai IW-FNERC 2011
57/88
57
0.0E+00
5.0E-04
1.0E-03
1.5E-03
2.0E-03
2.5E-03
3.0E-03
3.5E-03
0 0.2 0.4 0.6 0.8 1
Vg=0V
Vg=0.2V
Vg=0.4V
Vg=0.6V
Vg=0.8V
Vg=1.0V
Vg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0V
Vg=0.2V
Vg=0.4V
Vg=0.6V
Vg=0.8V
Vg=1.0V
Vg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0V
Vg=0.2V
Vg=0.4V
Vg=0.6V
Vg=0.8V
Vg=1.0V
Vg=1.2VId(V)
W/L = 50m /2.5m
Vd (V) Vd (V) Vd (V)
EOT=0.37nm
Vth=-0.04VVth=-0.05VVth=-0.06V
EOT=0.37nm EOT=0.40nm EOT=0.48nm
W/L = 50m /2.5m W/L = 50m /2.5m
0.48
0.37nm Increase of Id at 30%
La2O3 at 300oC process make sub-0.4 nm EOT MOSFET
However high-temperature anneal is necessary
8/2/2019 Iwai IW-FNERC 2011
58/88
58
2
1.5
1
0.5
0
Capacitance[F/cm
2]
-1 -0.5 0 0.5 1Gate Voltage [V]
10kHz100kHz1MHz
20 x 20m2
1.5
1
0.5
0
Capacitanc
e[F/cm
2]
-1.5 -1 -0.5 0 0.5Gate Voltage [V]
20 x 20m2
10kHz100kHz1MHz
2
1.5
1
0.5
0
Capacitanc
e[F/cm
2]
-1.5 -1 -0.5 0 0.5Gate Voltage [V]
20 x 20m2
10kHz100kHz1MHz
FGA500oC 30min FGA700oC 30min FGA800oC 30min
A fairly nice La-silicate/Si interface can be obtained
with high temperature annealing. (800oC)
However, high temperature anneal is necessary
for the good interfacial property
Physical mechanisms for small DitPhysical mechanisms for small Dit
8/2/2019 Iwai IW-FNERC 2011
59/88
59
silicate-reaction-formedfresh interface
metal
Si sub.
metal
Si sub.
La2O3 La-silicateSi Si
Fresh interface with
silicate reaction
J. S. Jur, et al., Appl. Phys. Lett.,Vol. 87, No. 10, (2007) p. 102908
stress relaxation at interfaceby glass type structure of La
silicate.
La atom
La-O-Si bonding
Si sub.
SiO4tetrahedronnetwork
FGA800oC is necessary to
reduce the interfacial stress
S. D. Kosowsky, et al., Appl. Phys. Lett.,Vol. 70, No. 23, (1997) pp. 3119
Physical mechanisms for small DitPhysical mechanisms for small Dit
8/2/2019 Iwai IW-FNERC 2011
60/88
60
500
400
300
200
100
0
ElectronMo
bility[cm
2/Vsec]
10.80.60.40.20Eeff [MV/cm]
FGA 800oC
FGA 700oC
FGA 500oC
Universal
Nsub = 3 x 1016
cm-3
T = 300K
EOT~1.3nm
Pulse input
10-9
10-8
10-7
10-6
Chargepum
pingcurrent[A]
10
4
10
5
10
6
Frequency [Hz]
Dit = 2 x 1012 [cm-2/eV]
Dit = 5 x 1011 [cm-2/eV]
Dit = 1.6 x 1011 [cm-2/eV]
500oC
700oC
800oC
A small Dit of1.6x1011 cm-2/eV, results in better
electron mobility.
EOT growth suppression by Si coverage
8/2/2019 Iwai IW-FNERC 2011
61/88
61
4
3
2
1
0Gate-ChannelC
apacitance[F/cm
2]
10.50-0.5-1
Gate Voltage [V]
at 1MHz
L / W = 20 / 20m
FGA 800oC 30min
Si sub.
La-silicate
W
Si sub.
La-silicate
W
TiN
Si sub.
La-silicateW
TiN
Si
EOT=1.02nm
EOT=1.63nm
EOT=0.71nm
10-12
10-11
10-10
10-9
10
-8
10-7
10-6
10-5
10-4
10-3
Drain
Current[A]
-1 -0.5 0 0.5 1
Vg - Vth [V]
L / W = 2.5 / 50m
Vds = 0.05V
EOT = 0.71nmEOT = 1.02nmEOT = 1.63nm
65~70mV/dec
Increasing EOT caused by high temperature annealing can
be dramatically suppressed by Silicon masked stacks
g pp y g
8/2/2019 Iwai IW-FNERC 2011
62/88
62
No interfacial layer can be confirmed with Si/TiN/W
MIPSW TiN/W
Kav ~ 8 Kav ~ 12 Kav ~ 16
Si 2nm2nm2nm
HK
MG
La2O3
Si/TiN/W
MOSFET ith EOT f 0 62
8/2/2019 Iwai IW-FNERC 2011
63/88
63
4
3
2
1
0Gate-ChannelCapacitance[F/c
m2]
10.50-0.5
Gate Voltage [V]
FGA 800oC 30min
L / W = 10 / 10m
10kHz100kHz1MHz
200
150
100
50
0
ElectronM
obility[cm
2/Vsec]
1.510.50
Eeff [MV/cm]
L / W = 10 / 10m
Nsub = 3 x 1016
cm-3T = 300K
EOT=0.62nmEOT=0.62nm
No frequency
dispersion
EOT of 0.62nm and 155 cm2/Vsec at 1MV/cm can be achieved
nMOSFET with EOT of 0.62nm
8/2/2019 Iwai IW-FNERC 2011
64/88
64
10-2
10-1
100
101
102
103
104
Jg
atV
g=1V[A/cm
2]
0.80.750.70.650.60.550.5
EOT [nm]
A = 10 x 10m2
ITRS requirements
MIPS Stacks
300
250
200
150
100
50
0
ElectronM
obility[cm
2/Vsec]
1.31.21.110.90.80.70.60.5
EOT [nm]
at 1MV/cmT = 300KThis work
(MIPS Stacks)
Open : Hf-based oxides
T. Ando et al., IEDM2009
Gate leakage is two orders
of magnitude lower than
that of ITRS
Electron mobility is comparable
to record mobility with Hf-based
oxides
Benchmark of La-silicate dielectrics
8/2/2019 Iwai IW-FNERC 2011
65/88
Metal (Silicide) S/D
8/2/2019 Iwai IW-FNERC 2011
66/88
Extreme scaling in MOSFET Lphy
DopantCo
nc.
Gate
MetalC
onc.
Gate
Lphy = Leff- Atomically abrupt junction
- Lowering S/D resistances
- Low temperature process for S/D
Metal Schottky S/D junctions
- Dopant abruptness at S/D
- Vt and ION variation
- GIDL
Schottky Barrier FET is a strong
candidate for extremely scaled
MOSFETS DChannel
S DChannel
n+-Sin+-Si
Metal
Silicide
Metal
Silicide
8/2/2019 Iwai IW-FNERC 2011
67/88
67
Surface or interface control
Diffusion species:
metal atom (Ni, Co) Rough interface at silicide/Si
- Excess silicide formation
- Different Bn presented
at interface
- Process temperature
dependent composition
Diffusion species: Si atom (Ti)
Surface roughness increases- Line dependent
resistivity change
Line widthof 0.1 m
H. Iwai et al., Microelectron. Eng., 60, 157 (2002).
Top view
Epitaxial NiSi2
O. Nakatsuka et al., Microelectron. Eng.,
83, 2272 (2006).
Si(001) sub.
Annealing: 650 oC
8/2/2019 Iwai IW-FNERC 2011
68/88
68
Unwanted leakage current
- Atomically flat interface with smooth surface- Suppressed leakage current
- Stability of silicide phase and interface
in a wide process temperature
Specification for metal silicide S/D
- Edge leakage current at periphery
- Generation current due to
defects in substrate
Length of a contact side (m)Currentdensity(A/c
m2)
10-3
10-2
10 102
Vapp = -0.2V Bn = ~0.57 eV
Variable leakage current
in smaller contactNi silicide/Si diodes
Annealing: 500 oC
8/2/2019 Iwai IW-FNERC 2011
69/88
69
Si substrate
Ni-silicide
Si substrate
Si substrate
Ni-silicide
Si substrate
Deposition
of Ni film
Depositionfrom
NiSi2 source Annealing Flat interface
Rough
interface
No Si substrateconsumption
Annealing
Deposition of Ni-Si mixed films from NiSi2 source
- No consumption of Si atoms from substrate
- No structural size effect in silicidation process
- Stable in a wide process temperature range
SEM views of silicide/Si interfaces
8/2/2019 Iwai IW-FNERC 2011
70/88
70
NiSi2 source
Ni source (50nm)
rough
rough
roughflat
flat
flat
STI500nm
NiSi2 source (50nm)
500nm
500nm
STI
500nmSTI STI
500nmSTI
500nmSTI
600oC , 1min
700oC , 1min
800oC , 1min
- Rough interfaces
- Consumed Si substrate
- Thickness increase ~100 nm
Ni source
- Atomically flat interfaces
- No Si consumption
- Temperature-independent
Si substrate
Ni-silicide
Ni source
Ni-silicide
Si substrate
NiSi2 source
STI
8/2/2019 Iwai IW-FNERC 2011
71/88
71
Ideal characteristics (n = 1.00, suppressed leakage current)
Suppressed reverse leakage current
- Flat interface and No Si substrate consumption
- No defects in Si substrate
Ni
NiSi2
-0.8 -0.6 0.0 0.2
Diode voltage (V)
-0.4 -0.210-5
10-4
10-3
10-2
Diode
current(A/cm
2)
1.001.08
n
0.659NiSi2
0.676Ni
Bn (eV)Source
1.001.08
n
0.659NiSi2
0.676Ni
Bn (eV)Source
Generation current
RTA500oC, 1min
Schottky diode structures
Leakage current
Al contact
Ni source
Al contact
NiSi2 source
Si substrate
Si substrate
NiSi2 source Applied Voltage (V)
Curren
tdensity(A/cm2)
8/2/2019 Iwai IW-FNERC 2011
72/88
Wire channel
S i f bth h ld l k
8/2/2019 Iwai IW-FNERC 2011
73/88
73
1V0V
0V
S
0V
0V V 1V
1V0V
0V
0V
0VS D
G
G
G
Suppression of subthreshold leakage
by surrounding gate structure
Planar Surrounding gate
B f ff l k t l
8/2/2019 Iwai IW-FNERC 2011
74/88
Planar Nanowire
Source Drain
Gate
Wdep
1
Leakage current
S D
Planar FETFin FET
Nanowire FET
Because of off-leakage control,
V1
V1V1
V1
V1
S
D
G
G
8/2/2019 Iwai IW-FNERC 2011
75/88
75
Fin Tri-gate -gate All-around
G G G
G
G
Nanowire structures in a wide meaning
Si nanowire FET as a strong candidate
1S D
8/2/2019 Iwai IW-FNERC 2011
76/88
76
1. Compatibility with
current CMOS process
2. Good controllability of IOFF
3. High drive current
1D ballistic
conduction
Multi quantum
Channel High integration
of wires
k
E
Quantum channel
Quantum channelQuantum channel
Quantum channelk
E
Quantum channel
Quantum channelQuantum channel
Quantum channel
Off
Gate:OFF
Drain Source
cut-off
Gate: OFF
drainsource
Off
Gate:OFF
Drain Source
cut-off
Gate: OFF
drainsource
Wdep
Leakage current
S D
Increase the Number of quantum channels
8/2/2019 Iwai IW-FNERC 2011
77/88
Increase the Number of quantum channels
Energy band of Bulk Si
Eg
By Prof. Shiraishi of Tsukuba univ.
Energy band of 3 x 3 Si wire
4 channels can be used
Eg
77
Device fabrication
8/2/2019 Iwai IW-FNERC 2011
78/88
Device fabrication
Si/Si0.8Ge0.2superlattice
epitaxy on SOI
Anisotropic
etching
of these layers
Isotropic
etching
of SiGe
Gate depositions S/D implantation
Spacer formationActivation anneal
Salicidation
BOX
SiSiGe
Si
SiGeSi
SiGe
SiN
BOX BOX
BOX
Gate
BOX
Gate
Gate etchingStandard
Back-End
of-LineProcess
HfO2 (3nm)
TiN (10nm)Poly-Si (200nm)
C. Dupre et al.,
IEDM Tech. Dig., p.749, 2008
7
SiN HM
Process Details :
The NW diameteris controllable
down to 5 nm
by self limited oxidation.
( )
3D stacked Si NWs with Hi k/MG
8/2/2019 Iwai IW-FNERC 2011
79/88
Cross-section
50nm
SiN HM
Wire direction :
50 NWs in parallel
3 levels vertically-stackedTotal array of 150 wires
EOT ~2.6 nm
NWs
8
3D-stacked Si NWs with Hi-k/MG
BOX
500 nm
Source
Drain
Gate
Top view
C. Dupre et al.,
IEDM Tech. Dig., p.749, 2008
SiNW FET Fabrication
8/2/2019 Iwai IW-FNERC 2011
80/88
Sacrificial Oxidation
SiN sidewall support formation
Ni SALISIDE Process (Ni 9nm / TiN 10nm)
S/D & Fin Patterning
Gate Oxidation & Poly-Si Deposition
Gate Lithography & RIE Etching
Gate Sidewall Formation
30nm
30nm
30nm
Oixde etch back
Standard recipe for gate stack formation
Backend
Recent results to be presented by ESSDERC 2010 next week in Sevile
8/2/2019 Iwai IW-FNERC 2011
81/88
Lg=65nm, Tox=3nm
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.0
0.E+00
1.E-05
2.E-05
3.E-05
4.E-05
5.E-05
6.E-05
7.E-05
-1.0 -0.5 0.0 0.5 1.0
0
10
20
30
40
50
60
70
DrainCu
rrent(A)
Drain Voltage (V)
Vg-Vth=1.0 V
Vg-Vth= -1.0 V
0.8 V
0.6 V
0.4 V
0.2 V
(a)
10
-12
Gate Voltage (V)
pFET nFET
(b)
10-11
10-10
10-910-8
10-7
10-6
10-5
10-4
10-3
DrainC
urrent(A)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.0
0.E+00
1.E-05
2.E-05
3.E-05
4.E-05
5.E-05
6.E-05
7.E-05
-1.0 -0.5 0.0 0.5 1.0
0
10
20
30
40
50
60
70
DrainCu
rrent(A)
Drain Voltage (V)
Vg-Vth=1.0 V
Vg-Vth= -1.0 V
0.8 V
0.6 V
0.4 V
0.2 V
(a)
10
-12
Gate Voltage (V)
pFET nFET
(b)
10-11
10-10
10-910-8
10-7
10-6
10-5
10-4
10-3
DrainC
urrent(A)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
On/Off>106 60uA/wire
Wire cross-section: 20 nm X 10 nm
Bench Mark
8/2/2019 Iwai IW-FNERC 2011
82/88
0
10
20
30
40
50
60
70
Gate Length (nm)
ION
(A/
wire)
nMOS
pMOS
(5)
(5)
(10)
(10)
(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
0
10
20
30
40
50
60
70
Gate Length (nm)
ION
(A/
wire)
nMOS
pMOS
0
10
20
30
40
50
60
70
Gate Length (nm)
ION
(A/
wire)
nMOS
pMOS
(5)
(5)
(10)
(10)
(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
(12)
0
10
20
30
40
50
60
70
Gate Length (nm)
ION
(A/
wire)
nMOS
pMOS
(5)
(5)
(10)
(10)
(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
0
10
20
30
40
50
60
70
Gate Length (nm)
ION
(A/
wire)
nMOS
pMOS
0
10
20
30
40
50
60
70
Gate Length (nm)
ION
(A/
wire)
nMOS
pMOS
(5)
(5)
(10)
(10)
(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
0
10
20
30
40
50
60
70
Gate Length (nm)
ION
(A/
wire)
nMOS
pMOS
(5)
(5)
(10)
(10)
(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
0
10
20
30
40
50
60
70
Gate Length (nm)
ION
(A/
wire)
nMOS
pMOS
0
10
20
30
40
50
60
70
Gate Length (nm)
ION
(A/
wire)
nMOS
pMOS
(5)
(5)
(10)
(10)
(12)
(12x19)
(12)
(12x19)
(13x20)
(9x14)(10)
(10)
(10)
(8)
(8)
(16)
(13)
(34)
(3)(3)
(30)
(19)
VDD: 1.0~1.5 V
(12)
(10x20)102A
Our Work
Bench Mark
IIONON/I/IOFFOFF Bench markBench mark
8/2/2019 Iwai IW-FNERC 2011
83/88
Y. Jiang, VLSI 2008, p.34H.-S. Wong, VLSI 2009, p.92
S. Bangsaruntip, IEDM 2009, p.297
C. Dupre, IEDM 2008, p. 749
S.D.Suk, IEDM 2005, p.735
G.Bidel, VLSI 2009, p.240
Si nanowireFET
Planer FET
S. Kamiyama, IEDM 2009, p. 431P. Packan, IEDM 2009, p.659
1.2 1.3V
1.0 1.1V
Lg=500 65nm
Thiswork
8/2/2019 Iwai IW-FNERC 2011
84/88
8/2/2019 Iwai IW-FNERC 2011
85/88
Distance from SiNW Surface (nm)
6
5
4
3
2
1
0
(x019cm-3)Electron Density
Edge portion
Flat portion
Primitive estimation !
8/2/2019 Iwai IW-FNERC 2011
86/88
0
2000
4000
6000
8000
10000
12000
2008 2010 2012 2014 2016 2018 2020 2022 2024 2026
Year
ION
(A
/m)
SiNW (12nm 19nm)
MGFD
bulk
IONLg-0.5 Tox
-1(20)
(11)
(33)
(15)
(26)
ION
1m
S/D
pMOS
EOT
Compact model
Small EOT for high-k
P-MOS improvement
Low S/D resistance
# of wires /1m
Assumption
ITRS
Na
nowire
Primitive estimation !
Our roadmap for R &DSource: H. Iwai, IWJT 2008
Current Issues
Si Nanowire
8/2/2019 Iwai IW-FNERC 2011
87/88
Source: H. Iwai, IWJT 2008
III-V & Ge Nanowire
High-k gate insulator
Wire formation technique
CNT:
Width and Chirality controlGrowth and integration of CNT
Graphene:
Graphene formation technique
Suppression of off-current
Very small bandgap or
no bandgap (semi-metal)
Control of ribbon edge structure
which affects bandgap
Chirality determines conduction
types: metal or semiconductor
87
Control of wire surface property
Compact I-V model
Source Drain contact
Optimization of wire diameter
8/2/2019 Iwai IW-FNERC 2011
88/88
Recommended