IE1204 Digital Design: L3: CMOS circuits, Implementation ......Transmission gate (pass gate) A Q E A...

IE1204 Digital Design:

L3: CMOS circuits,Implementation Technologies

Masoumeh (Azin) Ebrahimi (masebr@kth.se)

Elena Dubrova(dubrova@kth.se)KTH / ICT / ES

Transistor - a switch with no movingparts

Schematic diagram ofthe SiGe transistor

Source Drain

IE1204 Digital Design, Autumn2015 2

• CMOS transistors are easy to manufacture

• CMOS transistors are made from ordinary sand=> cheap raw materials

• A transistor is easy to get to work as a switch

Why CMOS?

PMOS and NMOS

PMOS NMOS

• A PMOS transistor (p-channel MOS) isconducting (switch isclosed) if gate voltage (VGS)is close to VSS.

• An NMOS (n-channel) isconducting (switch isclosed) if gate voltage (VGS)is close to VDD.

Source Source

The structure of a CMOS circuit

IE1204 Digital Design, Autumn2015

Pull-down network

Pull-up network

PMOS makes theoutput ”1”

NMOS makes theoutput ”0”

PMOS and NMOS Transistors

”Pull Up”

”Pull Down”

CMOS inverter

(A) Circuit

(B) Truth table and transistor states

T2T1 T2

• CMOS circuits are composed of bothPMOS and NMOS transistors

• CMOS stands for Complementary MOS

• Area: AInverter= 2 Transistors

CMOS inverter

(A) Circuit

T2T1 T2

• Area: AInverter= 2 Transistors0

CMOS inverter

(A) Circuit

T2T1 T2

• Area: AInverter= 2 Transistors1

CMOS inverter voltage transfercharacteristic

VOH = VDD

VT VIL VIH VDD-VT

45 degree tilt

Power Supply 5.0V 3.3V 1.8VVOH 5.0 3.3 1,8VIH 2,9 1,9 1.0VIL 2,1 1,4 0.8VOL 0.0 0.0 0.0

VOL = 0 V

”1”

”0”

VT = 0.2VDD

Low Noise Margin: NML= VIL-VOL

High Noise Margin NMH= VOH-VIH

One point is unstable!• CMOS circuit has a very stabletransfer function

• At Vinto= VDD/2 there is anunstable point, then both T1 and T2are conducting

• If a circuit temporarily stuck inthis mode, it enters a state calledmetastability

• If this state lasts for a long time,the transistors in the circuit may bedamaged by the high current

Metastability will be discussedin later lectures

Unstable point

CMOS–Dynamic power consumption!

Classical CMOS has only losses exactly at the vidswitching point. The Power dissipation PF is proportionalto the clock-frequency!

VoltageSupplyVencyClockfrequf

lossesPowerPVfP

DDCF2×µ”1” ”0”

”1”® ”0”

”1”¬ ”0”

NAND gate

VA VB VOH

VSS(0) VSS(0) VDD(1)VSS(0) VDD(1) VDD(1)VDD(1) VSS(0) VDD(1)VDD(1) VDD(1) VSS(0)

Area: ANAND= 4 Transistors

NAND gate

VA VB VOH

VSS(0) VSS(0) VDD(1)0

NAND gate

VA VB VOH

VSS(0) VSS(0) VDD(1)VSS(0) VDD(1) VDD(1)

NAND gate

offVA VB VOH

VSS(0) VSS(0) VDD(1)VSS(0) VDD(1) VDD(1)VDD(1) VSS(0) VDD(1)

NAND gate

VA VB VOH

VSS(0) VSS(0) VDD(1)VSS(0) VDD(1) VDD(1)VDD(1) VSS(0) VDD(1)VDD(1) VDD(1) VSS(0)

NOR gate

VA VB VOH

VSS(0) VSS(0) VDD(1)VSS(0) VDD(1) VSS(0)VDD(1) VSS(0) VSS(0)VDD(1) VDD(1) VSS(0)

Area: ANOR= 4 Transistors

NOR gate

VA VB VOH

VSS(0) VSS(0) VDD(1)0

offoff

NOR gate

VA VB VOH

VSS(0) VSS(0) VDD(1)VSS(0) VDD(1) VSS(0)

NOR gate

VA VB VOH

VSS(0) VSS(0) VDD(1)VSS(0) VDD(1) VSS(0)VDD(1) VSS(0) VSS(0)

NOR gate

VA VB VOH

VSS(0) VSS(0) VDD(1)VSS(0) VDD(1) VSS(0)VDD(1) VSS(0) VSS(0)VDD(1) VDD(1) VSS(0)

Group work

Illustrate the CMOS circuit of F=X1+X2X3

PDN network: F=X1+X2X3 = X1(X2+X3)

Negative logic

• You can also reverse the logic and let L (lowvoltage) represent the logic 1 and H (highvoltage) represent the logic 0– This is called negative logic

• An AND function becomes an OR function andvice versa– It is not important which logic is used - negative or

positive, but positive logic is more traditional

Three-state?

A CMOS-gate in addition to "1" or"0" is also provided with a thirdoutput state - the three-state ”Z”. ( =unconnected output).

If many outputs are connected to thesame line ("bus"), you can use one ofthe out-puts at a time . The otheroutputs are held in the Three-statecondition.

Three-state?

”0”

”1”off

off ”Z”

Three-state?

A”1”

on”0”

High Impedance ('Z')

AY = ''ZY =

Output is not connected28

Transmission gate (pass gate)

VA VE VOH

L L ZL H LH L ZH H H

• The pass gate acts as a switch controlled by E• If E = 0, the switch is open, Q = Z• If E = 1, the switch is closed, Q = A• Pass gates have a smaller driving capacity

than ordinary gates

Area: ATG= 2 Transistors

than ordinary gates

VA VE VOH

than ordinary gates

Multiplexer

The inverter is denoted by a circle

Example: MUX is a dataselector

Q Q = XS + YS

Transmission gateMUX Implementation

B FSel

Area: Amux= 6 Transistors

Sel2 MOS

2 MOS”0”

Sel2 MOS

”1”

XOR implementation with pass gates

F = a ⊕ b

”1”

onF = A Å B

”0”

offF = A Å B

011101110000FBA

Things Take Time ...About delays in circuits

• Each wires in an electronic circuits has a capacitance• Capacitance has a negative effect on the speed of

operation of logic circuits

Delays in circuits

Typical delays

NAND, NOR TNOT ½ T, T (if implemented using

NAND-gate)AND, OR 2T (2 NANDs in a row)XOR, XNOR, MUX 3T...5TXOR, MUX (Pass-Gate) 2T

Optimized structures (MUX)

Area: AMUX= 2+6+6+6=20TransistorsDelay: TMUX= 5TNAND

Area: AMUX= 2+4+4+4 =14TransistorsDelay: TMUX= 3TNAND

DeMorgan

Area: AMUX= 2+2+2=6TransistorsDelay: TMUX= ~ 2TNAND

AND-OR NAND-NAND

Best!43

Optimized structures (XOR)

Area: AMUX= 2+2+6+6+6=22TransistorsDelay: TMUX= 5TNAND

Area: AMUX= 2+2+4+4+4=16 TransistorsDelay: TMUX= 3TNAND

DeMorgan

Area: AMUX= 2x4=8 TransistorsDelay: TMUX= ~ 2TNAND

Area: AMUX= 16 TransistorsDelay: TMUX= 3TNAND

NAND only

Best!44

Fan-in

• Fan-in is the number of inputs to the gate.• If a gate has many inputs, it has a larger internal

capacitance => its internal delay Ti (also calledthe intrinsic delay) becomes larger.

28IE1204 Digital Design, HT14

Gates with more than 2 inputs

3-input NAND

• Gates with more thanthree or four inputs areused rarely

• The internal capacitancebecomes too large andgates too slow

• A long line of transistorsconnected in series giveslong delay!

High fan-in is solved with tree-structures

DeMorgan

)( cbacba ××=××

)()( dcbadcba ×××=××× dcbadcba ×××=×+× )()(

More tree structures ...

)()( dcbadcba +++=+++

)()( dcbadcba ÅÅÅ=ÅÅÅ

• Fan-out is number of other gates that a specificgate drives

• Each of driven gates increases the capacitiveload on f

Fan-out

(B) Equivalent circuit for timing purposes

(A) Inverter that drives n other inverters

To the inputs ofn other inverters

To the inputs ofn other invertersx

Cn= NC

Effect of fan-out on propagation delay

• The propagation time for different fan-outs

for n =1Vf

for n = 4Vf

• A buffer is a circuit that implements thefunction f(x) = x

• Buffers are used to increase performance• They have larger transistors and can drive

higher-than-normal capacitive loads• They are also used when high current flow

is needed to drive external devices

Buffering

High Fan-out: Use Buffers

Non-Inverting Buffer Tri-State Buffer

When En = 0, f isdisconnected from x

When En = 1, f = x

High-Fan-Out Buffer

En x En f0 0 Z0 1 01 0 Z1 1 1

Critical Path (Longest path)

f = Sm (3,2,0) = x2x1x0+ x2x1x0+ x2x1x0

Critical Path (cont'd.)

x0x1x2

2120210 xxxxxxxf ++=

x0 x1 x2 all pass NOT , AND, and OR,On their way to the output f, but x2 has the load of threeinputs (it is two for x0 and x1). ”Critical path” becomesfrom x2 to f!

3 * Tinv

Signal Racing

f(x) = x x = x x = 0f(x)x

If a signal has severalpaths to the exit, socalled signal racingmay happen

f2(x) = x

Tand Tand

• NMOS and PMOS circuits consume both staticand dynamic power– Static power is dissipated by the current that flows in

the steady state– Dymanic power is dissipated when the current flows

because of changes in signal level• CMOS circuits consume only dynamic power

Power consumption of CMOS

7400 Series Standard Chips

Implementation of a logic function

An implementation of f = x1x2 + x2x3

x1x2x3

7408 7432

Look-up tables (LUT)

Two-input LUT

Programmablecell 1

A LUT with n inputs canrealize all combinationalfunctions with up to ninputs

The usual size in anFPGA is n = 4

Example: XOR gate

Two-input LUT

Programmedvalues 1

Multiplexer

011101110000

21 fxx

Three-way light control

Brown/Vranesic: 2.8.1Suppose that we need to be ableto turn on / off the lamp fromthree different places.

x1x2x3

Three-way light control

321321321321)7,4,2,1( xxxxxxxxxxxxmf +++==å

NAND-NAND

7404 7410 7410 7420

If we change toNAND-NAND allnecessary gates areincluded with thesimulator.

#1 #2 #3 #4

You must enter the pin number in the schematic - otherwiseyou can get lost!

7410 7410 7420

1:31:4

2:22:13

1:131:12

2:102:112:9

3:13:133:23:33:43:5

4:14:24:44:5

Simulate!

How many transistors are inside an iPhone6?

Make a guess!

2,000,000,000

What would the world be without theCMOS?!

• Logic gates can be implemented withCMOS technology

• Logic circuits have a delay• CMOS circuits have relatively low power

consumption

Summary

IE1204 Digital Design: L3: CMOS circuits, Implementation ......Transmission gate (pass gate) A Q E A...

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