Hdi Presentation 110913

HDI Printed Circuit Boards

The Integrated PCB Producer

The Integrated PCB Producer

•!•!•!•!•!•!•!•!•!•!•!•!

Higher Complexity •! Increasing functionality •! Decreasing size •! Lighter weight Higher Density •! Smaller feature sizes •! Decreasing via sizes

Worldwide Micro-Via Demand (units Million m!)

Source: BPA Report

0

5

10

15

20

25

30

2007 2008 2009 2010 2011 2012 2013

Rest of World

China

SE Asia

Europé

Japan

USA

•! IPC-2226 Sectional Design Standard for High Density Interconnect (HDI) Boards

•! IPC-6016 Qualification & Performance Specification for High Density Interconnect (HDI) Layers or Boards

•! IPC-4104 Specification for High Density Interconnect (HDI) and Microvia Materials

•!Defines a single microvia layer on either one or both sides of core.

•!Core can be multilayer, rigid or flex.

•!Core is typically manufactured using conventional PWB techniques.

•!Uses both plated microvias and plated through holes for interconnection.

•!Employs blind, but not buried vias.

•!Defines a single microvia layer on either one or both sides of core.

•!Core can be multilayer, rigid or flex.

•!Core is typically manufactured using conventional PWB techniques.

•!Uses both plated microvias and plated through holes for interconnection.

•!Employs blind and buried vias.

•!Defines at least two layers of microvia layers on either one or both sides of core.

•!Core can be multilayer, rigid or flex.

•!Core is typically manufactured using conventional PWB techniques.

•!Uses both plated microvias and plated through holes for interconnection.

•!Employs blind and buried vias.

•!Defines to have at least one microvia layer on either one or both sides of core.

•!Core is typically manufactured using conventional PWB techniques.

•!Uses both plated microvias and plated through holes for interconnection.

•!Uses a passive core not electrically connected, used normally for CTE management.

•!Uses thin “cores” which uses both plated microvias and conductive paste interconnections.

•!Uses B-stage resin system prepreg where conductive material locally have been placed.

•!OrmeLink TLPS

•!A construction where connections are buildup without normal plating.

•!The connections are formed with conductive ink, or other type of conductive material.

•!Examples as ALIVH (Any-Layer, Inner Via Hole )and PALAP (Patterned Prepreg Lay Up Process ) both Japanese inventions.

•! Increased interconnection density by miniaturization of holes, pads and conductors.

•! Provides the possibility to have a via hole connect direct in the

SMD or BGA pad. •! Improved signal integrity because of reduced track length. •! Improved possibility to maximization of ground connections. •! Opportunities of better thermal enhancement. •! Improved reliability by stepping up technology rather than

compromising existing design rules.

Class 1000 clean room with auto alignment exposure units and LDI

LDI

Production key equipment

Automatic lay up and high capacity lamination press with auto-loading

Automatic lay-up

Production key equipment

New generation of CO! laser drilling machines

Production key equipment

Good HDI Cu plating solution with horizontal copper plating line plus vertical continuous plating line

In processing

Horizontal Cu plating line VCP line

Production key equipment

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All the structure as above are available for mass production

Build-ups

One of the newer ways to produce HDI boards is to use copper filled "vias. This gives benefits such as:

•! Saves space compared to staggered "vias

•! Improved thermal management

•! Improved current capacity

•! Improved planarity on SMD pds for BGA components

By using special chemistry with a special mix of brighteners and levelers it is possible to fill up cavities.

•! The brightener which is the smallest particle have the highest priority on the via bottom and accelerates the deposit of copper.

•! The leveler suppresses the deposit rate on the surface and the via holes corner.

•! The dimple will be around 15"m in the middle of the "via.

Key features for a good result:

•! A good laser drilled hole free from protruding fibers.

•! Proper desmearing and electro less plating.

•! A small laser via diameter, preferred around 75-100"m.

•! A moderate dielectric thickness preferred around 75"m since this will give a lower dimple after filling.

Future components will have even smaller pitch than today. Example below shows a pad layout for a 8*8 ball grid array component with a pitch of 300"m. With this component it’s possible to have 64 contact points on approx 4mm!.

•!•!•!•!•!•!

Copper C-stage B-stage

What material should be used? Since HDI boards are a more sensible in construction and we now have moved over to lead-free soldering there is a need for better material then on normal multilayer boards. They key parameters are: •! Total CTE in Z-axis •! Decomposition temperature •! T260 •! T288 •! Glass transition temp (Tg)

New materials according to IPC-4101C

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Conclusions: •! Use LDP or prepreg instead of RCC foil as material for "via

•! Use high quality FR4 in cores and Prepreg

•! Specify the material according to IPC standard instead of any name of the material

This technique is a patent from Jiangnan Institute of Computing Technology and is a sequential process where the "vias are created first as copper pillars and after that coated with the dielectric material. This technique creates the most reliable and robust "via on the market.

The perfect micro via?

The process is starting with a normal PCB in the case a 4 layer

!! Panel plating of copper in hole wall

!! Plugging of holes / grinding of excess

!! Over plating of holes

!! Pattern etching

!! Plating of seeding layer

!! Dry film lamination

!! Exposure, plating

!! Stripping resist & flash etching

Appearance of “copper pillar” after plating

!! Coating with dielectric

!! Leveling down

!! Plating of seed layer

!! Dry film

!! Exposure & Develop of dry film

!! Plating, Stripping

!! Dry film, exposure, plating

!! Stripping & Flash etching

!! Repeating previous steps (n-times)

!! Soldermask

!! Surface treatments

Copper pillar technique benefits

• Enables the manufacture of complex high-density interconnections, responding to future market demands for cellular phones and other next-generation mobile information devices. • Use of solid copper intra-layer interconnections enables the reduction of electrical resistance and improves thermal conductivity, responding to such needs for IT devices with increased functionality. • Enables small diameter pillar formation, leveraging the advantageous material performance characteristics of copper.

ELIC (Every Layer Inter-Connection ) This rather new technique have been popular due to the smaller pitches used mainly in mobile telephones, the standard today is 400"m pitch BGA. One of the starting company using this technique was Ibiden and they called it FVSS (Free Vis Stacked up Structure)

ELIC (Every Layer Inter-Connection ) Benefits is of course no need for buried mechanical holes which takes up a lot of space inside the board.

Disadvantage is that the thickness can not be 1.60mm on lower layer account boards if full ELIC is used.

ELIC (Every Layer Inter-Connection ) The process is starting with a thin FR4 core 60-80"m

!! Laser drilling of "vias in core

!! Copper plate "vias

!! Reduce copper if needed

!! Coating of etch resist

ELIC (Every Layer Inter-Connection ) The process continue 2

!! Exposure / Develop

!! Etch

!! Strip

!! Brown oxide

ELIC (Every Layer Inter-Connection ) The process continue 3

!! Lay-up / Pressing

!! Laser drilling of more "vias

!! Copper plate "vias

!! Reduce copper if needed

ELIC (Every Layer Inter-Connection ) The process continue 4

!! Coating of etch resist

!! Exposure / Develop

!! Etching

!! Strip

ELIC (Every Layer Inter-Connection ) The process continue 5

!! More layers, more laser drilling etc#

!! Soldermask, surface treatment etc#

ELIC (Every Layer Inter-Connection ) Alternative versions

Design rules

•! Always aim for symmetrical build-ups even if "vias not are needed on both sides.

•! Aspect ratio on blind hole should be kept under 1:1, preferred 0.7:1

•! When using 2 levels of "vias, keep the copper balance good, fill out empty areas with ground plane, so the amount of resin is enough to make a good encapsulation of the tracks.

Example of to high aspect ratio on "via

A

D

B

C

A Entry pad size 300!m 250!m L1

B Microvia size 100!m 100!m STD

C Dielectric thickness 60-80!m 60-80!m STD

D Capture pad size 300!m 250!m L2

A Entry pad size 300!m 250!m L1 & L2

B Microvia size 100!m 100!m V1-2 & V2-3

C Dielectric thickness 60-80!m 60-80!m L1-L2 & L2-L3

D Capture pad size 300!m 250!m L2 & L3

E Microvia pitch 400!m 350!m STD

A B

C

D

B

C

E

A Microvia size 200!m 200!m V1-2

B Microvia size 100!m 100!m V2-3

C Dielectric thickness 60-80!m 60-80!m L1-L2 & L2-L3

D Capture pad size 300!m 250!m L3

E Entry / Capture pad 400!m 350!m L2

F Entry pad size 400!m 350!m L1

A

C

D

B

C

E

F

A Microvia size 200!m 200!m V1-3

B Entry pad szie 400!m 350!m L1

C Dielectric thickness 140!m 140!m L1-L3 Max

D Capture pad size 400!m 350!m L3

E Anti pad size 400!m 350!m L2 Min

A

C E

B

D

A Entry pad size 300!m 250!m L1

B Microvia size 100!m 100!m V1-2 & V2-3

C Dielectric thickness 60-80!m 60-80!m L1-L2 & L2-L3

D Capture pad size 300!m 250!m L2 & L3

A

D

B

C

C

!via between L2-L3 need to be copper filled

A Entry pad size 300!m 250!m L1

B Microvia size 100!m 100!m V1-2

C Dielectric thickness 60-80!m 60-80!m L1-L2

D Capture pad size 500!m 450!m L2

E Buried hole size 250!m 200!m

A

D

B

C

E