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ADC DSPLNA X XIF stage BB stage
LO1 LO2
ADC DSP
� The ADC sampling jitter is critical at high frequency
The hardware components are embedded in a digital processor
Digitization process represents a critical issue
E-ADC State of the art
MLL MZ mod.
ADC
ReceivedRADAR signal
Time Domain Parallelizer(DEMUX)
ADC…
tt
÷N
t
Optical sampling Sample parallelization
t
Electronic digitization
Sampling pulses
Amplitude noise σσσσa
Timing jitter ττττa
The precision of the digitization process is affected by
• time jitter ( ττττj)• amplitude noise ( σσσσa)
of the sampling pulses
The noise introduced by the sampling pulses must be lower than the quantization noise ( ∆∆∆∆VQ)
These requirements impose:• amplitude jitter <0.03% • time jitter <10fs
integrated over the duration of the radar measurement
1
3 2j ENOB
samplingfτ
π= =
( )1
12 2 1a ENOB
σ < =−
Voltage
Tim
e
Voltage
Optical Power
Time
Transmittivity
Modulator
ext.ratio
Modulator Transfer Function
Vbias
RF signal
Transposed Optical Signal
� Expected received dynamic range: 70dB.
� A Sensitivity Time Control (STC) allows avoiding strong nonlinearities at the modulator.
Sensitivity Time Control
MZ switch
MZ switch
MZ switch
RFPort 1
RFPort 2
RFPort 3
Optical input
t
t
Optical Output 1
Optical Output 2
Optical Output 3
Optical Output 4
t
t
t
t
t
1:4 parallelizer
MZ switch
MZ switch
MZ switch
RFPort 1
RFPort 2
RFPort 3
Optical input
t
t
Optical Output 1
Optical Output 2
Optical Output 3
Optical Output 4
t
t
t
t
t
1:4 parallelizer
Device developed by Selex ES within the Nexpresso project
MLL EDFAMZM
Switching Matrix ADC
ADC
÷ 2400MHz Clock
RF input
ADC
ADC
OBPF
÷ 2
D-MZM
D-MZM
D-MZM
DCF spools
MLL EDFAMZM
Switching Matrix ADC
ADC
÷ 2400MHz Clock
RF input
ADC
ADC
OBPF
÷ 2
D-MZM
D-MZM
D-MZM
DCF spools
1. MLL (OneFive Origami) at 400MHz with 10fs jitter @[10KHz-10MHz] . Pulse length 400fs .
2. Standard 40GHz MZM.
3. Integrated 1x4 LiNbO 3 switching matrix , with 25dB ER .
4. Pulses are broadened with -300ps/nm chromatic dispersion to reduce the peak power.
5. Four 2GHz bandwidth photodetectors in their linear region.
6. Four 100MSample/s 14-bit ADCs (National Instruments PXIe5122).
OpticalModulator
MLL pulses
RF input
Optically sampled signal
PD
Opt
ical
Sw
itchi
ng
PD
PD
PD
ADC
ADC
ADC
ADC
1
2
3
4
Which are the sources of nonlinearities?
Modulator harmonics
Limited ER of the matrix
Different IL
Different Responsivity
Different offset\gain and time skew
Channels inequalities producespurious components
SFDR = 15dBc2th HR = 38dBc
SFDR = 57dBc2th HR = 55dBc
SFDR = 65dBc2th HR = 55dBc
Raw data
Gain\offsetEqualization
Time skewEqualization
Performances enhancement due to the Digital Signal Processing (DSP)
� The algorithm doesn't change the noise floors
� The spurious peaks drastically decrease
� Enhanced SFDR
fundamental interleavingCrosstalk and time skew
� At lower frequency the system ENOB is limited by the spurious peaks
� At higher frequency the ENOB is mostly limited by the time jit ter of the MLL
Input freq ENOB
9.92GHz 7.4
25.02GHz 7.1
39.82GHz 7.0
ENOB for 200MHz signal bandwidth
Our results
Improvements:
� Reduction of the noise floor: differential detection
� Reduction of the spurious components: improved switching m atrix
� Increase of the instantaneous bandwidth: MLL and ADCs with h ighersampling rates
Developments:
� Including the simultaneous tunable anti-alias filtering ( submitted to OFC2014)
thank you!paolo.ghelfi@cnit.it
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