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This material is based upon work supported by the U.S. Department of Energy Office of Science under Cooperative Agreement DE-SC0000661, the State of Michigan and Michigan
State University. Michigan State University designs and establishes FRIB as a DOE Office of Science National User Facility in support of the mission of the Office of Nuclear Physics.
Ryan Bliton
Power Supplies Engineer
FRIB Power Supplies Status And FRIB “Digital” DCCT Integration To The Fast
Machine Protection System
▪ 10s of µs – the topic of this presentation
▪ 100s of Milliseconds– possible future need for a medium speed interface external current transducer to RPS PLC
▪Milliseconds to seconds - Enables/disables beam through EPICS and PLC
PS Interface to Machine Protection System
R. Bliton, POCPA September, 2018, Slide 2
Fast
Protection
System
(FPS)
Run Permit
System
(RPS)
Machine
Protection
System
The FRIB power supplies interface to the Machine Protection System to disable the beam in case of a PS drifting past a threshold. There are 3 speeds
Future
Medium
Speed
RPS
System
Fast Protection System Overview
▪ The goal of the Machine Protection System is to turn off the beam within 35µs of an undesirable machine state being sensed.• E.g. dipole current is drifting or has shut off
▪ Many systems are connected as ‘Fast’ devices to MPS, including Beam Loss Monitors, Low Level RF, bending dipole magnet power supplies
R. Bliton, POCPA September, 2018, Slide 3
Fast Protection System Beam Mitigation
R. Bliton, POCPA September, 2018, Slide 4
Corrector magnet connection
discovered and resolved
during upper LEBT testing
▪Beam mitigation for MPS is accomplished by disabling:• Ion Source RF, Klystron • Ion Source HV platform»40kV extraction bias
• Chopper• Electrostatic bending dipoles
Front End and Vertical Drop
SC Source
RT Source E-Bend
E-Bend
Chopper
Chopper and E-Dipole Mitigation Devices
R. Bliton, POCPA September, 2018, Slide 5
Corrector magnet connection
discovered and resolved
during upper LEBT testing
Chopper▪ The Chopper switch disable beam in ~25nS but is
not failsafe (requires HV to disable beam)
▪ The E-Dipole switches disable beam in ~1us • The solid state switch isolates the HV PS and grounds
the E-dipole plate
• 10% voltage drop
disables beam
E-Dipole
E-Dipole
Chopper waveform
E-dipole waveform
MPS fast abort switch
cutaway
Fast Protection Devices – Tunnel Dipoles
R. Bliton, POCPA September, 2018, Slide 6
Corrector magnet connection
discovered and resolved
during upper LEBT testing
LS1
LS3BDS FS2
FE
LINAC tunnel beamline
▪ The dipoles (highlighted red) in the graphic below all connect to the FPS system
▪ The Front End bending dipoles are excluded due to low energy beam
Front End and Vertical Drop
SC Source
RT Source E-Bend
E-Bend
Chopper
FS1LS2
Dipole Fast Device – Digital DCCT
R. Bliton, POCPA September, 2018, Slide 7
▪ Secondary DCCT measures dipole current
• Analog to Digital Converter (ADC), controller, and digital comparator built in the DCCT
• DCCT provides fast signal to FPS
• First Articles received January 2018
• Acceptance testing completed February 2018
• Integration with FRIB General Purpose Digital Board (FPGDB) in progress
Beam
Mitigation
FRIB General Purpose Digital Board
▪ The MPS response logic will be controlled by the FRIB General Purpose Digital Board (FGPDB)
▪ Developed in-house.
▪ Adds time stamping and high-speed data logging capabilities
▪ Works with full MPS system to trigger mitigation devices
▪ Many I/O options including LAN, USB
R. Bliton, POCPA September, 2018, Slide 8
Digital DCCT Alarm Requirements
R. Bliton, POCPA September, 2018, Slide 9
▪ After the power supply reaches thermal equilibrium at it’s desired set-point, the digital DCCT will set a current baseline based on the current read-back and set a +-window around the baseline
▪ Afterward, if the measured current crosses either the +or- window threshold, then the alarm signal will be sent and the beam will be shut off
▪ The alarm output signal should switch from the ‘good’ state to
‘bad’ state within 10µs of the threshold being reached
Digital DCCT Margin Requirements
R. Bliton, POCPA September, 2018, Slide 10
▪ DCCT must be able to be armed (set the current baseline and thresholds).
▪ DCCT must set a current baseline based on the current read-back, set a +-window around the baseline, and trigger if this threshold is crossed.
▪ The thresholds must be settable by the user
▪ ADC must have 20+bit resolution
Upper Margin
Lower Margin
Measured Center Line
Actual Signal
▪ The measured center line settings have 20+bit resolution
▪ Streaming raw data output through a high-speed bus (e.g. USB)
▪ Time-stamping of data
Upper threshold
Lower threshold
Current levels/Resolution Requirements
R. Bliton, POCPA September, 2018, Slide 11
▪Dipole Requiring Digital DCCTs are listed below:
Power
Supply
Threshold
% of Full
Scale
Maximum
Power
Supply
Current
(A)
Full Scale
Expected
Maximum
Operating
Current (A)
Minimum
Operating
Current
Needed
(A)
Window
Size
Minimum
(A)
Response
Time
Requirement
PSD1 ±2% 300 247 60 ±1.2 10 µs
PSD2 ±2% 240 214 122 ±2.44 10 µs
PSD3 ±0.5% 250 200 140 ±0.7 10 µs
PSD4 ±2% 150 135 100 ±2 10 µs
▪ The threshold requirements were given as a percentage of full scale current.
▪Each PSD3 is dedicated for a single magnet while the other power four magnets each in series
▪ The worst case is PSD3 with ±0.5% threshold requirement resulting in a minimum window size of ±700mA.
Digital DCCT Source Selection
R. Bliton, POCPA September, 2018, Slide 12
▪ It was decided to seek a COTS product for the digital DCCT in lieu of developing it in-house as long as the cost was reasonable.
▪ Unfortunately no COTS products offered higher than 100 kHz sample rate (one sample every 10µs).
▪ It is not possible for a trigger alarm signal to be sent in <10µs after the PS current crosses a threshold being that at least one sample must be recorded
▪ We proposed reducing the margins slightly such that the threshold will be reached sooner to compensate for additional delay.
▪ This will work as long as the decrease in margin does not cause unnecessary tripping
Magnet
Old Threshold %
of Full Scale
Old Window
Size
Minimum
(A)
Minimum
Operating
Current
Needed (A)
Response
Time
Requirement
D1 ±2% no change ±1.2 60 20 µs
D2 ±2% no change ±2.44 122 20 µs
D3 ±0.5% to ±0.4% ±0.56 140 20 µs
D4 ±2% no change ±2 100 20 µs
DCCT Test Circuit/Components
R. Bliton, POCPA September, 2018, Slide 13
▪ DCCT Test Circuit Layout
• No filtering or averaging could be used to clean up the analog DCCT signal because of latency concerns
• A resistive dummy load was used.
PSResistive
Load
Digital
DCCT
Calibrated
Analog
DCCT
Oscilloscope
Fast trigger
output (3.3V)DCCT Analog
Output -10 to 10V
µs Delay Test Results
R. Bliton, POCPA September, 2018, Slide 14
▪ Using a threshold of 10 Amps
▪ Positioning the alarm at zero
▪ Set cursors where average DCCT value crosses trigger points
Upper trigger
point 269.498mVUpper trigger
time to alarm 6µsLower trigger
point 267.562mVLower trigger
time to alarm 46µs
▪ Repeat the process by finding lower threshold trigger points and ramping PS down.
▪ Repeating both ramp-up and ramp-down tests twice resulted in a ~40µs time window, or +-20µs.
Alarm Signal
Avoiding False Triggering
R. Bliton, POCPA September, 2018, Slide 15
▪ The possibility of false triggering is reduced by waiting for a set number of sequential samples to cross the threshold before triggering.
▪ The test was repeated with the trigger set to wait for 4 ‘bad’ samples before the alarm signal
Upper trigger
point 269.298mVUpper trigger
time to alarm 10µsLower trigger
point 266.762mVLower trigger
time to alarm 82µs
▪As expected, waiting for 4 bad samples instead of one adds 30µs to the alarm delay time.
Alarm Signal
Testing Center Line Resolution and Minimum Threshold
R. Bliton, POCPA September, 2018, Slide 16
▪ It was important to confirm the setting resolution for the window and what sort of noise levels the digital DCCT sees on the PS output
+100mA
-100mA
▪ PS was set to 200A
▪ Threshold settings started at +-100mA and were decreased in subsequent tests• +-100mA with 1 bad sample ok long term
(2 hours+)
• +-50mA with 2 bad sample ok long term
• +-40mA with 8 bad sample ok long term
▪Next the test was repeating with the current setpoint 200.1A, followed by 199.05A • Results were similar
Measured Center Line
Thank you
End
R. Bliton, POCPA September, 2018, Slide 17
µs Delay Testing Method
R. Bliton, POCPA September, 2018, Slide 18
▪Goal: Capture trigger alarm output with DCCT waveform, determine delay between threshold crossing and alarm output
▪ Issue: How to tell exactly when threshold is crossed
▪Procedure: • Warmup PS for 1 hour before starting
• Determine limits as read by analog DCCT»Set PS close to upper threshold from below
» Increment by 1mA, waiting 5 seconds between, until alarm triggers
»Repeat a second time, use lower number
»Set close to upper threshold from above
»Decrement by 1mA, waiting 5 seconds between, until alarm triggers
»Repeat a second time, use higher number
• Ramp past upper threshold from below at maximum PS ramp rate
• Find the higher and lower numbers on the analog DCCT waveform
• Record time difference between these points and the alarm signal
D4 Example
R. Bliton, POCPA September, 2018, Slide 19
▪Magnet layout
Which Dipoles are Monitored
R. Bliton, POCPA September, 2018, Slide 20
Corrector magnet connection
discovered and resolved
during upper LEBT testing
▪Magnet layout
D2 Dipoles
D3 Dipoles
Which Dipoles are Monitored
R. Bliton, POCPA September, 2018, Slide 21
▪Magnet layout
D4 Dipoles
D1 DipolesD1 Dipoles
Backup Magnet Layout
R. Bliton, POCPA September, 2018, Slide 22
▪Backup
Corrector magnet connection
discovered and resolved during upper
LEBT testing
LS1
LS3BDS
FS2LS2
FE
FS1
Target
D1D1D2 D3
D4
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