FPGA based Embedded SoPCs: System on Programmable Chipscourses/ee8205/lectures/... ·...

©G. Khan EE8205: Embedded Computer Systems FPGA based SoPCs Page: 1

FPGA based Embedded SoPCs:System on Programmable Chips

EE8205: Embedded Computer Systemshttp://www.ee.ryerson.ca/~courses/EE8205/

Dr. Gul N. Khanhttp://www.ee.ryerson.ca/~gnkhan

Electrical and Computer EngineeringRyerson University

Overview• Introduction to Altera SoPCs• Embedded System on Programmable Chip • Cyclone IV and Stratix FPGAs• Nios-II CPU Core and SoPC IPs; Avalon Bus • SOPC Builder

Introductory Articles on SoPC, DE-115 Manual available at the course webpage.Part of Sections 5.4, 6.3, 6.4 and part of Chapter 9 of text by Navabi

Programmable Chip Mainly two sources of programmable chips that can

accommodate a significant part of embedded computer system including CPU and peripheral devices

Altera• Apex, Stratix, Cyclone use NIOS processor core• Cyclone-V, Stratix-V Devices use ARM Cortex CPU

based coreXilinx• Spartan II, Virtex, Virtex-E, Virtex-II, Virtex-II Pro.• Virtex-5, Virtex-6 and Virtex-7 accommodate µblaze

and PowerPC as well as ARM Cortex cores.

A Nios CPU based SoPC FPGA

DE2-115 NIOS Development Board

DE2-115 Block Diagram

DE2-115: SoPC Options

DE2-115: TV Box Configuration

DE2-115: Karaoke Machine Configuration

DE2-115: Karaoke Configuration

DE2-115: SD Music Player

Altera System on Programmable Chips Cyclone and Stratix Series FPGACyclone IV-E Family FPGAs

Cyclone IV-E FeaturesLow-cost, low-power FPGA fabric: 6K to 150K logic elements Up to 6.3 Mb of embedded memory Up to 360 18 × 18 multipliers for DSP

processing intensive applications Protocol bridging applications for under 1.5 W

total power

Cyclone-IV LE (Logic Elements)LE is a compact (a small logic) unit that provides

advanced features with efficient logic utilization.• A four-input look-up table (LUT), which is a function

generator that can implement any function of four variables.• A programmable register.• A carry chain connection.• A register chain connection.• The ability to drive all types of interconnects: local, row,

column, register chain, and direct link interconnects.• Support for register packing and feedback.

Each LE’s programmable register can be configured for D, T or JK operation and has data, clock, clock enable, and clear inputs.

Cyclone Logic Element

LAB: Logic Array BlocksEach LAB consists of 16 LEs LAB control signals, LE

carry chains, register chains and local interconnect.

LE Normal and Arithmetic ModesNormal modeGeneral logic applications and combinatorial functions

Logic Element Arithmetic ModeArithmetic mode is ideal for implementing adders, counters, accumulators, and comparators. LE can implement a 2-bit full adder and basic carry chain.

Cyclone IV M9K MemoryM9K blocks support the following features:• 8,192 memory bits per block (9,216 bits per block

including parity).• M9K memory block is split into two 4.5 K single-

port RAMs in the Packed mode.• Variable port configurations• Single-port and simple dual-port modes support

for all port widths• Initialization file to pre-load memory content in

RAM and ROM modes

M9K Memory Feature Summary

M9K - Dual Port MemoryThe widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit.

Embedded Multiplier Block ArchitectureThe embedded multiplier consists of multiplier block, input and output registers and interfaces: 18x18

Two 9x9 Multiplier Blocks

Cyclone-II (IOE) I/O Element

IOEs are located in I/O blocks around the periphery of the device.

An IOE contains one input register, one output register, and an output enable register.

IOEs contain a bi-directional I/O buffer and three registers. For complete embedded bi-directional single data rate transfer.

IOEs in a Bidirectional I/O Configuration

©G. Khan

Stratix-IV/Cyclone MLAB Memory

COE718: HW/SW Codesign of Embedded Systems FPGA based SoPCs Page: 27

LUT-based SRAM capability to the LAB. The MLAB supports a maximum of 640 bitsof dual-port SRAM. MLAB is a superset of the LAB and includes all LAB features.

©G. Khan

Cyclone-V SX SoC FPGACyclone-V FPGA family is based on 1.1-V, 28-nm. High performance designs and SoC prototyping.

Stratix-II Family FPGAs OverviewStratix-II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs).

Stratix-II Main Features• 15,600 to 179,400 equivalent LEs; New and innovative adaptive

logic module (ALM).• Up to 9,383,040 RAM bits (1,172,880 bytes).• TriMatrix memory consisting of three RAM block sizes.

(to implement true dual-port memory and (FIFO) buffers)• DSP blocks support dedicated multipliers (370 MHz), multiply-

accumulate functions, and FIR filters.• Up to 12 PLLs (4 enhanced PLLs and 8 fast PLLs).• Support for high-speed external memory, including DDR and

DDR2 SDRAM; RLDRAM II, QDR II SRAM and SDR SDRAM.• High-speed serial interface channels with dynamic phase

alignment (DPA) support data transfer at up to 1 Gbps using LVDS or Hyper Transport technology I/O standards.

©G. Khan

Stratix-V GX FamilyStratix-V FPGA family is based on 0.85-V, 28-nm. Highest performance designs, highest logic- and memory-density designs, and ASIC prototyping.

©G. Khan

Arria-V SX SoC FPGAArria-V FPGA family is based on 1.1V, 28-nm. It can prptotype and implement ARM Cortex CPU based SoC

Adaptive Logic Module Structure

ALMALM can operate in one of the modes that are Normal, Extended

LUT, Arithmetic and Shared arithmetic mode.

High Level Block Diagram

4×2 Crossbar Switch on one ALM

4 × 2 crossbar switch (two 4-to-1 multiplexers with common inputs and unique select lines) can be implemented in one ALM.

ALM in Arithmetic Mode

Example of a 3-bit Add Utilizing Shared Arithmetic Mode

DSP Block Architecture

DSP BlocksDSP functions for complex FIR and IIR filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlation.

They all use the multiplier as the fundamental building block. Each DSP block can be configured for up to: eight 9×9-bit, four 18×18-bit multipliers or one 36×36-bit multiplier

Nios-II Embedded Processor

Nios-II CPU Core Features

• Nios-II CPU is a pipelined, single-issue RISC processor • Most instructions run in a single clock cycle.• The instruction set is targeted for compiled (high level

language) embedded applications.• The Nios family of soft core processors includes 32-bit

architecture.• The register file size is 32 register of 32-bit wide. However,

it can have one or more shadow register files transparent to application code.

• Shadow register files are manipulated by kernel as Nios-II has support the user and kernel modes.

Nios-II Programmer Model

A Typical Nios CPU based System Ethernet Frame Data Transmission Path Using DMA

and Simultaneous Multi-Mastering

Altera SoPC IPs• DMA

The Nios direct memory access (DMA) peripheral is used to perform DMA data transfers between two memories, between a memory and a peripheral, or between two peripherals.

DMA peripheral has two Avalon master ports—a master read port and a master write port, and one Avalon slave port for controlling the DMA.

• Avalon Bus: On-chip Multi-master active bus

• PIO: PIO module is a memory-mapped interface between software and user-defined logic.

• Timer: 32-bit interval timer

• SPI: Serial Peripheral Interface

• UART: RS-232 asynchronous transmit and receive logic.

Avalon Bus• Avalon bus is an active, on-chip bus architecture that

accommodate the SOPC environment. • The interface to peripherals is synchronous with the Avalon clock.

Therefore, no complex, asynchronous handshaking and acknowledge schemes are necessary.

• Multiplexers (not tri-state buffers) inside the bus determine which signals drive which peripheral. Peripherals are never required to tri-state their outputs. Even when the peripheral is deselected

• The address, data and control signals use separate, dedicated ports. It simplifies the design of peripherals as they don’t need to decode address and data bus cycles as well as disable its outputs when it is not selected.

Avalon Bus ModuleThe Avalon bus module (an Avalon bus) is a unit of active logic that

takes the place of passive, metal bus lines on a physical PCB.

Slave Arbitrator

Avalon bus module contains one slave arbitrator for each shared slave port. Slave arbitrator performs the following.

• Defines control, address, and data paths from multiple master ports to the slave port and specifies the arbitration mechanism to use when multiple masters contend for a slave at the same time.

• At any given time, selects which master port has access to the slave port and forces all other contending masters (if any) to wait, based on the arbitration assignments.

• Controls the slave port, based on the address, data, and control signals presented by the currently selected master port.

Nios II basedEmbedded SoPC

Development Flow

Nios based Embedded Computer System

Cyclone IVFPGA SoPC

SoPC Builder: System TabThe System Contents Window

Nios II Types Available

SoPC BuilderTabSystem Contents with Nios II

SoPC Builder: Final Nios II System• Final System Contents • Auto Assign Base Addressing

Nios System Generation

Software for Nios SystemNIOS II IDE New Project Wizard

FPGA based Embedded SoPCs: System on Programmable Chipscourses/ee8205/lectures/... ·...

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