FLOATING GATE DEVICES Kyle Craig. Flash Memory Cells – An overview Paolo Pavan, Roberto Bez, Piero...

FLOATING GATE DEVICES

Kyle Craig

Flash Memory Cells – An overview Paolo Pavan, Roberto Bez, Piero Olivo and

Enrico Zanoni

Motivation!

Predicted Worldwide Memory Market

Flash prediction, 6% of total memory market…

According to Gartner Research in 2006 flash consisted of 33% of the market

FGMOSFET

If a charge can be forced onto the floating gate, it will remain there.

Charge on the floating gate shifts the VT of the device Two VT device

By having two VTs depending on the charge of the floating gate, device can be used as a memory. No charge on floating gate = logic 1 Charge on floating gate = logic 0

Hot Electron Injection

Electrons travel laterally from source to drain with applied voltage. Voltage on gate gives enough energy to inject through the thin oxide onto the floating gate

Three principles “lucky” enough to gain enough energy No collisions in substrate No collisions in oxide

Fowler Nordheim Tunneling

With an applied electric field, electrons are able to tunnel through the oxide.

The thicker the oxide, the greater the applied voltage needs to be

10nm oxide is considered standard Variation in this oxide will lead to wide distribution of VT values

Side effects

HEI and FN Tunneling can lead to charge being trapped in the oxide Change in the VTs of the device Inability to add or remove charge from

floating gate

Flash Memory: Programming Assumed device starts with no charge on

the floating gate i.e., storing a “1” Use HEI to put charge onto floating gate

Shifts VT of device Depends on:

Channel Length, Time, Temp, drain voltage

Flash Memory: Erasing

Use Fowler-Nordheim Tunneling to pull electrons off of floating gate to the source Depends on:

Oxide thickness, applied voltage Need to worry about breakdown of the

source/substrate junction Limits Scaling!

Program, Erase, Read

Source Control Gate (WL)

Drain (BL)

Read GND Vcc Vread

Program GND Vpp Vdd

Erase Vpp GND FloatingTypical Values: Vcc = 5V Vpp = 12V Vdd = 5V Vread = 1V

Programming Disturbs

Gate Disturbs – Cells not selected with active WL DC Erasing

If cell has charge store on it, electrons can tunnel from the FG to the Control Gate

DC Programming If the cell has no charge on it, electrons can

tunnel from the substrate to the FG

Programming Disturbs

Drain Disturbs Electrons can tunnel from the FG to the

drain Holes generated by impact-ionization in

substrate then injected into FG Lowers the high VT value

Retention/Endurance

Retention: Change in charge on FG Intrinsic: field-assisted electron emission,

thermionic emission Extrinsic: Oxide defects, Ionic

contamination Endurance: Change in threshold values

based on number of cycles

Scaling

Issues with scaling Decreasing L will increase performance

but also increase number of disturbs Physical voltage constraints

3.2 eV energy barrier and 8-9MV/cm for FN Oxide thickness limit

NOR vs NAND

NOR similar in structure to SRAM NAND more comparable to Harddrives

**From Micron NAND vs NOR Comparison

A 6V Embedded 90nm Silicon Nanocrystal Nonvolatile Memory R. Muralidhar, R.F. Steimle, M. Sadd, R.Rao,

C.T. Swift, E.J. Prinz, J. Yater, L. Grieve, K. Harber, B. Hradsky, S. Straub, B. Acred, W. Paulson, W. Chen, L. Parker, S.G.H. Anderson, M. Rossow, T. Merchant, M. Paransky, T. Huynh, D. Hadad, KO-Min Chang, and B.E. White Jr.

Motivation

Scaling of conventional floating gate memories is limited due to high voltages that are needed

Use of Silicon Nanocrystals has some benefits over floating gate Immune to oxide defects during

program/erase Reduction of oxide thickness Reduction of operating voltage

Replaces floating gate of traditional cell with discrete Nanocrystal particles

Produced using a conventional CMOS process flow with only 4 additional masks compared to logic

Control Gate

Current Characteristics

Two Bits/cell operation is possible with proper nanocyrstal isolation

Without needed isolation functions like a normal FG

Mask Adder

Endurance and Retention

Can be erased from the top oxide (between FG and control gate) or the bottom oxide (between nanocrystals and substrate) Erasing through the top oxide produces

lower VT

Cycling on VT

After cycling 1000 cycles Erase and Program VTs maintain tight distribution.

Summary

Produced in 90nm .25um technology Operation voltages 6V 90% yield on 4 MB array