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FINITE STATE MACHINES (FSM)
DESCRIPTION IN VHDL
Cristian Sisterna
UNSJ
FSM Review
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A sequential circuit that is implemented in a fixed number of possible states is called a Finite State Machine (FSM).
Finite state machines are critical for realizing the control and decision-making logic in a digital system.
Finite state machines have become an integral part of the system design.
VHDL has no formal format for modeling finite state machines.
To model a finite state machine in VHDL certain guidelines must be followed.
FSM Example
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Realizar la descripción en VHDL de un receptor y transmisor serie
tipo RS-232. El dato recibido y el dato a transmitir debe tener el
siguiente formato:
1 bit de start
8 bits de datos
Paridad programable: paridad/no paridad, par/impar
1 bit de stop
Frecuencia de transmisión por defecto es de 9600 Bauds, pero
el código debe permitir también otras frecuencias como: 4800,
38400, 115200 Bauds.
FSM Example
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RS-232 Tx format
State Machine State Diagram
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FSM General Schemes
Cristian SisternaFSM - DSDA
State Machine General Scheme 1
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OutputsInputs
Next
State
Logic
Current
State
Logic Current
State
Next
State
Output
Logic
Clk
Rst
Next State
Logic
Current
State Logic
Output
Logic
State Machine General Scheme 2
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Outputs
Next
State
InputsNext
State
Logic
Current
State
Logic
Current
State Output
Logic
Clk
Rst
Sync
Output
FFs
Next
State
Logic
Current
State
Logic
Output
Logic
Synchr.
Output
Logic
State Machine General Scheme 3
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Output A
Next
State
InputsNext
State
Logic
Current
State
Logic
Current
State
Clk
Rst
Output Z
. . .
. . .
Next
State
Logic
Current
State
Logic
Synchr. and
Output Logic
Synchr. and
Output Logic
State Machine - Special Case 1
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Outputs
Next
State
InputsNext
State
Logic
Current
State
LogicCurrent
State
Clk
Rst
Sync
Output
FFs
Next
State
Logic
Current
State
Logic
Synchr.
Output
Logic
FSM – VHDL Considerations
Cristian SisternaFSM - DSDA
FSM VHDL General Design Flow
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Specifications
Understand the Problem
Draw the ASM or State Diagram
Define an FSM Enumerated Type
Define FSM Signals
Select an Encoding Technique (optional)
Write the VHDL Code
Traditional Steps
VHDL Steps
+
FSM Enumerated Type Declaration
Cristian SisternaFSM - DSDA
FSM Enumerated Type Declaration
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Declare an enumerated data type with values (names) the states of
the state machine
The only values that current_state and next_state can hold are:
IDLE,START,STOP_1BIT,PARITY,SHIFT
-- declare signals of FSM_States type
signal current_state, next_state: FSM_States;
-- declare the states of the state-machine
-- as enumerated type
type FSM_States is(IDLE,START,STOP_1BIT,PARITY,SHIFT);
Declare the signals for the next state and current state of the state
machine as signal of the enumerated data type already defined
for the state machine
Symbolic State Names
FSM – Encoding Techniques
FSM Encoding Techniques
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State Assignment
During synthesis each symbolic state name has to be
mapped to a unique binary representation
A good state assignment can reduce the circuit size
and increase the clock rate (by reducing
propagation delays)
The hardware needed for the implementation of
the next state logic and the output logic is directly
related to the state assignment selected
type FSM_States is(IDLE, START, STOP_1BIT, PARITY, SHIFT);
signal current_state, next_state: FSM_States;
FSM Encoding Schemes
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An FSM with n symbolic states requires at least [log2 n ]
bits to encode all the possible symbolic values
Commonly used state assignment schemes:
Binary: assign states according to a binary sequence
Gray: use the Gray code sequence for assigning
states
One-hot: assigns one ‘hot’ bit for each state
Almost one-hot: similar to one-hot but add the all
zeros code (initial state)
FSM Encoding Schemes
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Binary Gray One-Hot Almost One-hot
idle 000 000 00001 0000
start 001 001 00010 0001
stop_1bit 010 011 00100 0010
parity 011 010 01000 0100
shift 100 110 10000 1000
Encoding Schemes in VHDL
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How is the map process done ?
During synthesis each symbolic state name has to be
mapped to a unique binary representation
user attribute (synthesis attribute)
enum_encoding(VHDL standard
explicit user-defined assignment
default encoding
syn_encoding – Quartus & Synplify
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• syn_encoding is the synthesis user-attribute of Quartus
(Synplify) that specifies encoding for the states modeled by an
enumeration type
• To use the syn_encoding attribute, it must first be
declared as string type. Then, assign a value to it, referencing
the current state signal.
-- declare the (state-machine) enumerated type
type my_fms_states is (IDLE,START,STOP_1BIT,PARITY,SHIFT);
-- declare signals as my_fsm_states type
signal nxt_state, current_state: my_fsm_states;
-- set the style encoding
attribute syn_encoding: string;
attribute syn_encoding of my_fms_states : type is “one-hot”;
syn_encoding - Quartus & Synplify
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Possible values:
default: assign an encoding style based on the number of states:
Sequential encoding for 0 - 4 enumerated types
One-hot encoding for 5 – 50 enumerated types
Gray encoding for > 50 enumerated types
sequential: 000 001 010 011 100 101 110 111
one-hot: 0000001 00000010 00000100 . . .
gray: 000 001 011 010 110 111 101 100
johnson : 0000 0001 0011 0111 1111 1110 1100 1000
safe: default encoding + reset logic to a known state
attribute syn_encoding: string;
attribute syn_encoding of my_fms_states: type is “one-hot, safe”;
user-defined: assign an encoding style defined by the userattribute syn_encoding: string;
attribute syn_encoding of my_fms_states: type is “10 11 01 00”;
Examples of Synthesis Reports (Quartus)
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Results for Different Encoding Schemes
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One-hot
safe
One-hot Gray Gray-Safe Binary Johnson
Total
combinatio
nal
functions
76 66 66 68 66 68
Dedicated
logic
registers
45 45 43 43 43 43
Max. frq. 352.24 340.95 331.02 335.01 338.34 311.72
Simple, 5 states, state machine
Results for Different Encoding Schemes
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One-hot
safe
One-hot Gray Gray-Safe Binary Johnson
Total
combinati
onal
functions
556 523 569 566 561 573
Dedicated
logic
registers
215 215 201 201 201 206
Max. frq. 187.3 175.22 186.39 180.6 197.63 186.22
19 states, state machine
Xilinx XST State Encoding Techniques
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Auto-State Encoding
One-Hot Encoding
Gray State Encoding
Compact State Encoding
Johnson State Encoding
Sequential State Encoding
Speed1 State Encoding
User State Encoding
XST (the synthesis tool for ISE) supports the following
state encoding techniques:
XST State Encoding Techniques
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Declare the attribute as follows:
attribute fsm_encoding: string;
Specify as follows:
attribute fsm_encoding of {entity_name|signal_name }:
{entity |signal} is "{auto | one-hot | compact|
sequential| gray| Johnson | speed1|user}";
The default is auto
Precision State Encoding Techniques
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Possible values:
• Binary
• Onehot
• Twohot
• Gray
• Random
-- Declare the (state-machine) enumerated type
type my_state_type is (SEND, RECEIVE, IGNORE, HOLD, IDLE);
-- Set the type_encoding_style of the state type
attribute type_encoding_style of my_state_type:type is ONEHOT;
Declare the attribute as follows:
attribute type_encoding_stype string;
Note: precision is a synthesis tool available in some FPGA vendor’s software
Precision State Encoding Techniques
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type_encoding_style allows to fully control the state
encoding hard code the state code in the source code
-- Declare the (state-machine) enumerated type
type my_state_type is (SEND, RECEIVE, IGNORE, HOLD, IDLE);
-- Set the type_encoding attribute
attribute type_encoding_style of my_state_type:type is
("0001","01--","0000","11--","0010");
State
Table
Note: Precision allows to use ‘-’. It can be used to reduce the size of the circuit
State Machine Coding: Residual States
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If one-hot state coding is not used, the maximum number of states is equal to 2**N, where N is the vector length of the state vector
In state machines where not all the states are used, there are three options:
Let chance decide what is to happen if the machine goes to an undefined state
Define what is to happen if the state machine goes to an undefined state by ending the case statement with when others
Define all the possible states in the VHDL code
State Machine Coding: Synplify Report
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State Machine Coding: XST Report
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==============================================
* Advanced HDL Synthesis *
==============================================
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <rs232_tx/tx_current_state/FSM> on signal
<tx_current_state[1:3]> with sequential encoding.
-----------------------------
State | Encoding
-----------------------------
idle | 000
start | 001
shift | 010
parity | 011
stop_1bit | 100
-----------------------------
State Machine Coding: Quartus Report
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State Machine Coding: Simulation
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FSM Style Description Example
State Machine VHDL Coding Styles
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Coding Style Current State Next State Logic Output Logic
Style E Seq. Logic Comb. Logic Seq. Logic
Style A Seq. Logic Comb. Logic Comb. Logic
Style C Seq. Logic Comb. Logic
Style D Seq. Logic Comb. Logic
Style B Seq. Logic
OutputsInputs
Next
State
Logic
Current
State
Logic Current
State
Next
State
Output
Logic
CLK
RST
Next
State
Logic
Current
State
Logic
Output
Logic
FSM: Clocked Process for Current State
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The current_state clocked process decides when the state machine
should change state
This process is activated by the state machine’s clock signal
Depending on the current state and the value of the input signals,
the state machine can change state at every active clock edge
Current state gets the value of the next state on the active edge of
the clock
The next state value is generated in the next state process
(combinational process), depending on the values of current state
and the inputs
FSM: Combinational Process
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Assigns the output signals their value depending on the current state
Assigns the next state value depending on the current state and the
input’s value(s)
Next state logic and output logic is best modeled using case
statements are better for this process
All the rules of combinatorial process have to be followed to avoid
generating unwanted latches
For Mealy Machines if-then-else statement is used to create
the dependency between the current state, the input signals and
output signals
Next State and Output Logic
State Machine: Reset behavior
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Asynchronous reset: ensure that the state machine
is always initialized to a known valid state, before
the first active clock transition and normal operation
commences
No reset : there is no way to predict the initial value
of the state register flip-flops. It could power up
and become permanently stuck in an uncoded state.
FSM Style Descriptions - Example
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S1S0X = 1Z = 1
X = 0Z = 0
X = 1Z = 0
X = 0Z = 1
S1Z = 1
S0Z = 0 X = 1X = 0
X = 1
X = 0
Mealy FSM
Moore FSM
Seq. Output Logic
Z
Style E - Moore State Machine
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process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
Z <= ‘0’;
when S1 =>
Z <= ‘1’;
when others =>
Z <= ‘1’;
end case;
end process;
Comb. Next State Logic
Seq. Present State Logic
Clk
Rst
X
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
state
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
Current
State Logic
Output
Logic
Seq. Output Logic
Z
Style E - Moore State Machine
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Comb. Next State Logic
Seq. Present State Logic
Clk
Rst
Xstate
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk))
then
state <= next_state;
end if;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
Z <= ‘0’;
elsif (rising_edge(clk))
then
case state is
when S0 =>
Z <= ‘0’;
when S1 =>
Z <= ‘1’;
when others =>
Z <= ‘1’;
end case;
end process;
Style E - Moore State Machine
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-- VHDL code example for an FSM
library ieee;
use ieee.std_logic_1164.all;
entity my_fsm is
port(
x: in std_logic;
clk: in std_logic;
rst: in std_logic;
z: out std_logic );
end entity my fsm;
architecture beh of my_fsm is
-- fsm enumerated type declaration
type fsm_states is (S0, S1);
-- fsm signal declarations
signal next_state, state: fsm_states;
begin
-- current state logic
cst_pr: process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process cst_pr;
-- next state logic
nxt_pr:process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process nxt_pr;
- - output logic
out_pr:process (clk, rst)
begin
if(rst = ‘1’) then
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 => Z <= ‘0’;
when S1 => Z <= ‘1’;
when others => Z<= ‘1’;
end case;
end process out_pr;
end architecture beh;
Style E - Mealy State Machine
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Z
Comb.Next State Logic
Seq.Present State Logic
Seq. Output Logic
Clk
Rst
X
state
Warning on Mealy Outputs !
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk))
then
state <= next_state;
end if;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if (X = ‘0’) then
Z <=…;
else
Z <=... ;
end if;
when S1 =>
if (X = ‘1’) then
.... ;
else
.... ;
end if;
when others =>
Z<=‘0’;
end case;
end if;
end process;
Comb.Output LogicSeq. Present State Logic
Comb. Next State Logic
Style A - Moore State Machine
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Z
Clock
X
Reset
state
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk))
then
state <= next_state;
end if;
end process;
process (state)
begin
Z <= ‘0’; -- default value
case state is
when S0 => Z <= ‘0’;
when S1 => Z <= ‘1’;
when others => Z <= ‘0’;
end case;
end process;
Style A – Moore Synthesis
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Style A - Mealy State Machine
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Z
Comb. Next State Logic
Seq. Present State Logic
Comb. Output Logic
Clock
Reset
X
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process;
process (state, X)
begin
case state is
when S0 =>
if (X = ‘0’) then
Z <=…;
else
Z <=... ;
end if;
when S1 =>
if (X = ‘1’) then
.... ;
else
.... ;
end if;
when others =>
Z<=‘0’;
end case;
end process;
Style A – Mealy Synthesis
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Mealy
Comb. Output Logic - Mealy
Style A – Moore & Mealy State Machine
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Z
Comb. Next State Logic
Seq. Present State Logic
Clock
Reset
X
Comb.Output Logic Moore
Y
Hypothetical case
process (state, X)
begin
case state is
when S0 =>
if(X=‘0’) then
next_state <= S0;
else(X=‘1’) then
next_state <= S1;
end if;
when S1 =>
if ….
next_state <= .. ;
….
when others =>
….
end case;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process;
process (state, X)
begin
case state is
when S0 =>
if (X = ‘0’) then
Z <=…;
...
end if;
when S1 =>
if (X = ‘1’) then
.... ;
end if;
when others =>
Z<=‘0’;
end case;
end process;
process (state)
begin
case state is
when S0 => Y <= ‘1’;
when S1 => Y <= ‘0’;
when others => Y <= ‘0’;
end case;
end process;
Style B - Moore State Machine
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X Z
Seq. State, Next State and Output Logic
Clk
Rst
process(clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if (X=’0’) then
state <= S0;
elsif (X=’1’) then
state <= S1;
end if;
Z <=‘0’;
when S1 =>
if (X = ‘0’) then
. . .
end if;
Z <= ‘1’ ;
end case;
end if;
end process;
Style B - Mealy State Machine
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XZ
Seq. State, Next State and Output Logic
Clock
Reset
process(clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
Z <= ‘0’;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if (X=’0’) then
state <= .... ;
Z <= ... ;
elsif (X=’1’) then
state <= .... ;
Z <= ... ;
end if;
when S1 =>
if (X = ‘0’) then
. . .
end if;
end case;
end if;
end process;
Style B – Moore Synthesis
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Style B – Mealy Synthesis
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Comb. Output Logic
Style C - Moore State Machine
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Z
Seq. Present State and Next State Logic
Clk
X
Rst
process (clk, rst)
begin
if(rst = ‘1’) then
State <= S0;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if(X =’1’) then
state <=S1;
end if;
when S1 =>
if( X = ‘1’) then
state <=S0;
end if;
end case;
end if;
end process;
process (state)
begin
case state is
when S0 => Z <=‘0’;
when S1 => Z <=‘1’;
when others Z <=‘0’
end case;
end process;
Seq. Present State and Next State Logic
Style C - Mealy State Machine
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Z
Comb. Output Logic
Clk
X
Rst
process (clk, rst)
begin
if(rst = ‘1’) then
State <= S0;
elsif (rising_edge(clk)) then
case state is
when S0 =>
if(X =’1’) then
state <=S1;
end if;
when S1 =>
if( X = ‘1’) then
state <=S0;
end if;
end case;
end if;
end process;
process (state, X)
begin
case state is
when S0 =>
if(X=’1’) then
Z <= ... ;
else
Z <= ... ;
end if;
when S1 =>
if(X=’1’) then
Z <= ... ;
else
Z <= ... ;
end if;
end case;
end process;
Style C – Moore State Machine
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Style C - Mealy State Machine
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Comb. Next State and Output Logic
Style D - Moore State Machine
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Z
Seq. Present State Logic
Clk
X
Rst
process (state, X)
begin
next_state <= state;
case state is
when S0 =>
if(X =’1’) then
next_state <=S1;
end if;
Z <=‘0’;
when S1 =>
if( X = ‘1’) then
next_state <=S0;
end if;
Z <=‘1’;
end case;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process;
Style D - Mealy State Machine
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Z
Comb. Next State and Output Logic
Seq. Present State Logic
Clk
X
Rst
process (state, X)
begin
next_state <= state;
Z <= ... ;
case state is
when S0 =>
if(X =’1’) then
next_state <= ... ;
Z <= ... ;
end if;
when S1 =>
if( X = ‘1’) then
next_state <= ... ;
Z <= ... ;
end if;
end case;
end process;
process (clk, rst)
begin
if(rst = ‘1’) then
state <= S0;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process;
Style D – Moore State Machine
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59
Style D - Mealy State Machine
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60
FSM Example
Cristian SisternaFSM - DSDA
Another Example: Memory Controller FSM
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Let’s try to obtain an state diagram of a hypothetical memory controller FSM that has the
following specifications:
The controller is between a processor and a memory chip, interpreting commands from the
processor and then generating a control sequence accordingly. The commands, mem, rw and
burst, from the processor constitute the input signals of the FSM. The mem signal is asserted to
high when a memory access is required. The rdwr signal indicates the type of memory access,
and its value can be either ’1’ or ’0’, for memory read and memory write respectively. The
burst signal is for a special mode of a memory read operation. If it is asserted, four
consecutive read operations will be performed. The memory chip has two control signals, oe
(for output enable) and we (for write enable), which need to be asserted during the memory
read and memory write respectively. The two output signals of the FSM, oe and we, are
connected to the memory chip’s control signals. For comparison purpose, let also add an
artificial Mealy output signal, we_mealy , to the state diagram. Initially, the FSM is in the idle
state, waiting for the mem command from the processor. Once mem is asserted, the FSM
examines the value of rdwr and moves to either the read1 or the write state. The input
conditions can be formalized to logic expressions, as shown below:
mem’ : represents that no memory operation is required (mem=‘0’)
mem.rdwr: represents that a memory read operation is required (mem=rdwr=‘1’).
mem.rdwr’: represents that a memory write operation is required (mem=‘1’; rdwr=‘0’)Based on an example from the “RTL Hardware Design Using VHDL” book, By Pong Chu
Memory Controller FSM
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Processor
Memory
Controller FSM
Memory IC
Data Bus
Address Bus
mem
burst
rdwr
oe
we
we_mealy
Memory Controller FSM
Cristian SisternaFSM - DSDA
64
mem’
read1
read2
read3
read4
mem.rdwr
burst’
idle
write
we
oe
oe
oe
oe
mem.rdwr’
we_mealy
burst
Memory Controller FSM
Cristian SisternaFSM - DSDA
65
mem
rdwr
we_mealy
we
oe
burst
oe
oe
oe
idle
write
read1
read2
read3
read4
Memory Controller FSM – VHDL Code
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66
Entity-Architecture Declarations
FSM enumeration type declaration, FSM signal declarations
library ieee ;
use ieee.std_logic_1164.all;
entity mem_ctrl is
port (
clk, reset : in std_logic;
mem, rdwr, burst: in std_logic;
oe, we, we_mealy: out std_logic
);
end mem_ctrl ;
architecture mult_seg_arch of mem_ctrl is
type fsm_states_type is
(idle, read1, read2, read3, read4, write);
signal crrnt_state, next_state: fsm_states_type;
begin
Memory Controller FSM – VHDL Code
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67
Current state process
−− current state procesee
cs_pr: process (clk, reset)
begin
if(reset = ’1’) then
crrnt_state <= idle ;
elsif(rising_edge(clk))then
crrnt_state <= next_state;
end if;
end process cs_pr;
Memory Controller FSM – VHDL Code
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Next state process (1)
−− next−state logic
nxp:process(crrnt_state,mem,rdwr,burst)
begin
case crrnt_state is
when idle =>
if mem = ’1 ’ then
if rw = ’1’ then
next_state <= read1;
else
next_state <= write;
end if;
else
next_state <= idle;
end if;
when write =>
next_state <= idle;
Memory Controller FSM – VHDL Code
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Next state process (2)
when read1 =>
if (burst = ’1’) then
next_state <= read2;
else
next_state <= idle;
end if;
when read2 =>
next_state <= read3;
when read3 =>
next_state <= read4;
when read4 =>
next_state <= idle;
when others =>
next_state <= idle;
end case;
end process nxp;
Memory Controller FSM – VHDL Code
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70
Moore outputs process−− Moore output logic
moore_pr: process (crrnt_state)
begin
we <= ’0’; −− default value
oe <= ’0’; −− default value
case crrt_state is
when idle => null;
when write =>
we <= ’1’;
when read1 =>
oe <= ’1’;
when read2 =>
oe <= ’1’;
when read3 =>
oe <= ’1’;
when read4 =>
oe <= ’1’;
when others => null;
end case ;
end process moore_pr;
Memory Controller FSM – VHDL Code
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Mealy output process−− Mealy output logic
mly_pr: process(crrt_state,mem,rdwr)
begin
we_me <= ’0’; −− default value
case state_reg is
when idle =>
if (mem=’1’)and(rdwr =’0’)then
we_me <= ’1’;
end if;
when write => null;
when read1 => null;
when read2 => null;
when read3 => null;
when read4 => null;
end case;
end process mly_pr;
Memory Controller FSM – VHDL Code
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Mealy output statement
−− Mealy output logic
we_me <= ’1’ when ((crrnt_state=idle) and (mem=’1’) and(rdwr=’0’))
else
’0’;
Another Example
Cristian SisternaFSM - DSDA
FSM Example – RS232
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74
Realizar la descripción en VHDL de un receptor y transmisor serie
tipo RS-232. El dato recibido y el dato a transmitir debe tener el
siguiente formato:
1 bit de start
8 bits de datos
Paridad programable: paridad/no paridad, par/impar
1 bit de stop
Frecuencia de transmisión por defecto es de 9600 Bauds, pero
el código debe permitir también otras frecuencias como: 4800,
38400, 115200 Bauds.
FSM Example – RS232
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RS-232 Tx format
FSM Example – RS232
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FSM
RS232 Tx Controller
Parity
DatoSent
StartTx
SysClock
SysReset
Dato(7:0)
DatoSerie
En
Div.
Frec.
??
FSM Example – RTL Synthesis View
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FSM Example – Quartus State diagram
Cristian SisternaFSM - DSDA
78
FSM Example: Solution 2 - RTL Viewer
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79
RTL Viewer
Double click
FSM Example: Solution 2- RTL Viewer
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Double click
FSM Example: Solution 2 – FSM Viewer
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81
Synpsys FSM Viewer
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In this case a clock enable is used.
FSM Example – RS232 Other Approach
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Reg
Desplaz
amiento
FSM
RS232 Tx Controller
Parity
DatoSent
StartTx
SysClock
SysReset
Dato(7:0)
StartStopBit
Sel1, Sel0
Done
00
01
10
E1
E0
DatoSerie
En
Div.
Frec.
??
Interacting State Machines
Interacting FSM
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CS1
CS2
CS3
Ld_Tx
Tx_busy’
Tx_busy
TS2
TS1
TS3
TS4
Tx_busy
Ld_Tx’
Transmitter FSMController FSM
Tx_busy
Tx_busyTx_busy’
Ld_Tx’
Interacting FSM
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Outputs
Inputs
Next
State
Process
Current
State
ProcessCurrent
State
Next
State
Output
Process
Clk
Rst
OutputsInputs
Next
State
Process
Current
State
Process
Current
State
Next
State
Output
Process
Tx_busy
Ld_Tx
Transmitter
FSM
Processes
Controller
FSM
Processes
ctrl_tx.vhd
Interacting FSM
Cristian SisternaFSM - DSDA
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Outputs
Inputs
Next
State
Process
Current
State
ProcessCurrent
State
Next
State
Output
Process
Clk
Rst
OutputsInputs
Next
State
Process
Current
State
Process
Current
State
Next
State
Output
Process
Tx_busy
Ld_Tx
tx_fsm.vhd
cntrl_fsm.vhd
Recommended