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Expert Layout Editor
Technical Description
Expert Layout Editor
Agenda
Expert Layout Editor Overview General Layout Editing Features Technology File Setup Multi-user Project Library Setup Advanced Programmable Features Schematic Netlist Driven Layout Parameterized Cell (Pcell) Development Real -Time DRC Design for Manufacturing - Cross Section Viewer
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Expert Layout Editor
Expert Layout Editor
Productive layout environment for analog, RF, microwave, and digital layouts
Flexible tuning to different IC technologies: CMOS, Bipolar, BiCMOS, SiGe, GaAs, InP and other unique processes
Extremely fast loading, viewing and editing operation for multi-million transistor designs regardless available memory
Integrated verification tools (DRC/ERC/LVS) for interactive or batch operation
Parameterized cells (Pcells) using the powerful LISA scripting language
Same intuitive interface across Solaris, Linux, and Windows platforms
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Expert Layout Editor
Expert Inputs and Outputs
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Accepts GDSII, LEF/DEF, CIF, Applicon and OASIS
Expert Layout Editor
Multi-Window Hierarchical Editing: Three Level View of Chip Hierarchy
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Project Hierarchy Tree
Cell Map
Level 1
Level 2
Design Bar
Layer Bar
Level 6
Hierarchy Level (6 of 9)
Expert Layout Editor
Hierarchical Editing: Top Level with Routing
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Hierarchy Level (4 of 13)
Expert Layout Editor
Hierarchical Floorplan View
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Hierarchy Level (4 of 13)
Expert Layout Editor
Hierarchical Editing – 6th Level with Routing
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Hierarchy Level (6 of 13)
Expert Layout Editor
Easy to Adopt and Use
Customizable hotkeys, macros, and toolbars may be set to emulate the look and feel of Virtuoso environment for layout designers
Process Design Kits (PDKs) from foundries enable quick start-up of new design environments
Informative, easily accessible online help for all menus and icons Linux and Windows availability enables wide deployment on
economy workstations Simple installation process does not require consultants to set
up environment Cross-platform floating license system with support for Virtual
Network Connection (VNC) for distribute offices Drives wide selection of printers and plotters (HP, Gerber,
Versatech) with multi-page tiling based on paper size
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Expert Layout Editor
High-End Layout Editing Capabilities
Library management and multi-user environment Facilitated technology migration Electrical hierarchical node probing Netlist-driven layout with parameterized cells (Pcells) Numerous productivity enhancers (gravity, reference points, pre-
selection, layer plans, etc.) Intelligent geometry database, offering fast processing speed
and low memory requirements Arbitrary geometric shapes for device creation and DRC checks
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Expert Layout Editor
All-Angle Features
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All angle geometries Rounded corners Text tags Rulers Derived layers Functions Useful for RF & MEMS
Expert Layout Editor
Powerful Functions For Customization and Porting
Create parameterized cells (Pcells) with the LISA scripting and graphical support
Powerful C++ API can access all editing functions Auto scaling and resize feature minimizes process migration
efforts Powerful hierarchical search Productivity for Power Users
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Expert Layout Editor
Hierarchical Search with Edit in Place
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Search Criteria
Search Window
Edit in Place
Found Object Properties
Expert Layout Editor
Interoperable with Popular Design Flows
Directly imports Calibre®, Dracula®, and Diva™ DRC/ERC/LVS rule decks
Reads Calibre® and Dracula error reports for Result Viewing Environment (RVE)
Technology file import from Virtuoso™ for layers, colors, stipples Customizable hotkeys, macros, and toolbars for familiar look and
feel Imports legacy designs with GDSII, Applicon and CIF data
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Expert Layout Editor
Calibre® Error Database and Expert Error Review
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Expert Layout Editor - 16 -
Easy Technology File Setup with Virtuoso® Import - Main Layer Setup Window with GDS Layers
Layer Setup
Stipple Selector
Edit Stipple Bitmap
Select Colors
Setup Menu
Choose Setup of Colors, Stipples, View Style
Expert Layout Editor
Library Types in Expert
Personal design (exclusive access) allow one user edit mode while all others in view mode
Read-only libraries (completed, reusable designs) Used with Process Design Kits (PDKs) Prevents modifications
Shared libraries, for multi-user concurrent access Check-in, check-out library manager enables designers to
simultaneously work on the same project across a network Used for teams completing large chips, by area, before final tapeout Permissions can be set per user
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Expert Layout Editor
Multi-User Shared Library Environment with Expert
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Cell List and Status
Shared and Exclusive Libraries
Shared Library Setup
Check-in Check-out
Expert Layout Editor
Data Safety Setup
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Main Setup Menu
Auto-save option
Automatic Backup
Undo Level
Cell & Project Safety Options For Shared and Exclusive Libraries
Activity Log Options
Recovery Files
Expert Layout Editor
Customizable GUI
Many buttons/toolbars/controls on screen, online help Custom bindkeys/menu/colors Customizable layer plans Easy customizable menu by LISA script command Powerful C++ interface allow create additional functional module
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Expert Layout Editor
DRC Guard: Real-Time DRC
Instant DRC checks during editing Convenient navigation over error markers Efficient utilization of multiprocessing capabilities Real-time feedback for DRC errors while editing Tightly integrated into Expert Same rule set of Guardian DRC Free limited DRC (10 rules) with each Expert license
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Expert Layout Editor
Real-Time DRC
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Real-Time DRC bar (Error Navigator)
If an user sets up Real-Time DRC rule set then during every editing layout, changes will be checked against these rules
Real-Time error indicator
Expert Layout Editor
Highlighting Multiple Nets Simultaneously to Find Opens
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Real-time Connectivity Extraction
Expert Layout Editor
Multi-point Probing Locates Shorts
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Real-time Connectivity Extraction
Expert Layout Editor
Schematic Netlist Driven Layout
Import Spice-Netlist file Generate Pcells using parameters from Netlist file Automatically initial placement cells Store connectivity information in layout Point-to-point wiring Show unfinished, shorted nets
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Expert Layout Editor
Schematic Netlist Driven Layout
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Cell Hierarchy
Netlist
Instanciated Cells
Netlist Hierarchy Flight Lines
External Nets
Expert Layout Editor
Powerful Scripting Language for Expert (LISA)
LISA: Language for Interfacing Simucad Applications Supports all high-level program flow controls Provides means for defining custom commands
XI-scripts (Expert Interface scripts) Extension of LISA by Expert application-specific tools Provide access to any objects and editing operations
Parameterized Cells (Pcells) Parameterized construction of cells by custom commands Creating shapes of any complexity Powerful stretch, repeat, and layer commands
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Expert Layout Editor
Parameterized Cells (Pcells)
Pcells can be created either Textual or Graphical
Graphical Pcells are generated automatically by specifying values for predefined parameters: Stretch Repetition Layer For quick and intuitive creation of
simple Pcells Textual P-cells for complex structures
with Powerful LISA/Xi scripting language
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Expert Layout Editor
Pcells Construction with Xi Scripting – MOS Xistor
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Geometry With Default Parameters
Xi Script
Expert Layout Editor
Complex Shapes by Xi-Scripts – Spiral Inductor
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Geometry With Default Parameters
Xi Script
Expert Layout Editor
Creating Textual Pcells with Xi Scripting
Create new textual Pcell by menu command Pcell>>New>>Textual
Xi-script editor will be activated with predefined skeleton for Pcell definition
Create textual Pcell from scratch in the Xi-script editor using predefined Xi command DEFINE PCELL
Edit textual Pcell parameters and body Xi-script manually Run Xi-script to create new or modify existing Pcell
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Expert Layout Editor
Graphical Pcell Functions
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Add Layer
Stretch
Repetition
Expert Layout Editor
Graphical Pcell Parameter Setting
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Expert Layout Editor
Cross-Sectional Viewer for DFM
Cross-Sectional Viewer within Expert simulates the cross sectional view of ICs along an arbitrary drawn cut-line on the layout
Cross sectional drawings are useful for understanding design rules, parasitic coupling and other design and fabrication problems
Design for Manufacturing and Yield Analysis
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Expert Layout Editor
Cross-Sectional Viewer Setup
Process simulation parameters Set manually by
editing Expert technology file
Set interactively using Cross Sectional Viewer setup page of the Expert Preferences dialog panel
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Layer { Name = "NWELL" ... Material { ... Thickness = 4 } ... Processing { ProcessingStep = 1 Operation = DIFFUSE Undercut = 0 Angle = 100 } }
Expert Layout Editor
Cross-Sectional Viewer for DFM and Yield Analysis
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Cut Line in Expert
Mirrors Cell View In Cross Section View
Expert Layout Editor
Cross-Sectional Viewer Access
Docking Window Cross Section adds, deletes and chooses viewing
Multiple Cut Cross-Sectional Viewer enables: View the fabrication processes one step at time Choose first, last, next, and previous fabrication step Zoom current cross section view for convenient investigation of
specific sections
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Expert Layout Editor
Conclusion
Expert Layout Editor creates all-angle polygons for analog, RF, and microwave circuit elements, including inductors and power devices in CMOS, Bipolar, BiCMOS, SiGe, GaAs, SiC, InP, TFT, and other process technologies
Expert Layout Editor enables mask designers to achieve maximum density and performance in analog and digital layouts
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