EET3350Lec15 Counters

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EET 3350 Digital Systems Design

Textbook: John WakerlyChapter 8: 8.4

Counters

Agenda for Today

• Counters – Definition– Types– Characteristics

• Asynchronous Counters• Synchronous Counters• MSI Counters

– Especially the 74LS163

• Counters in VHDL• Other Counter Types

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Clock Count

optional inputs

Counter

Sm

S1 S2S3

S4S5

Counters

• A counter is a circuit that produces a numeric count each time an input clock pulse makes an active transition

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Clock Count

optional inputs

Counter

Load an initial value, reset Load an initial value, reset to starting count, etc.to starting count, etc.

May also enable count, May also enable count, select direction, etc.select direction, etc.

Counter• From another viewpoint, a counter is any sequential

circuit whose state diagram is a single cycle– in other words, counters are a special case of a finite state

machine

• Output is usually the state value, Moore machine

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Sm

S1 S2S3

S4

S5

EN EN

EN

ENEN

EN

RESET

EN

EN

EN EN

EN

ENEN

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Counters

Characteristic Description

Modulus Length of sequence

Coding Count sequence

Direction Up or down

Resetable Reset to zero

Loadable Load a specific value

• Counters differ by a number of basic characteristics, including:

Counters

• Applications include:– system clock– timer, delays– watches, clocks, alarms– counting events– memory addressing – frequency division – sequence control– cycle control– protocols

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Present State Next State A B A B

0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0

00 01

1011

Counter Types

• Asynchronous– Ripple

• Synchronous– Clocked

• Modulus – Binary– Decade – etc.

• Ring • Johnson

– Twisted ring

• Up/Down• LFSR

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001

010

011

100

101

000

Counters

• Some examples of modulus and coding sequence for counters

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Counters

• Modulus– number of states in a counter’s cycle

• Given m states– modulo-m counter or divide-by-m counter

• Power-of-2 counters use all states• Non-power-of-2 counters have extra, unused

states

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Sm

S1 S2S3

S4

S5

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Example 4-bit Counters

• 4-bit Binary / Hex / Mod-16 Counter– 0000, 0001, 0010, … 1110, 1111, 0000, 0001, …

• 4-bit BCD / Decade / Mod-10 Counter– 0000, 0001, 0010, … 1000, 1001, 0000, 0001, …

• 4-bit Ring Counter– 1000, 0100, 0010, 0001, 1000, 0100, …

all states used

six unused states

twelve unused states

Counters

• Ripple counters– asynchronous– an n-state counter that is formed from n cascaded

flip-flops – the clock input to each of the individual flip-flops,

with the exception of the first, is taken from the output of the preceding one

– the count thus ripples along the counter's length due to the propagation delay associated with each stage of counting

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Asynchronous Ripple Counter

Q3 Q2 Q1 Q0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0

Q0

Q1

Q2

Q3

...

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Ripple Counter Timing• The ideal count sequence for the ripple counter

yields the timing diagram below

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Q0

Q1

Q2

Q3

Q0 Q1 Q2 Q3

CLOCK

Ripple Counter Timing

CLK

Q0

0 1 2 3 4

1

2

3Q2

Q1

• But there is delay ( ) as shown below:

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Asynchronous Ripple Counter

Q0

Q1

Q2

Q3

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divide-by-2

divide-by-4

divide-by-8

divide-by-16

a T flip-flop is a a T flip-flop is a natural frequency natural frequency divider …divider …

Synchronous Counters

• Asynchronous counters are easy to understand, but avoid their use– slow, limited by propagation delays– error prone

• Characteristics of synchronous counters– use a common clock pulse to trigger all flip-flops

simultaneously– have a higher clock speed– hardware is more complex but more reliable

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LSB

MSB

Synchronous counter

serial enable logic

4-Bit Counter

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Synchronous counter

LSB

MSB

parallel enable logic

4-Bit Counter

MSI Counters

• Counters can be built from individual SSI Flip-Flops, e.g.,– 7470– 7474– 7479

• Counters may also be built using MSI components– 74x90, 74x92, 74x93– 74x160, 74x161, 74x162, 74x163– 74x168, 74x169– 74x190, 74x191– 74x196, 74x197

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and many others …

74x163

we’ll look at this onewe’ll look at this one

D1 D2

MSI Counter

• 4-bit synchronous counter– edge-triggered– synchronously

presettable– cascadable

• Typical Count Rate of 35 MHz

• ‘160 and ‘162, Mod-10• ‘161 and ‘163, Mod-16

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MSI Counter

• 74LS163 4-bit synchronous counter

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16-pin DIP16-pin DIP

MSI Counter

• 74LS163 characteristics– edge-triggered– synchronously presettable– cascadable– count modulo 16 (binary)

• Synchronous Reset (Clear) input that overrides all other control inputs– active only during the rising

clock edge

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74x163

MSI Counter

• 74LS163 logic symbols

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74x163texttext

datasheetdatasheet

MSI Counter

• 74LS163 state diagram and logic equations

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MSI Counter

• 74LS163 mode select table• All signals must be high ( H ) to enable the

count sequence to begin

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MSI Counter• 74x163 is a synchronous

4-bit binary counter• RCO=1 when all count

bits are 1 and ENT is asserted

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MSI Counter

• The control inputs for the 74x163 have the following effects:

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clear

loadhold

hold

MSI Counters• 7458: Dual 4-bit Decade Counter

• 7459: Dual 4-bit Binary Counter

• 7468: Dual 4 Bit Decade or Binary Counters

• 7469: Dual 4 Bit Decade or Binary Counters

• 7490: Decade Counter (separate Divide-by-2 and Divide-by-5 sections)

• 7492: Divide-by-12 Counter (separate Divide-by-2 and Divide-by-6 sections)

• 7493: 4-bit Binary Counter (separate Divide-by-2 and Divide-by-8 sections)

• 74142: Decade Counter/Latch/Decoder/Nixie Tube Driver

• 74143: Decade Counter/Latch/Decoder/7-segment Driver, 15 mA Constant Current

• 74144: Decade Counter/Latch/Decoder/7-segment Driver, 15V open collector outputs

• 74160: Synchronous 4-bit Decade Counter with Asynchronous Clear

• 74161: Synchronous 4-bit Binary Counter with Asynchronous Clear

• 74162: Synchronous 4-bit Decade Counter with Synchronous Clear

• 74163: Synchronous 4-bit Binary Counter with Synchronous Clear

• 74168: Synchronous 4-Bit Up/Down Decade Counter

• 74169: Synchronous 4-Bit Up/Down Binary Counter

• 74176: Presettable Decade (Bi-Quinary) Counter/Latch

• 74177: Presettable Binary Counter/Latch

• 74190: Synchronous Up/Down Decade Counter

• 74191: Synchronous Up/Down Binary Counter

• 74192: Synchronous Up/Down Decade Counter with Clear

• 74193: Synchronous Up/Down Binary Counter with Clear

• 74196: Presettable Decade Counter/Latch

• 74197: Presettable Binary Counter/Latch

• 74290: Decade Counter (separate divide-by-2 and divide-by-5 sections)

• 74291: 4-bit Universal Shift register, Binary Up/Down Counter, Synchronous

• 74293: 4-bit Binary Counter (separate divide-by-2 and divide-by-8 sections)

• 74390: Dual 4-bit Decade Counter

• 74393: Dual 4-bit Binary Counter

• 74452: Dual Decade Counter, Synchronous

• 74453: Dual Binary Counter, Synchronous

• 74454: Dual Decade Up/Down Counter, Synchronous, Preset Input

• 74455: Dual Binary Up/Down Counter, Synchronous, Preset Input

• 74461: 8-bit Presettable Binary Counter with three-state outputs

• 74490: Dual Decade Counter

• 74491: 10-bit Binary Up/Down Counter with Limited Preset and three-state logic outputs

• 74560: 4-bit Decade Counter with three-state outputs

• 74561: 4-bit Binary Counter with three-state outputs

• 74568: Decade Up/Down Counter with three-state outputs

• 74569: Binary Up/Down Counter with three-state outputs

• 74590: 8-Bit Binary Counter with Output Registers and three-state outputs

• 74592: 8-Bit Binary Counter with Input Registers

• 74593: 8-Bit Binary Counter with Input Registers and three-state outputs

• 74668: Synchronous 4-bit Decade Up/Down Counter

• 74669: Synchronous 4-bit Binary Up/Down Counter

• 74690: 4-bit Decimal Counter/Latch/Multiplexer with Asynchronous Reset, Three-State Outputs

• 74691: 4-bit Binary Counter/Latch/Multiplexer with Asynchronous Reset, Three-State Outputs

• 74692: 4-bit Decimal Counter/Latch/Multiplexer with Synchronous Reset, Three-State Outputs

• 74693: 4-bit Binary Counter/Latch/Multiplexer with Synchronous Reset, Three-State Outputs

• 74694: 4-bit Decimal Counter/Latch/Multiplexer with Synchronous and Asynchronous Resets, three-state outputs

• 74695: 4-bit Binary Counter/Latch/Multiplexer with Synchronous and Asynchronous Resets, three-state outputs

• 74696: 4-bit Decimal Counter/Register/Multiplexer with Asynchronous Reset, three-state outputs

• 74697: 4-bit Binary Counter/Register/Multiplexer with Asynchronous Reset, three-state outputs

• 74698: 4-bit Decimal Counter/Register/Multiplexer with Synchronous Reset, three-state outputs

• 74699: 4-bit Binary Counter/Register/Multiplexer with Synchronous Reset, three-state outputs

• 74716: Programmable Decade Counter

• 74718: Programmable Binary Counter

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Counters in VHDL

• VHDL code for a 74x163 like 4-bit binary counter

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library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;

entity V74x163 isport ( CLK, CLR_L, LD_L, ENP, ENT: in STD_LOGIC; D: in UNSIGNED (3 downto 0); Q: out UNSIGNED (3 downto 0); RCO: out STD_LOGIC );end V74x163;

architecture V74x163_arch of V74x163 issignal IQ: UNSIGNED (3 downto 0);beginprocess (CLK, ENT, IQ) begin if (CLK'event and CLK='1') then if CLR_L='0' then IQ <= (others => '0'); elsif LD_L='0' then IQ <= D; elsif (ENT and ENP)='1' then IQ <= IQ + 1; end if; end if; if (IQ=15) and (ENT='1') then RCO <= '1'; else RCO <= '0'; end if; Q <= IQ; end process;end V74x163_arch;

Counters in VHDL

• VHDL code for counting in the excess-3 sequence

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library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;

entity V74xs3 is port ( CLK, CLR_L, LD_L, ENP, ENT: in STD_LOGIC; D: in UNSIGNED (3 downto 0); Q: out UNSIGNED (3 downto 0); RCO: out STD_LOGIC );end V74xs3;

architecture V74xs3_arch of V74xs3 issignal IQ: UNSIGNED (3 downto 0);beginprocess (CLK, ENT, IQ) begin if CLK'event and CLK='1' then if CLR_L='0' then IQ <= (others => '0'); elsif LD_L='0' then IQ <= D; elsif (ENT and ENP)='1' and (IQ=12) then IQ <= ('0','0','1','1'); elsif (ENT and ENP)='1' then IQ <= IQ + 1; end if; end if; if (IQ=12) and (ENT='1') then RCO <= '1'; else RCO <= '0'; end if; Q <= IQ; end process;end V74xs3_arch;

Counters in VHDL

• Component of the previous code

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library IEEE;use IEEE.std_logic_1164.all;

entity Vdffqqn is port( CLK, D: in STD_LOGIC; Q, QN: out STD_LOGIC );end Vdffqqn;

architecture Vdffqqn_arch of Vdffqqn isbeginprocess(CLK) begin if (CLK'event and CLK='1') then Q <= D; QN <= not D; end if; end process;end Vdffqqn_arch;

Counters in VHDL

• VHDL program for 8-bit 74x163 like synchronous serial counter

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library IEEE;use IEEE.std_logic_1164.all;

entity V74x163s is port( CLK, CLR_L, LD_L, ENP, ENT: in STD_LOGIC; D: in STD_LOGIC_VECTOR (7 downto 0); Q: out STD_LOGIC_VECTOR (7 downto 0); RCO: out STD_LOGIC );end V74x163s;

architecture V74x163s_arch of V74x163s iscomponent syncsercell port( CLK, LDNOCLR, NOCLRORLD, CNTENP, D, CNTEN: in STD_LOGIC; CNTENO, Q: out STD_LOGIC );end component;signal LDNOCLR, NOCLRORLD: STD_LOGIC; -- common signalssignal SCNTEN: STD_LOGIC_VECTOR (8 downto 0); -- serial count-enable inputsbegin LDNOCLR <= (not LD_L) and CLR_L; -- create common load and clear controls NOCLRORLD <= LD_L and CLR_L; SCNTEN(0) <= ENT; -- serial count-enable into the first stage g1: for i in 0 to 7 generate -- generate the eight syncsercell stages U1: syncsercell port map ( CLK, LDNOCLR, NOCLRORLD, ENP, D(i), SCNTEN(i), SCNTEN(i+1), Q(i)); end generate; RCO <= SCNTEN(8); -- RCO is equivalent to final count-enable outputend V74x163s_arch;

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74x163 Internal Logic Diagram• XOR gates

embody the “T” function

• Mux-like structure for loading

One of the four bit “cells”One of the four bit “cells”

Counters in VHDL

• 1-bit cell of a synchronous serial, 74x163 like counter

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Counters in VHDL

• 1-bit cell of a synchronous serial, 74x163 like counter

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library IEEE;use IEEE.std_logic_1164.all;

entity syncsercell is port( CLK, LDNOCLR, NOCLRORLD, CNTENP, D, CNTEN: in STD_LOGIC; CNTENO, Q: out STD_LOGIC );end syncsercell;

architecture syncsercell_arch of syncsercell iscomponent Vdffqqn port( CLK, D: in STD_LOGIC; Q, QN: out STD_LOGIC );end component;signal LDAT, CDAT, DIN, Q_L: STD_LOGIC;begin LDAT <= LDNOCLR and D; CDAT <= NOCLRORLD and ((CNTENP and CNTEN) xor not Q_L); DIN <= LDAT or CDAT; CNTENO <= (not Q_L) and CNTEN; U1: Vdffqqn port map (CLK, DIN, Q, Q_L); end syncsercell_arch;

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Counter Operation• Free-running 16• Count if ENP and

ENT both asserted• Load if LD is asserted

(overrides counting)• Clear if CLR is asserted

(overrides loading and counting)

• All operations take place on rising CLK edge

• RCO is asserted if ENT is asserted andCount = 15

makes it free-runningmakes it free-running

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Free-Running 4-Bit ’163 Counter• “divide-by-16” counter• RCO is asserted if ENT is asserted and Count = 15

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Modified Counting Sequence

• Load 0101 (5) after Count = 15• 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5, 6, …• “divide-by-11” counter

DCBA

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Another Way

• Clear after Count = 1010 (10)• 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 0, 1, 2, 3, …• “modulo-11” or “divide-by-11” counter

saves gate saves gate inputsinputs

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Counting from 3 to 12

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Cascading Counters

• RCO (ripple carry out) is asserted in state 15, if ENT is asserted

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Decoding Binary-Counter States

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Decoder Waveforms

• Glitches may or may not be a concern

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Glitch-Free Outputs

• Registered outputs delayed by one clock cycle

Modulo-10 Counters

• From the 74LS163 “family” – the 74LS160– 74LS160 in free-running mode– Duty cycle of QC and QD is not 50%

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Modulo-10 Counters

• 74LS160 state diagram• The 74LS160 (and

74LS162) can be preset to any state, but will not count beyond 9.

• If preset to state 10, 11, 12, 13, 14, or 15, it will return to its normal sequence within two clock pulses.

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Ring Counter

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• A ring counter is a loop of flip-flops interconnected in such a manner that only one of the devices may be in a specified state at one time

• If the specified state is HIGH, then only one device may be HIGH at one time.

• As the clock, or input, signal is received, the specified state will shift to the next device at a rate of 1 shift per clock, or input, pulse.

Ring Counter• A typical four-stage ring

counter

• Composed of R-S FFs. – J-K FFs may be used as well

• Output of each AND gate is input to the R, or reset side, of the nearest FF and to the S, or set side, of the next FF

• Q output of each FF is applied to the B input of the AND gate that is connected to its own R input

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Another MSI Device• 74LS194 is a 4-Bit

Bidirectional Universal Shift Register

• may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers

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Another MSI Device

• The ‘194 has the circuitry needed to count

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Shift-Register Counters

• Ring counter

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Johnson Counter

• “Twisted ring” counter

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LFSR Counters• Pseudo-random number generator• 2n - 1 states before repeating• Same circuits used in CRC error checking in

Ethernet networks, etc.

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LFSR Counters

• Feedback equations for all values of n

Decade Counters• A decade counter is a binary counter that is designed to

count to 1010, or 10102

• An ordinary four-stage counter can be easily modified to a decade counter by adding a NAND gate as shown below

• Notice that FF2 and FF4 provide the inputs to the NAND gate

• The NAND gate output is connected to the CLR input of each of the FFs

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Counter Applications

• Digital Clock

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Up/Down Counters

• A 3-bit binary up/down counter

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Clock Count

UP / DOWN

Counter

QA

QB

QC

Up/Down Counters• This circuit is a 3-bit

UP/DOWN synchronous counter using JK flip-flops configured to operate as toggle or T-type flip-flops giving a count of zero (000) to seven (111) and back to zero again.

• An additional input determines the direction of the count, either UP or DOWN and the timing diagram gives an example of the counters operation as this UP/DOWN input changes state.

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Up/Down Counters

• The 74LS169 is a fully synchronous 4-stage up/down counter

• Includes:– a preset capability for

programmable operation

– carry lookahead for easy cascading

– a U/ D input to control the direction of counting

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Up/Down Counters

• The SN74LS169 operates in a Modulo-16 binary sequence

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Up/Down Counters

• 74LS169 logic circuit diagram

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Counter Applications

• 3-Bit Gray Code Counter

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Counter Applications

• 3-Bit Gray Code Counter in VHDL

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library ieee;use ieee.std_logic_1164.all;

entity StateCounter is port(clock: in std_logic; Q: buffer std_logic_vector(0 to 2) );end entity StateCounter;

architecture CounterBehavior of StateCounter isbeginprocess (Clock)begin if Clock = ‘1’ and Clock’event then case Q is when “000” => Q <= “010”; when “010” => Q <= “110”; when “110” => Q <= “100”; when “100” => Q <= “101”; when “101” => Q <= “001”; when “001” => Q <= “000”; when others => Q <= “000”; end case; end if;end process;end architecture CounterBehavior;

Next Time

• Midterm returned

• Start MIPs design

• Counter design using FSM approach

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