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EE141
Interconnect EffectsInput-Output
EE141- Spring 2003Lecture 25
EE141
Dealing with Capacitive Cross Talk
Avoid floating nodes Protect sensitive nodes Make rise and fall times as large as possible Differential signaling Do not run wires together for a long distance Use shielding wires Use shielding layers
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Delay Degradation
Cc
- Impact of neighboring signalactivity on switching delay
- When neighboring lines switchin opposite direction of victimline, delay increases
Miller EffectMiller Effect
- Both terminals of capacitor are switched in opposite directions(0 → Vdd, Vdd → 0)
- Effective voltage is doubled and additional charge is needed(from Q=CV)
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Impact of Cross Talk on Delay
r is ratio between capacitance to GND and to neighbor
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Interconnect ProjectionsLow-k dielectrics
Both delay and power are reduced by dropping interconnectcapacitance
Types of low-k materials include: inorganic (SiO2), organic(Polyimides) and aerogels (ultra low-k)
The numbers below are on theconservative side of the NRTS roadmap
Generation 0.25µm
0.18µm
0.13µm
0.1µm
0.07µm
0.05µm
DielectricConstant
3.3 2.7 2.3 2.0 1.8 1.5
εεεε
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How to Battle CapacitiveCrosstalk
Substrate (GND)
GND
ShieldinglayerVDD
GND
Shieldingwire
Avoid large crosstalk cap’s Avoid floating nodes Isolate sensitive nodes Control rise/fall times Shield! Differential signaling
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Driving Large Capacitances
Vin Vout
CL
VDD
• Transistor Sizing• Cascaded Buffers
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Using Cascaded Buffers
CL = 20 pF
In Out
1 2 N
0.25 µµµµm processCin = 2.5 fFtp0 = 30 ps
F = CL/Cin = 8000fopt = 3.6 N = 7tp = 0.76 ns
(See Chapter 5)
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Output Driver Design
Trade off Performance for Area and EnergyGiven tpmax find N and f Area
Energy
( ) minminmin12
1
1
1
1...1 A
f
FA
f
fAfffA
NN
driver −−=
−−=++++= −
( ) 22212
11
1...1 DD
LDDiDDi
Ndriver V
f
CVC
f
FVCfffE
−≈
−−=++++= −
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Delay as a Function of F and N
101 3 5 7
Number of buffer stages N
9 11
10,000
1000
100
t
p
/
t
p
0
F = 100F = 1000
F = 10,000
t p/t
p0
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Output Driver Design
Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns
Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns
0.25 µµµµm process, CL = 20 pF
EE141
How to Design Large Transistors
G(ate)
S(ource)
D(rain)
Multiple
Contacts
small transistors in parallel
Reduces diffusion capacitance
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Bonding Pad Design
Bonding Pad
Out
InVDD GND
100µm
GND
Out
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ESD Protection
When a chip is connected to a board, there isunknown (potentially large) static voltagedifference
Equalizing potentials requires (large) chargeflow through the pads
Diodes sink this charge into the substrate –need guard rings to pick it up.
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ESD Protection
Diode
PAD
VDD
R D1
D2
X
C
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Chip Packaging
ChipL
L´
Bonding wire
Mountingcavity
Leadframe
Pin
•Bond wires (~25µm) are usedto connect the package to the chip
• Pads are arranged in a framearound the chip
• Pads are relatively large(~100µm in 0.25µm technology),with large pitch (100µm)
•Many chips areas are ‘pad limited’
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Pad Frame
Layout Die Photo
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Chip Packaging
An alternative is ‘flip-chip’:» Pads are distributed around the chip» The soldering balls are placed on pads» The chip is ‘flipped’ onto the package» Can have many more pads
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INTERCONNECT
Dealing with Resistance
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Impact of Resistance
Impact of resistance is commonly seen inpower supply distribution:» IR drop» Voltage variations
Power supply is distributed to minimize the IRdrop and the change in current due toswitching of gates
How to drive long RC wires» Major impact on performance in today’s ICs
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RI Introduced Noise
VDD
X
I
I
R’
R
VDD - ∆V’
∆V
∆V
φpre
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Power and Ground Distribution
GND
VDD
Logic
GND
VDD
Logic
GND
VDD
(a) Finger-shaped network (b) Network with multiple supply pins
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Resistance and the PowerDistribution Problem
Source: Simplex
•• Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction•• Heavily influenced by packaging technologyHeavily influenced by packaging technology
BeforeBefore AfterAfter
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Power Distribution
Low-level distribution is in Metal 1
Power has to be ‘strapped’ in higher layers ofmetal.
The spacing is set by IR drop,electromigration, inductive effects
Always use multiple contacts on straps
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Electromigration (1)
Limits dc-current to 1 mA/µm
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Electromigration (2)
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The Impact of Resistivity
CN-1 CNC2
R1 R2
C1
Tr
Vin
RN-1 RN
0 0.5 1 1 .5 2 2 .5 3 3 .5 4 4 .5 50
0 .5
1
1 .5
2
2 .5
time (nsec)
volta
ge
(V
)x= L/10
x = L/4
x = L/2
x= L
0 0.5 1 1 .5 2 2 .5 3 3 .5 4 4 .5 50
0 .5
1
1 .5
2
2 .5
time (nsec)
volta
ge
(V
)x= L/10
x = L/4
x = L/2
x= L
Diffused signalDiffused signalpropagationpropagation
Delay ~ LDelay ~ L22
The distributedThe distributed rcrc--lineline
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The Global Wire Problem
(((( ))))outwwdoutdwwd CRCRCR693.0CR377.0T ++++++++++++====
Challenges No further improvements to be expected after the
introduction of Copper (superconducting, optical?) Design solutions
» Use of fat wires» Insert repeaters — but might become prohibitive (power, area)» Efficient chip floorplanning
Towards “communication-based” design» How to deal with latency?» Is synchronicity an absolute necessity?
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Interconnect:# of Wiring Layers
# of metal layers is steadily increasing due to:
• Increasing die size and device count: we need more wires and longer wires to connect everything
• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC
substrate
poly
M1
M2
M3
M4
M5
M6
Tins
H
WS
ρρρρ = 2.2µΩµΩµΩµΩ-cm
0.25 µm wiring stack
Minimum Widths (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.0µ1.0µ1.0µ1.0µ 0.8µ0.8µ0.8µ0.8µ 0.6µ0.6µ0.6µ0.6µ 0.35µ0.35µ0.35µ0.35µ 0.25µ0.25µ0.25µ0.25µ
M5
M4
M3
M2
M1
Poly
Minimum Spacing (Relative)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1.0µ1.0µ1.0µ1.0µ 0.8µ0.8µ0.8µ0.8µ 0.6µ0.6µ0.6µ0.6µ 0.35µ0.35µ0.35µ0.35µ 0.25µ0.25µ0.25µ0.25µ
M5
M4
M3
M2
M1
Poly
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Interconnect Projections:Copper
Copper is planned in full sub-0.25µm process flows and large-scaledesigns (IBM, Motorola, IEDM97)
With cladding and other effects, Cu~ 2.2 µΩ-cm vs. 3.5 for Al(Cu)⇒40% reduction in resistance
Electromigration improvement;100X longer lifetime (IBM,IEDM97)
» Electromigration is a limiting factorbeyond 0.18 µm if Al is used (HP,IEDM95)
Vias
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Diagonal Wiring
y
x
destination
Manhattan
source
diagonal
• 20+% Interconnect length reduction• Clock speed
Signal integrityPower integrity
• 15+% Smaller chipsplus 30+% via reduction
Courtesy Cadence X-initiative
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Using BypassesDriver
Polysilicon word line
Polysilicon word line
Metal word line
Metal bypass
Driving a word line from both sides
Using a metal bypass
WL
WL K cells
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Reducing RC-delay
Repeater
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Repeater Insertion (Revisited)
Taking the repeater loading into account
For a given technology and a given interconnect layer, there exiFor a given technology and a given interconnect layer, there existsstsan optimal length of the wire segments between repeaters. Thean optimal length of the wire segments between repeaters. Thedelay of these wire segments isdelay of these wire segments is independent of the routing layer!independent of the routing layer!
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INTERCONNECT
Dealing with Inductance
EE141
L di/dt
CL
V’DD
VDD
L i(t)
VoutVin
GND’
L
Impact of inductanceon supply voltages:• Change in current inducesthe change in voltage• Longer supply lines havelarger L
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L di/dt: Simulation
t
t
t
vout
iL
vL
20mA
40mA
5V
0.2V
0.0
1.0
2.0
3.0
4.0
5.0
Vou
t(V)
0
10
20
I L(m
A)
2 4 6 8 10t (nsec)
-0.3
-0.1
0.1
0.3
0.5
VL(V
)
tfall = 0.5 nsec
tfall = 4 nsec
Signals Waveforms for Output Driver connected To Bonding Pads(a) vout; (b) iL and (c) vL.
The Results of an Actual Simulation are Shown on the Right Side.
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Choosing the Right Pin
ChipL
L´
Bonding wire
Mountingcavity
Leadframe
Pin
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Decoupling Capacitors
SUPPLY
Boardwiring
Bondingwire
Decouplingcapacitor
CHIPCd
Decoupling capacitors are added:• on the board (right under the supply pins)• on the chip (under the supply straps, near large buffers)
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De-coupling Capacitor Ratios
EV4» total effective switching capacitance = 12.5nF» 128nF of de-coupling capacitance» de-coupling/switching capacitance ~ 10x
EV5» 13.9nF of switching capacitance» 160nF of de-coupling capacitance
EV6» 34nF of effective switching capacitance» 320nF of de-coupling capacitance -- not enough!
Source: B. Herrick (Compaq)
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EV6 De-coupling CapacitanceDesign for ∆Idd= 25 A @ Vdd = 2.2 V, f = 600
MHz» 0.32-µF of on-chip de-coupling capacitance was
added– Under major busses and around major gridded clock drivers– Occupies 15-20% of die area
» 1-µF 2-cm2 Wirebond Attached Chip Capacitor(WACC) significantly increases “Near-Chip” de-coupling
– 160 Vdd/Vss bondwire pairs on the WACC minimizeinductance
Source: B. Herrick (Compaq)
EE141
EV6 WACC
587 IPGA
MicroprocessorWACC
Heat Slug
389 Signal - 198 VDD/VSS Pins389 Signal Bondwires
395 VDD/VSS Bondwires
320 VDD/VSS Bondwires
Source: B. Herrick (Compaq)
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Design Techniques to address L di/dt
Separate power pins for I/O pads and chip core Multiple power and ground pins Position of power and ground pins on package Increase tr and tf Advanced packaging technologies Decoupling capacitances on chip and on board
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