Dynamic Power Estimation With Process Variation Modeled as Min–Max Delay

Jins Davis AlexanderVishwani D. Agrawal

Department of Electrical and Computer EngineeringAuburn University, AL 36849 USA

Motivation Dynamic power increases with glitch

transitions, which in turn are a functions of gate delays.

Process variation can influence delays in a circuit, especially in nanoscale technologies.

Thus we need to access this variability for effective estimation of power.

Motivation… Many existing techniques depend on Monte

Carlo approaches which are time consuming and CPU intensive.

Bounded delay models are usually considered to address process variations in logic level simulation and timing analysis.

We propose a dynamic power analysis method that uses min–max delay model for variations, eliminating the need for Monte Carlo simulation.

Outline

Ambiguity Intervals. Maximum Transition Estimation. Minimum Transition Estimation. Simulation Methodology. Experimental Results and

Observations. Conclusion.

Circuit c880 Simulation

Monte Carlo Estimation (500 samples)

Power (mW)

Monte Carlo Simulation Min-Max Simulation

Min Pwr (mW)

Max Pwr (mW)

Exec. Time (secs)

Min Pwr (mW)

Max Pwr (mW)

Exec. Time (secs)

2.78 3.38 339.8 2.75 3.59 0.23

Ambiguity Interval of Signals.

EA is the earliest arrival time LS is the latest stabilization time IV is the initial signal value FV is the final signal value

EAdv LSdv

EAsv=-∞ LSsv=∞

EAsv LSsv

EAdv=-∞ LSdv=∞

Propagating Ambiguity Intervals through Gates.

(mindel, maxdel)

The ambiguity interval (EA,LS) for a gate output is determined from the ambiguity intervals of input signals, their pre-transition and post-transition steady-state values, and the min-max gate delays.

Theorem 1.

For a gate output: EA = max {E1, E2} + mindel LS = min {L1, L2} + maxdel Where following are for all inputs i

E1 = max{EAdv(i)} E2 = min{EAsv(i)} L1 = min{LSsv(i)} L2 = max{LSdv(i)}

Finding Number of Transitions.

5 8 10 12

(mindel, maxdel)

7 10 12 14

[0,2] 6 17

[mintran,maxtran]

Estimating Maximum Transitions First upper bound: We calculate the maximum transitions (Nd)

that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV,FV) output values.

Second upper bound: We take the sum of the input transitions (N) as the output cannot exceed this. We modify this by :

N = N – k .....(1) where k = 0, 1, or 2 for a 2-input gate and is determined by the

ambiguity regions and (IV, FV) values of inputs.

Theorem 2: The maximum number of transitions is minimum of the two upper bounds:

maxtran = min (Nd, N) .....(2)

Example 1: Upper Bounds.

Nd = ∞

maxtran=min (Nd, N) = 8

Nd = 6

maxtran=min (Nd, N) = 6

EAsv =

LSdv =

EAsv = LSdv =

EAdv LSsv

[n1 = 6]

[n2 = 4]

[n1 + n2 – k = 8 ] ,

where k = 2

[ 6 + 4 – 2 = 8 ]

Example 2: k in Second Upper Bound.

Estimating Minimum Transitions First lower bound (Ns): Based on steady state values, i.e.,

00, 11 as no transitions and 01, 10 as a single transition.

Second lower bound (Ndet): The minimum number of transitions that can occur in the output ambiguity region is the number of deterministic signal changes that occur within the ambiguity region and such that signal changes are spaced at time intervals greater than or equal to the inertial delay of the gate.

Theorem 3: The minimum number of transitions is the maximum of the two lower bounds:

mintran= max (Ns, Ndet) ...(3)

Example 3: Lower Bound.

There will always be a hazard in the output as long as

(EAsv – LSdv) ≥ dThus in this case the mintran is not 0 as per the steady state condition, but is 2.

EAsv =

LSsv =

EAdv = LSdv =

EAsv LSsv

Simulation Methodology maxdel, mindel = nominal delay ± Δ% Three linear-time passes for each input vector: First pass: zero delay simulation to determine initial

and final values, IV and FV, for all signals. Second pass: determines earliest arrival (EA) and

latest stabilization (LS) according to Theorem 1. Third pass: determines upper and lower bound,

maxtran and mintran, for all gates according to Theorems 2 and 3.

Experimental Results: Maximum Power.

Monte Carlo Simulation v/s Min-Max analysis for circuit C880. 100 sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors). Each point is maximum power for one vector-pair over 100 sample circuits.

R2 is coefficient of determination, equals 1.0 for ideal fit.

Ideal, for infinite samples

Regression line

Results: Minimum Power.

R2 is coefficient of determination, equals 1.0 for ideal fit.

Monte Carlo Simulation v/s Min-Max analysis for circuit C880. 100 sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors). Each point is minimum power for one vector-pair over 100 sample circuits.

Ideal, for infinite samples

Regression line

Observing Effect of Inertial Delay.

min-max delay (1ps,3ps)

0 2 4 6 8 10

Number of Transitions

0 2 4 6 8

Number of TransitionsF

Transition Statistics for high activity gate 1407 in c2670 for a random vector pair. Histograms obtained from Monte Carlo Simulations of 100 sample circuits.

Further Increasing Inertial Delay.

0 2 4 6

Table of Results…Circuits implemented using TSMC025 2.5V CMOS library , with standard size gate delay of 10 ps . Min-Max values obtained by assuming ± 20 % variation.

Execution Time Comparison.

357 514 880 1161 1667 2290 2416 3466

Number of gates

Event driven simulation

Min-Max Simulation

Conclusion. We have used min–max delay model to

successfully develop a power estimation method with consideration of process variations.

Linear time complexity in number of gates and an efficient alternative to the Monte Carlo analysis.

Future work includes considering process dependent variation in leakage as well as in node capacitances.

Thank You.

Dynamic Power Estimation With Process Variation Modeled as Min–Max Delay

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