Digital block implementation methodology for a 130nm · PDF fileDigital block implementation...

Digital block implementation methodology for a 130nm process

Microelecronics User Group meeting TWEPP 2009 – Paris

Sandro Bonacini CERN PH/ESE

sandro.bonacini@cern.ch

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

Motivation

  Implementation of digital blocks   for small (~200 kgate) logic cores   for digital or mixed signal ASICs

  Using the IBM 130 nm standard cell library   Separate substrate/ground and n-well/VDD biasing for mixed

signal designs

  Defined methodology compatible with mixed signal design flows   Open Access based

Design flow components   Tools

  Virtuoso 6.1.3 (OA based)   SOC Encounter 7.1   Conformal 7.2   EXT 7.1.2 (QRC)   Assura 3.2   Calibre 2008.3

  Design Kits   IBM CMOS8RF DM design kit V1.6

  3 thin, 2 thick, 3 RF metals.   IBM CMOS8RF LM design kit V1.6

  6 thin, 2 thick metals.

Digital design flow RTL synthesis

Floorplanning & power routing

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

Signoff RC extraction

Timing analysis

Logical Equivalence

Checking Clock tree synthesis

Routing

Timing optimization

Tape-out

Automated task User task

RTL compiler script [.tcl]

Abstract layout Definition [.lef]

Capacitance tables [.CapTbl]

Max timing Liberty libraries

[.lib]

Synthesis

RTL synthesis

RTL description [.v] / [.vhd]

Timing constraints

[.sdc]

Mapped netlist [.v]

Conformal script [.lec]

Synthesis, mapping and timing reports

  Timing constraints:   Clock definitions   Input delays,

fanout, transition, etc.

  Output load, etc.

RTL Compiler [rc]

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

Timing analysis

Logical Equivalence

Routing

Timing optimization

Tape-out

Logical Equivalence

Checking

Logic Equivalence Checking

  Tool: Conformal

Logical Equivalence

Checking

Max timing Liberty libraries

[.lib]

Mapped netlist [.v]

Conformal script [.lec]

LEC report

Synthesized netlist

User RTL code

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

Timing analysis

Logical Equivalence

Routing

Timing optimization

Tape-out

  Tool: Encounter

Design import and floorplanning

Mapped netlist [.v]

Open Access Standard cells

library [.oa]

QX tech file [.tch]

Capacitance tables [.CapTbl]

Min/Max timing Liberty libraries

[.lib]

Open Access Floorplanned

Design [.oa]

Reports Floorplanning

& power routing

Design import

  Define   Chip/core size   target area utilization   I/O placement   module placement in

case of TMR or other special constraints

  Power planning/routing   Core/block rings and

stripes

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

Timing analysis

Logical Equivalence

Routing

Timing optimization

Tape-out

Placement

  Encounter command file

Placement

Scan-chain reorder

Open Access Floorplanned Design [.oa]

Connect cells power/ground

Add tap cells

Open Access Placed

Design [.oa]

Reports

Power/ground connections

Placement

Tap cells Standard cells

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

Timing analysis

Logical Equivalence

Routing

Timing optimization

Tape-out

Congestion analysis

  Use Encounter Trialroute to estimate congested areas

  Manually add placement partial blockage

  Change position of I/Os or blocks

  …or increase number of routing metals

Open Access Placed

Design [.oa]

Congestion analysis

Placement optimization

Open Access Placed

Design [.oa]

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

Timing analysis

Logical Equivalence

Routing

Timing optimization

Tape-out

Timing optimization

Clock tree synthesis

Routing

Timing optimization

Automatic P&R steps

Timing optimization

Open Access Placed

Design [.oa]

Clock tree synthesis

Routing

Open Access Routed

Design [.oa]

Timing optimization

Reports

Clock tree synthesis & signal routing

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

Timing analysis

Logical Equivalence

Routing

Timing optimization

Tape-out

Timing analysis

Design for manufacturing

Cells & metal fill

Open Access Routed

Design [.oa]

Antenna fix

Via optimization

Timing analysis

Open Access Final

Design [.oa]

Signoff timing report

Delay file [.sdf]

Final netlist [.v]

Signal integrity analysis

Antenna fix

  Re-routes long nets

  Inserts tie-down diodes

Via optimization

Cells & metal fill

Timing closure

  If signoff timing analysis reports violations   increase buffer sizes   add extra buffers   reroute signals   check constraints   exploit useful skew   annotate native post-route RC

extraction tool   re-run optimization

Placement

Congestion analysis

Logical Equivalence

Checking

Timing optimization

Timing analysis

Logical Equivalence

Routing

Timing optimization

Tape-out

Logical Equivalence

Checking

Virtuoso

  OA design is present in Virtuoso   Easily

included in a mixed-signal chip

Thank you…

  Design flow   …is soon to be available

  Implementation of digital blocks   Using the IBM 130 nm standard cell library   Defined methodology compatible with mixed signal design

  Open Access based

Digital block implementation methodology for a 130nm · PDF fileDigital block implementation...

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