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TM
September 2013
2 TM
• Consumers in the mass market are driving demand for seamless integration of their smart-devices to bring personal content into the vehicle
• OEM software costs continue to rise due to increased resource and development needed to support higher level of integration as well as future software upgrade needs
• Rearview camera systems in all passenger vehicles driving the need for cost-effective solution to meet upcoming governmental safety mandates
• The need to isolate the vehicle from consumer device threats adds an additional layer of complexity to the design of driver information systems
3 TM
Gap and
architecture
break
Gen 4 Portfolio ARM v7
Gen 3 Portfolio Power Architecture®
and ARM®
i.MX6xx
Dual/Quad
Vybrid
R Series
Next Gen Cluster / Gauge
Next Gen Cluster / Gauge
i.MX5xx
Qorivva
MPC5645 Cluster / Gauge
Qorivva
MPC5606 Cluster / Gauge
i.MX 6Solo
Brid
ge, S
cale
an
d U
nify
8-,16- and 32-
bit MCUs 32-bit MCU/MPUs and
GPUs based on ARM
4 TM
• Cost-optimized solution integrates:
─MCU + MPU
─Video ADC
─On-chip SRAM
─Single 3.3V supply
• Improved reliability, fewer components, and reduced system complexity
• Simple, cost-effective package
Vybrid Automotive Solutions Today’s Connected Radio
Collection of discrete ICs
• Many external components: MCU, MPU, ADC, DRAM, PMIC
• Additional assembly steps and compromised reliability
• Higher total system cost
5 TM
Production
VF3xxR - Cortex A5+M4, 266MHz, 176LQFP
OpenVG, TFT , MLB, USB, VideoADC
VF5xxR - Cortex A5+M4, 400MHz, 364BGA
OpenVG, TFT, MLB, USBx2, VideoADC, DDR3
Fea
ture
In
teg
rati
on
Performance
AUTOMOTIVE
6 TM
• Unique dual-core architecture with apps processor to run high-level OS (i.e. Linux) and control processor to run RTOS (i.e. MQX)
• Ability to segment tasks that need predictable latencies to execute on the M4 and execute graphical and connectivity tasks on A5
• Secure boot and cryptographic algorithm acceleration for sensitive applications
• Multimedia hardware IP that offloads pixels processing from the cores
• Real time sub-system including PWM and ADC for motor control
Cortex-A5 Up to 400MHz
NEON/FPU
32KB/32KB L1
Multimedia Connectivity
Power Management
- single 3.3V supply
- low voltage reset
USB OTG + Phy
USB OTG + Phy
eMMC/SD x2
System Connectivity CAN x2
I2C x4
UART/LIN x6
SPI x3
Media Local Bus 3-wire
10/100 Ethernet
System and General Purpose
DMA
HAB 4.1 Security Tamper Detect
Watchdog Timer Other Timers (x8)
Display I/O 2D-ACE x2
Animation &Comp Engine
Segment Display Controller (4x40)
Camera Input, 18-bit + Composite (4 to 1))
Audio I/O
SAI x4 (i2s x4)
SP/DIF Receiver/Transmitter
Sample Rate Convertor
OpenVG GPU (GC355)
External Memory
DRAM (16-bit) LP , DDR3
Dual Quad-SPI Flash (SDR and DDR)
1.5MB SRAM
Real Time Clock
Pulse Width Modulator
GPIO
2x 12-bit SAR ADC
2x 12-bit DAC With Tone Generation
Internal Temperature Monitor
NEON optimized CODECS/Libraries
HMI Tools Comm Stacks
Royalty-free RTOS
NAND/NOR Flash 8/16b
Cortex-M4 Up to 166MHz
16KB/16KB L1
ESAI x1 (i2s x6)
7 TM
Feature 3xxR Family 5xxR Family
CPU 266MHz Cortex-A5
133MHz Cortex-M4
400MHz Cortex-A5
133MHz Cortex-M4
On-chip memory 1.5MB (512K ECC)
1.5MB (512K ECC)
OR
1MB & 512K L2 cache
Serial Flash interface Dual QuadSPI Dual QuadSPI
NAND Yes (8-bit)
Up to 32-bit HW ECC
Yes (16-bit)
Up to 32-bit HW ECC
FlexBus interface
(parallel NOR) Yes (addr / data mux’d)
Yes, (addr / data mux’d plus 8-bit
dedicated data)
DRAM interface No 16-bit LPDDR2/DDR3
Display interface TFT & 40x4 Segmented LCD OR
2x TFT up to WQVGA
TFT & 40x4 Segmented LCD OR
2x TFT up to WVGA
Video ADC / Camera Input 2x Composite
24-bit parallel
4x Composite
24-bit parallel
10/100 Ethernet w/ IEEE1588 1 2
10-channel 12-bit ADC Yes Yes
USB 1x USB OTG HS 2x USB OTG HS
Audio interface SAI x3 (i2s x3)
ESAI x1 (2 Tx, 4 Tx or Rx)
SAI x4 (i2s x4)
ESAI x1 (2 Tx, 4 Tx or Rx)
UART, DSPI, I2C 4, 3, 4 6, 4, 4
SD/MMC interface 1 2
CAN 2x FlexCAN 2x FlexCAN
MOST 1x MLB50 1x MLB50
GPIO Up to 115 Up to 136
Package 176LQFP 364BGA
AUTOMOTIVE
8 TM
S V 3 1 1 R 3 C MK
Brand: V = Vybrid
Series: F = current
2
Qualification Status
P = engineering samples
S = automotive qualified
Family
3 = Standard
5 = Advanced
F
Core
1 = Cortex A5
2 = Cortex A5 + M4
3 = M4 Primary
Version
R = Auto
Memory Option
3 = Standard (1.5MB SRAM)
2 = Optional (1MB SRAM and 512K L2 Cache)
Temp Spec
C = -40 to +85C Ta
Speed (A5 core)
2 = 266MHz
4 = 400MHz
Package
KU = 176LQFP
MK = 364BGA
Graphics
1 = No Open VG
2 = Open VG
Not all combinations are available. Please refer to part number list
K1
Revision
K1 = Rev 1.1
AUTOMOTIVE
9 TM
Part Number Sample Part Number
(Superset) Package Description
SVF311R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, 176LQFP-EP
SVF312R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, OpenVG GPU, 176LQFP-EP
SVF321R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, M4, 176LQFP-EP
SVF322R3K1CKU2 PVF322R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, M4, OpenVG GPU, 176LQFP-EP
SVF332R3K1CKU2 PVF332R3K1CKU2 LQFP-EP 176 24*24*1.6 A5-266, M4 Primary, OpenVG GPU, 176LQFP-
EP
SVF511R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, 364BGA
SVF512R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, OpenVG GPU, 364BGA
SVF521R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, M4, 364BGA
SVF522R3K1CMK4 PVF522R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, M4, OpenVG GPU, 364BGA
SVF532R3K1CMK4 PVF532R3K1CMK4 MAP 364 17*17*1.5 P0.8 A5-400, M4 Primary, OpenVG GPU, 364BGA
SVF522R2K1CMK4 N/A MAP 364 17*17*1.5 P0.8 A5-400, M4, L2 Cache, OpenVG GPU, 364BGA
Part numbers highlighted bold are supersets
AUTOMOTIVE
10 TM
OpenVG GPU 2D-ACE (DCU) VideoADC VIU3 QuadSPI
• 2D Graphics Accelerator
• Accelerates cluster needles at 60fps
• Rendering of true-type fonts with 16x AA
• Warping for Head Up Display applications
• Graphics acceleration for dual display systems
• Display controller with 2D acceleration features
• 6 layer blend & 64 layer support
• Enables low memory footprint GFx
• Inline Run Length Encode
• Composite Video (CVBS) Decoder & AFE
• PAL / NTSC
• Y/C Separation
• 2D Comb Filtering
• Interfaces to VIU3 for
• Digital Video Interface
• Supports ITU-656, RGB, YUV input formats
• Image Up/Downscaling
• Video De-interlacing
• Brightness and contrast adjustment
• Serial Flash Controller.
• 66MHz Dual DDR serial flash interface: 133MByte/sec
• Flexible buffering
• Support for multiple flash vendors
• Graphics storage and eXecute-in-Place (XIP)
11 TM
1. Cost-optimized for Connected Radios
− QFP-versions for lower board costs/complexity
− On-chip SRAM and RTOS option for running without DRAM
− Market specific integration
2. Added value through software and enablement
− “Foundation” software suite (production-grade/terms) provided
− Pre-integrated/tested software “accessories” available from Freescale
3. 2D Animation & Composition Engine (2D-ACE)
− Dramatically reduces VRAM requirements for large color displays
− Delivers 60fps animation w/ very low CPU load
− 2D GPU for line-drawing, transformations, raster ops
4. Cortex A5 CPU & peripheral reuse enables scalability to i.MX6 family
Ideal as connected, display-
based radio and graphics
processor for cluster and
Multi-Function Display
Delivers eye-catching graphics
with very efficient use of
system resources
12 TM
• MCU handles CAN +
system wake-up
• MPU/DSP for Media
Connectivity/Display/
UI
• Radio DSP for radio
baseband & Audio
I/O
• Add-on modules for
DAB / HD Radio
• External ADC for
analog back-up
camera •Board Space
•PCB Complexity
•Cost of components
13 TM
• Vybrid handles all
connectivity, media
playback, vehicle
communications and
power-up/down with A5 +
M4 architecture
• No ext DRAM for many
use-cases
• No need for complex PMIC
• No external Video ADC
• Radio DSP for radio
baseband & Audio I/O
• Add-on modules for DAB /
HD Radio
•Reduce PCB size and Complexity
•Fewer components
•Production Grade Connectivity SW
TM
15 TM
• Impresario is a Connected Radio
software platform targeted for the
Vybrid. The platform is made up of
functional blocks to deliver
automotive connected radio
functionality
• Scalable feature set from Entry
Level to Advanced solutions.
Drivers
OS (MQX/Linux)
Impresario
Middleware
Impresario API
Vybrid Silicon
Customer Application
16 TM
The Connected Radio software platform is being developed for the Faraday silicon. The platform is made up of functional blocks to deliver automotive connected radio functionality.
• Multimedia Framework with Radio Tuner and CD Support
− Support for industry standard audio CODECs
• CE Device Connectivity (iAP, USB, SD)
• HMI Framework
• Bluetooth Stack and Profiles with AEC/NS (HFP, A2DP, AVRCP)
• Automotive Communication Stacks (CAN, LIN, MOST)
• Advanced Connected Radio Functionality
− Text to Speech
− Speech Recognition
− MirrorLink / iPod Out
17 TM
Which Operating Systems will be supported?
− The Connected Radio platform leverages the Freescale Operating
System Abstraction layer to provide a Connected Radio Platform on
MQX and Linux*
− Through extensions to the OSA, Connected Radio can be modified
to work with any modern operating system that supports common
OS primitives (memory management, signals, mutexes, etc)
18 TM
• Underpinned by Freescale MQX and Linux
platform support and Commercial terms
− Standard Warranty and Indemnification
− Available Support and Maintenance
• CE Device Connectivity (iPhone, USB, SD)
• HMI Framework optimized for on-chip
graphics resources (2D-ACE, OpenVG
GPU)
• Multimedia Framework with Radio Tuner
and CD Player
• Bluetooth Stack and Profiles
• Automotive Communication Stacks
• Advanced Connected Radio Functionality
− Text to Speech, Speech Recognition
− iPod Out, Terminal Mode
19 TM
Which hardware will the Connected Radio platform support?
− Production level code with full peripheral support will be available
only on the Faraday reference hardware
Which Compilers will the Connected Radio platform support?
− Connected Radio will provide support for the following compilers
GNU
− Support for porting of Connected Radio to a new compiler can be
provided by the Freescale Professional Services Team
20 TM
• Pre-integrated key technologies from
industry-leading partners help you get to
market faster
• Proven, tested, production-ready code
ready for evaluation and integration
• Specifically optimized for Vybrid
performance and memory footprint
• Partners for HMI tools, Bluetooth, and
AEC/NS
21 TM
• Bluetooth protocol
stack
• Industry leader in
Bluetooth and active
SIG leadership
• Certified Bluetooth
compliance with 12
years of maturity
Bluetooth software
framework
• Multi-profile Bluetooth
SW application
framework
• “We love making
Bluetooth easy”
Sybase iAnywhere Cybercom blueGO
Voice Communication
Package
• Signal processing
enabling high quality
voice communications
• AEC / NS
− Acoustic Echo Canceller
− Noise Suppressor
Alango Technologies
TM 22
23 TM
• The 2D-ACE is an advanced graphics control module that directly drives an external TFT LCD
− Allows full flexibility of TFT display sizes
− Fetches bit-mapped “sprites” from on-chip or off-chip memory and places them on graphic layers
− Blends the layers using
− Has support for a cursor separate from the “sprite” graphics
− Supports multiple graphic formats in RGB and YUV format and with and without alpha and run length encoding
16bpp RGB565, RGB1555, RGB4444, 24bpp RGB888 and 32bpp ARGB8888
Indexed colors with variable bit depths from 1 bit per pixel (bpp) to 8bpp and APAL8
YUV format - YCbCr422
− Adjusts the gamma of the graphics to match the TFT in use and dither pixel colors on panels with less than 24-bit color
− Displays a test signal to allow calibration of panel and system test
24 TM
• Pipelined operation up to 90MHz pixel clock
• Memory size optimized
• Per obj. ani. frame rate
Any memory Any memory
RAM RAM
Any memory
Static
objects RAM
Dynamic
objects
eDMA
GPU
64 obj
Color conv
pre blend.
RLE exp.
32bpp
Animate.
Alpha,
Pos,
Obj …
Blend
Color key
6 planes
Dither.
Gamma corr
CRC check
2D-ACE
25 TM
• The DCU combines layers or “sprites” to create the final content
− There are up to 66 different sources of content possible
64 programmable layers that contain source graphics
A cursor layer
1 layer as a default color for the background
− Layers are in a fixed priority to each other
− For each pixel position
the DCU fetches a pixel from the topmost layer placed there AND
a pixel from the next layer in the priority
and pixels from up to four further layers (dependent on user configuration)
− If indexed colors are used these are converted to 32bpp before processing
− The fetched pixels are then blended to give the display content for that position.
The blending attributes are determined per layer and the lowest priority pixel’s blending attributes are ignore
− Each resulting pixel can be gamma corrected
− The output format is 8-bits per channel(24bpp)
26 TM
• A layer is the mechanism by which graphics are displayed on the panel
• The DCU has a set of 9 registers to configure each layer
• The layer registers configure
− Height & width of layer (pixels)
− Signed position on panel (x,y)
− Pointer to graphic (32-bit)
− Graphic coding (bpp) & CLUT, blending, type, tile & safety
− Chroma limits (max & min)
− Tile size
− Transparency mode colors
x y
x y
x y
27 TM
28 TM
Layer 20:
16x480
(0,0)
YCbCr
Alpha:100%
Serial flash
29 TM
Layer 20:
800x480
(0,0)
YCbCr
Alpha:100%
Tile size: 16x480
Serial flash
30 TM
Layer 12:
800x430
(0,50)
8BPP
Alpha:100%
Simple chroma
DRAM
31 TM
Layer 10:
52x34
(350,70)
4BPP
Alpha:100%
SRAM
32 TM
Layer 8:
80x80
(100,350)
8BPP
Alpha:100%
Simple Chroma
Serial flash
Layer 9:
60x60
(80,348)
8BPP
Alpha:100%
Simple Chroma
SRAM
33 TM
Layer 6:
40x40
(5,120)
4BPP
Alpha:100%
Simple Chroma
Serial flash
Layer 6:
40x40
(400,30)
4BPP
Alpha:100%
Simple Chroma
DRAM
34 TM
35 TM
36 TM
• Full fixed function hardware vector graphics GPU
• Hardware Tessellation
• Minimum CPU involvement
• 16X FSAA
• Photorealistic quality
• No performance degradation
• Multi-format rendering
• sRGB color transformation
• Video image conversion
• High-quality vector font rendering support
• Dedicated GPU for QoS requirements
37 TM
• Vector graphics are drawn and stored as mathematical vector formulae
• Each vector and fill is assigned a color value, instead of assigning color to each separate pixel
• A black circle can be represented as:
− x = r cos θ y = r sin θ
or:
− r2 = x2+ y2
− With color value 0000 for black
• Benefits – Infinitely scalable
– Independent of screen resolution
– Saves data memory
38 TM
• Fully HW accelerated OpenVG pipeline
− Stage 1: Path, Transformation, Stroke, &Paint
− Stage 2: Stroked Path Generation
− Stage 3: Transformation
− Stage 4: Rasterization
− Stage 5: Clipping and Masking
− Stage 6: Paint Generation
− Stage 7: Image Interpolation
− Stage 8: Blending and Antialiasing
• Benefits:
− Continuous high frame rates; Outstanding 16X MSAA quality, Very low OpenVG CPU driver load
− Native rendering of true-type fonts, w/16x Anti-Aliasing
− Additional graphics acceleration for dual display systems
• Also used in i.MX6D/Q
Entire OpenVG pipeline hardware accelerated
Memory Controller
Host Interface
AHB AXI
Vector Graphics Pipeline Graphics
Pipeline
Front End
VG Pixel
Engine Vector Graphics Engine Imaging Engine
GC355 GPU Core
39 TM
Analogue Front
End (AFE)
Video
Decoder
(VDEC)
VIU
Graphics
Memory
YUV888,RGBnnn,
or ITU656
The “Video Subsystem” Analogue
In: CVBS
Digital Path
DCU TFT
LCD
Mux
Digital out:
YUV888
40 TM
• Integrated LCD driver with support up to 40 front-planes and 8 back-planes
− 160 LCD segments
− Adjustable for 3V3 only operation
− Operation can continue of stop mode if required
• Contrast adjustable in two ways
− VLCD control
− Contrast adjustment phases for electronic control of contrast
• Configurable for a wide range of LCDs
− Individual enables for front- and back-plane signals
− Bias voltage adjustable
− Ability to reconfigure BP and FP signals on the interface to adjust ratio of FP and BP
TM 41
42 TM
• Simple power supply – No PMIC needed
• Only two levels of power sequencing
− Controlled by Vybrid via NPN transistor
− In Low Power modes external NPN is turned off
• Need regulators for:
− 3.3V for main power
− 1.5V/.75V for DDR3; 1.2V/0.6V for LPDDR2
− 5V for USB Host
43 TM
• Run Mode
− High frequency using PLLs, all peripherals operational
• Low Power Modes
− Low Power Run (LPRUN) Mode – PLLs OFF, Sys clock is 24 MHz
− Ultra Low Power Run (ULPRUN) Mode – PLLs OFF, Sys clock is 32 kHz
− WAIT Mode – Both the CA5 and CM4 cores are halted
Optionally can keep core clocked to debug in WAIT mode
− STOP Mode – Cores halted, Peripheral clocks are gated off, Optional Regulator Power down, Deep Sleep option
• Power Gated Modes
− LPSTOP[3-1] - Peripheral clocks are gated off, power domains are de-energized, and some (or all) SysRam is lost
44 TM
Power Mode Current Consumption
Run Mode (@ A5=396 MHz, M4=132 MHz)
- Full Tower using TWR-LCD-RGB and
TWR-SER w/ Ethernet, DDR
600 mA
(Measured on 3.3V supply for
system)
Run Mode (@ A5=396 MHz, M4=132 MHz)
- Linux (150 Threads, 24FPS, 63% CPU)
using TWR-LCD-RGB + TWR-SER2, DDR
775 mA
(Measured on 3.3V supply for
system)
LPRUN (FIRC; with no PLLs) 16 mA
ULPRUN (Slow XOSC) 8 mA
STOP (with Well Bias) 4 - 5 mA
LPS3 (48K memory retained) 270 uA
LPS2 (16K memory retained) 250 uA
LPS1 (FIRC disabled, no memory retained) 40 uA
TM 45
46 TM
• Vybrid has no onboard flash. In order to store important non-
volatile, constant information we use fuses.
• For example: Serial No., MAC Address, Boot information
• Various Boot Interfaces Supported
− Quad SPI (QSPI[0:1])
− NOR Flash (FlexBus)
− SD/eSD/MMC/eMMC (ESDHC[0:1])
− NAND Flash (NFC)
− FlexCAN[0:1] (using Serial Download Protocol)
− Serial Flash (I2C[0:3]/DSPI[0:3]) (Recovery Boot)
− USB
− UART[0:3]
47 TM
• Various Boot Interfaces Supported
− Quad SPI (QSPI[0:1])
− NOR Flash (FlexBus)
− SD/eSD/MMC/eMMC (ESDHC[0:1])
− NAND Flash (NFC)
− FlexCAN[0:1] (using Serial Download Protocol)
− Serial Flash (I2C[0:3]/DSPI[0:3]) (Recovery Boot)
• Serial Download Interfaces
− USB
− UART[0:3]
48 TM
BootROM
BootROM retrieves code to SRAM,
then change program counter to
SRAM for U-Boot to start executing
BootROM changes Program
Counter to NOR/QuadSPI region. U-
Boot starts executing there.
SPI Flash SDCard NAND NOR QuadSPI Flash U-Boot
with boot
header –
u-boot.imx
49 TM
• Serial Flash:
− Communications interface between MCU and external flash memory
− Interface similar to standard SPI but optionally utilises 2 or 4 data lines to transfer Can optionally support DDR to further increase throughput
− Command driven interface
− Supports both 24- and 32-bit addressing.
• Quad Mode SDR Read Command Sequence:
50 TM
• Dual QuadSPI architecture supports:
− 2 external Serial Flashes per QuadSPI module
− SDR and DDR Serial Flash
− Programmable Sequence Engine for compatibility to any Serial flash
− Supports XIP (Execute-In-Place)
• QuadSPI can control 2 x 4-bit serial flashes :
− Accessed separately or….
− Parallel mode enabling ‘octal flash’ with data recombination internally in QuadSPI
• 66MHz clock => 132MByte/sec peak bandwidth
• Flexible Buffering Scheme:
− Sub-buffers allocated to specific masters.
− Master prioritization
− Pre-fetch capability
− Suspend & resume for lower priority masters
TM
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