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Design Methodology for High-Density FPGA Design. Selecting an Architecture High-Density Software Methodology Implementation and Integration of Cores. V400 FPGA. Transmitter. Channel Interface. PCI. CPU and Software. Channel Manager. Spectral Analysis. A/D. System Level FPGA. - PowerPoint PPT Presentation
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1Design Methodology
Design Methodology for Design Methodology for High-Density FPGA DesignHigh-Density FPGA Design
Selecting an Architecture
High-Density Software Methodology
Implementation and Integration of Cores
2Design Methodology
Spread Spectrum Frequency Channel Allocation Design
PCI
Channel Manager
TransmitterChannelInterface
A/D
V400 FPGA
CPU and Software
Spectral Analysis
System Level FPGASystem Level FPGA
3Design Methodology
Challenges of High-Density Challenges of High-Density FPGA DesignFPGA Design
How to Implement?
What ArchitectureArchitecture?
SoftwareSoftware Access to Architectural Features?
Verification StrategyVerification Strategy?
Use IP CoresIP Cores?
PCI
Channel Manager
TransmitterChannelInterface
A/D
Virtex V400 FPGA
CPU and Software
Spectral Analysis
4Design Methodology
AgendaAgenda Selecting an architecture
— system level FPGA— Smart-IP technology
High-density FPGA software methodology— design flow — accessing the architecture specific features— design verification
Implementation and integration of cores— CORE Generator— LogiCORE— AllianceCORE— design series
Software demo Roadmap
5Design Methodology
System-Level FPGASystem-Level FPGA
PCI
Channel Manager
TransmitterChannelInterface
A/D
CPU and Software
Spectral Analysis
Integrates with software tools?
High performance I/O standards?
Million system gates? Performance?
— 100 MHz
Memory?— SRAM, FIFO
IP friendly?— 133 MHz SDRAM 1 Gbit
Ethernet 66 MHz PCI
6Design Methodology
Only available from Xilinx
Xilinx Smart-IP TechnologyXilinx Smart-IP Technology
Xilinx Smart-IP Technology— architectures tailored to cores— intelligent software implementation— flexible core technology
Delivers:— high predictability— high performance— high flexibility
7Design Methodology
Xilinx Smart-IP Technology Xilinx Smart-IP Technology Architecture Tailored to Accept CoresArchitecture Tailored to Accept Cores
Advantages• Efficient Routing• Predictable Timing• Low Power
Xilinx Segmented Routing Non-Segmented Routing
Core1
Core2
8Design Methodology
Advantages• Portable RAM-based cores• 16x improved logic efficiency• High-performance cores
Local RAMavailable
to the Core
Distributed Memory
Xilinx Smart-IP Technology Xilinx Smart-IP Technology Architecture Tailored to Accept CoresArchitecture Tailored to Accept Cores
9Design Methodology
Enhances Performance & Predictability
Relative Placement
Other Logic Does Not Affect on the Core
Fixed Placement & Pre-defined Routing
GuaranteesPerformance
Guarantees I/O &Logic Predictability
Fixed Placement
I/Os
Xilinx Smart-IP Technology Xilinx Smart-IP Technology Pre-defined Placement & RoutingPre-defined Placement & Routing
10Design Methodology
Performance is independent of core placement and number of cores used in the device
Avoids the performance loss of non-segmented architectures
Xilinx Smart-IP TechnologyXilinx Smart-IP TechnologyDelivers Design PredictabilityDelivers Design Predictability
80 MHZ
80 MHZ
80 MHZ
80 MHZ
11Design Methodology
Performance is independent of device size
Xilinx Smart-IP TechnologyXilinx Smart-IP TechnologyDelivers Design PredictabilityDelivers Design Predictability
Avoids the performance loss of non-segmented architectures
12Design Methodology
Virtex EnablesVirtex Enables
PCI
Channel Manager
TransmitterChannelInterface
A/D
Virtex V400 FPGA
CPU and Software
Spectral Analysis
Integrates with software tools?
High performance I/O standards?
Million system gates?Performance?
— 100 MHz
Memory?— SRAM, FIFO
IP friendly?— 133 MHz SDRAM 1 Gbit
Ethernet 66 MHz PCI
System Level FPGA
13Design Methodology
AgendaAgendaSelecting an architecture
— system level FPGA— Smart-IP technology
High-density FPGA software methodology— design flow — accessing the architecture specific features— design verification
Implementation and integration of cores— CORE Generator— LogiCORE— AllianceCORE— design series
Software demo Roadmap
14Design Methodology
The Value of Xilinx PartnershipsThe Value of Xilinx PartnershipsThe most comprehensive “Open System” solutionThe most comprehensive “Open System” solution
Early software support for new devicesNew product development maximizing
architectural and synthesis capabilities– efficient timing constraints integration– high performance optimization engines tuned for
new Xilinx devices– direct optimization & mapping of Carry logic,
complex I/O, LUTs, CE, arithmetic operator
Joint definition of next-generation Solutions
15Design Methodology
Design Verification
Design Implementation
Design EntrySource Code
Design FlowDesign Flow
Functional Simulation
Timing Simulation
Top LevelHDL or Schematic
Netlist
Symbol/HDL
SynthesisUser design only
Netlist
Sim.Model
ConstraintsNetlist
Place & Route
HDL Editor
Design ReuseAllianceCORE
LogiCORE
SchematicEntry
Static Timing Analysis
Xilinx FPGA
16Design Methodology
XC4000XL family supported in A1.5, Virtex to follow
Software Features (ASIC-Like) Software Features (ASIC-Like) Minimum-delay reporting
— hold-time analysis— finds hazards in asynchronous logic— min delay option “-s min” for TRCE and NGDANNO
Voltage and temperature pro rating— can specify a higher voltage than worst case
– specify 3.3V instead of 3.0V— can specify a lower temperature than worst case
– specify 55°C instead of 85°C
First SRAM based device to support temp & voltage pro rating and minimum delays
17Design Methodology
Minimum DelayMinimum DelaySystem-Level AnalysisSystem-Level Analysis
Internally, Xilinx guarantees 0ns hold times
Identify board-level hold time violations for synchronous designs
SystemClock
Inst_A
Q
SystemClock
FPGA
SDRAM
Flip-Flop Hold time 1 ns
D
SystemClock
With max tco (for Inst_A) = 5 ns
With min tco (for Inst_A) = 2 ns
Q
Q
Valid data on Q forworst case delay
D
D Hold Time violation forbest case delay
1 ns
Data not latched}
}
18Design Methodology
Temperature and Voltage Pro ratingTemperature and Voltage Pro rating
Delays based on worst case process
Adjust temperature and voltage to reflect system operating conditions
Reduce system cost by targeting a slower speed grade
Parameter[ns]
Internal Period
Clock-to-Out
Input Setup
Parameter[ns]
Internal Period
Clock-to-Out
Input Setup
SystemRequirements
3.3V, 70°C
10.0
4.0
6.0
SystemRequirements
3.3V, 70°C
10.0
4.0
6.0
XLA–08V = 3.0VT = 85°C
10.6
4.2
5.8
XLA–08V = 3.0VT = 85°C
10.6
4.2
5.8
XLA–08V = 3.3VT = 70°C
9.0
3.7
5.2
XLA–08V = 3.3VT = 70°C
9.0
3.7
5.2
Meets Requirements
XLA–09V = 3.3VT = 70°C
9.4
3.9
5.4
XLA–09V = 3.3VT = 70°C
9.4
3.9
5.4
LowestCost
19Design Methodology
1 Million Gates1 Million GatesIn Less Than 5 HoursIn Less Than 5 Hours
Compile Times Gates Per Hour
150k
100k
50k
0
200k
A 1.5XC4000XL
A 1.5
Timing Driven Implementation
50kGates /hour
35kGates /hour
A 1.4XC4000XL
New place & route algorithms
Abundant & flexible vector based interconnect
— 4x routing resource vs XC4000XL
— fully populated switch matrix
Buffering of high fanout and long distance interconnects
— 8 ns across 250K system gates
Up to 40% smaller interface netlist
200kGates/hour
20Design Methodology
Faster Compiles with VirtexFaster Compiles with Virtex““Tough” Customer DesignsTough” Customer Designs
0100200300400500600700800
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Com
pile
Tim
e (m
inut
es)
Virtex compiles, on average, 28 times faster
Virtex -4XC4000XL-09
Design Suite
21Design Methodology
Faster Systems with VirtexFaster Systems with Virtex ““Tough” Customer DesignsTough” Customer Designs
0
100%
200%
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Design Suite
Nor
mal
ized
Clo
ck S
peed
Faster Virtex speeds with silicon characterized speeds files Virtex is faster for 84% of the designs Designs from ATM, PCI, Networking & ISDN applications
19
Virtex -4XC4000XL-09
22Design Methodology
Accessing Accessing Technology-Specific FeaturesTechnology-Specific Features
By inference — technology mapping using behavioral
constructs that allow code portability— operators — RAM
By instantiation — use gates in the target technology
making the code technology specific— Block RAM— CLKDLL— special I/Os.
23Design Methodology
Inferring Inferring Technology-Specific FeaturesTechnology-Specific Features Fast arithmetic carry chains
Wide input muxes, “case vs. priority encoder”
RTL flexibility for register configurations
Area-efficient muxes using TBUFs
Distributed RAM inferencing
Registered I/O buffer inference
Timing-driven register IOB mapping
24Design Methodology
180 MHz 32-bit arithmetic/counters
Small 16-bit adders using 16 LUTs — 51 for XC4000XL
60MHz 16x16 multipliers— 30% area reduction compared to XC4000XL— 160MHz with pipeline stages
Operator Inferencing from synthesis
Pipelined multipliers from the CORE Generator tool
0 1
0 1
0 1
0 1
Virtex Logic Block Carry
Fast Arithmetic Functions Fast Arithmetic Functions Using Carry ChainsUsing Carry Chains
if (!reset)count = 32’b0;
else count = count + 1’;
Sum = a_in + b_in
mult = a_in * b_in
LUT
LUT
LUT
LUT
25Design Methodology
in [4]
SS
S S
in [2]in [1]
in [0]
in [3]
Priority Encoder “if-then-else”Priority Encoder “if-then-else”When to use?When to use?
Assign highest priority to a late arriving critical signal Nested “if-then-else” might increase area and delay Use “case” statement if possible to describe the same function
always @(sel or in)begin if (sel == 3'h0)
out = in[0]; else if (sel == 3'h1)
out = in[1]; else if (sel == 3'h2)
out = in[2]; else if (sel == 3'h3)
out = in[3]; else if (sel == 3'h4)
out = in[4]; else
out = in[5];end
26Design Methodology
Benefits of “Case” StatementBenefits of “Case” Statement
CDEFGHIJ
S
Z
8:1 Mux
Compact and delay-optimized implementation— implemented in a single CLB
Synthesis maps to MUXF5 and MUXF6 functions 8:1 multiplexor is implemented in a single CLB
always @(C or D or E or F or S)
begin
case (S)2’b000 : Z = C;2’b001 : Z = D;2’b010 : Z = E;2’b011 : Z = F;2’b100 : Z = G;2’b101 : Z = H;2’b110 : Z = I;default : Z = J;
endcase
27Design Methodology
Register mapping for— registers with sync/async set and reset— clocks, inverted clocks, and clock enable
Positive-Edge Triggered Flip-Flop with clock enable, sync reset and preset
reset
data
clk
q
preset
ce
always @(posedge clk or posedge preset)begin if (preset)
q = 1; else if (reset)
q = 0; else if (CE)
q = data;end
RTL Flexibility RTL Flexibility for Register Configurationsfor Register Configurations
28Design Methodology
Area Efficient Muxes Using TBUFsArea Efficient Muxes Using TBUFs
Improve area efficiency by using tri-states Each CLB has 2 TBUFs Place-and-route can connect tri-states on multiple horizontal
Longlines to build wide muxes
E[3:0]
A[7:0]
B[7:0]C[7:0]D[7:0]
Z[7:0]
A[7:0]
B[7:0]
C[7:0]
D[7:0]
E0
E1
E2
E3
Z[7:0]
case (E) 4’b0001 : Q[7:0] = A[7:0]; 4’b0010 : Q[7:0] = B[7:0]; 4’b0100 : Q[7:0] = C[7:0]; 4’b1000 : Q[7:0] = D[7:0];endcase
assign Q[7:0] = E0 ? A[7:0] : 8'bzz..z;assign Q[7:0] = E1 ? B[7:0] : 8'bzz..z;assign Q[7:0] = E2 ? C[7:0] : 8'bzz..z;assign Q[7:0] = E3 ? D[7:0] : 8'bzz..z;
29Design Methodology
Distributed RAM InferencingDistributed RAM Inferencing System MemorySystem Memory
Synplicity (RAM 8x4)
Synplify and Leonardo Spectrum can infer distributed RAM FPGA Express will support RAM inferencing in the future
AO
A1
A2
A3D
WCLK
WE
Addr [2:0]
D [3:0]
clkwe
q [3:0]
RAM 16x1S
RAM 16x1S
Q
module ramtest(q, addr, d, we, clk); output [3:0] q; input [3:0] d; input [2:0] addr; input we; input clk;
reg [3:0] mem [7:0];
assign q = mem[addr]; always @(posedge clk) begin if(we) mem[addr] = d; endendmodule
AO
A1
A2
A3D
WCLK
WE
30Design Methodology
Registered I/O MappingRegistered I/O Mapping System InterfacesSystem Interfaces
System timing— chip-to-chip performance often limits
system speeds— registered I/O improves performance
No need to instantiate IOB register cells— implementation tools will pack registers
in the IOBs— map -pr b
– b (both input and output)– i (input only)– o (output only)
— IOB = TRUE attribute
Mapping for data and enable ports
S/R
D
CE
CLK
Q
OBUF
S/R
QCE
D
CLK
IBUF
S/R
D
CE
CLK
Q
OBUF
31Design Methodology
Controlling the InferenceControlling the Inferenceof Output Registersof Output Registers
Technology mapping will not duplicate registers
Critical signal will not be absorbed in the IOB register
OUT [23:0]
TRI TRI_R
CLK
D Q
DATA [23:0]
fanout = 24
process (Tri, Clk) begin if (clk’event and clk =`1`) then Tri_R <= Tri; end if;end process;
process (Tri, Data_in) begin if (Tri_R = ‘1’) then Out <= Data_in; else Out <= (others => ‘Z’); end if;end process;
32Design Methodology
Controlling the InferenceControlling the Inferenceof Output Registersof Output Registers
Duplicates register on critical path for fanout of 1
Mapping will absorb register in IOB
TRI
CLK
D QTRI_R1
DATA [23] OUT [23]
fanout = 1
TRI
CLK
D QTRI_R2
OUT [22:0]DATA [22:0]
fanout = 23
process (Tri_, Clk) begin if (clk’event and clk =`1`) then Tri_R1 <= Tri; Tri_R2 <= Tri; end if; end process;process (Tri_R1, Data_in) begin if (Tri_R1 = ‘1’) then Out(23) <= Data_in(23); else Out(23) <= ‘Z’); end if;end process;process (Tri_R2, Data_in) begin if (Tri_R2 = ‘1’) then
Out(22:0) <= Data_in(22:0); else
Out(22:0) <= (others => ‘Z’); end if;end process;
33Design Methodology
Instantiating Instantiating Technology-Specific FeaturesTechnology-Specific Features
Block RAM— system memory
CLKDLL— minimizes clock skew
Special I/Os— interfacing with standard buses
LUTs for datapath pipelining— add latency with minimal area impact
34Design Methodology
RAMB4_S1
doDO
addr
enwe
rst
clk
di
ADDRWEENRST
D
CLK
Block RAM System MemoryBlock RAM System Memory
component RAMb4_S1port(WE,EN,RST,CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(11 downto 0); DO: out STD_LOGIC; DI: in STD_LOGIC_VECTOR(0 downto 0));end component;
begin U1: RAMB4_S1 port map(WE=>WE, EN=>EN, RST=>RST, CLK=>CLK, DI=>DI, ADDR=>ADDR, DO=>DO);
RAMB4_S1 U1 (.WE(WE), .EN(EN), .RST(RST), .CLK(CLK), .ADDR(ADDR), .DI(DI), .DO(DO));
Instantiate single- and dual-port RAM Use the CORE Generator to build RAM and FIFO (Q1 ‘99)
35Design Methodology
Verilog
BUFG
CLKIN
CLKFB
RST
CLKDLLCLK0
CLK90CLK180CLK270CLK2XCLKDV
LOCKED
IBUFG
U4
clkin
rst
clk_fb
CLKDLL Minimize CLKDLL Minimize Clock-to-Out System TimingClock-to-Out System Timing
One use of a CLKDLL is to minimize clock to outpad delay— removes all delay from external GCLKPAD pin to the registers and RAM
BUFGDLL is available for instantiation Other configurations can be built by instantiating the CLKDLL macro
wire clk_fb;BUFGDLL U4 (.I(clkin), .O(clk_fb));
36Design Methodology
Default I/O buffer is LVTTL (12mA), available via inference— process technology leads to mixed voltage systems— high-performance, low-power signal standards emerging
Instantiate I/O buffers for non default current drive— non-default voltage standard— non-default slew
Advanced Graphics Port bus interface (Pentium II graphics app)
Fast slew rate and 24 mA drive strength
OBUF_AGP U0 (.I(awire), .O(oport));
OBUF_F_24 U1 (.I(awire), .O(oport));
awire oport
U0
awire oport
U1
Special I/O BuffersSpecial I/O BuffersSystem InterfacesSystem Interfaces
37Design Methodology
LUTs for Datapath PipeliningLUTs for Datapath Pipelining LUT can be used in place of registers to balance pipeline stages
— area efficient implementation
SRL16E can delay an input value up to 16 clock cycles Synchronized operands before the next operation
F
GH
A[31:0]
B[31:0]
C[31:0]
Z
8 cycles5 cycles
1 cycle
SRL16EDCE CLKA3A2A1A0
Q7
SRL16EDCE CLKA3A2A1A0
Q12
32 LUTs replace 256 registers
32 LUTs replace 416 registers
38Design Methodology
Design VerificationDesign Verification
Trends
Stages
Xilinx solutions
39Design Methodology
What’s Driving the What’s Driving the Verification Trends?Verification Trends?
Functional simulation should eliminate 95% of the bugs
Design Cycle Stages
FunctionalSimulation
Synthesis PAR SystemTest
EndProduct
Cost of Design Error Over Time
$$$
10,000X
1000X
100X
10X1X
40Design Methodology
Stages to Verify the DesignStages to Verify the Design
Synthesis
VHDL or Verilog
Implementation
Gate-level Functional Simulation Checks the synthesis implementation to gates Test initialization states Analyze ‘don’t care’ conditions
Gate-level Timing Simulation Post implementation timing simulation Test race conditions Test set-up and holds violations based on
operating conditions
Gate-level Functional Simulation Create testbench Verifies syntax & functionality Majority of design cycle time Errors found are inexpensive to fix
testbench
41Design Methodology
UNISIMUNISIMLibraryLibraryUNISIMUNISIMLibraryLibrary
SIMPRIMSIMPRIM
LibraryLibrarySIMPRIMSIMPRIM
LibraryLibrary
SIMPRIMSIMPRIM
LibraryLibrary
Simulation
What Does Xilinx Provide?What Does Xilinx Provide? Libraries and interfaces for simulation
throughout the design flow— functional simulation with UNISIM — timing simulation with SIMPRIM
Mixed-mode simulation— schematic and HDL
Minimum-delay analysis
Voltage and temperature prorating
Unique VHDL simulation of global set/reset capabilities
VHDL or Verilog
Synthesis
Implementation
42Design Methodology
Benefits of the Xilinx FPGABenefits of the Xilinx FPGASoftware Development MethodologySoftware Development Methodology ASIC-like design flow and features
— open development system— minimum delays and temp pro rating— robust Verification Flow
Improve designer productivity— faster compile times, better performance
Utilizing device resources— technology independence since most technology features
are accessible via inference— use techniques to reduce area and increase performance
43Design Methodology
AgendaAgendaSelecting an architecture
— system level FPGA— Smart-IP technology
High-density FPGA software methodology— design flow — accessing the architecture specific features— design verification
Implementation and integration of cores— CORE Generator— LogiCORE— AllianceCORE— design series
Software demo Roadmap
44Design Methodology
Implementation and Implementation and Integration of CoresIntegration of Cores
IP
A
IP
B
IP
C
PCI PCMCIA HDLC Reed-Solomon MPEG T1 Framer DRAM Controller DMA Viterbi Decoder FIR Filter
45Design Methodology
High-Density FPGA High-Density FPGA Design ImplementationDesign Implementation Xilinx CORE Generator
— reduces time to market— delivers parameterizable cores— optimized using SmartIP technology
LogiCORE products— licensed and supported by Xilinx— highly optimized for Xilinx FPGAs results
in best possible performance, area and predictability
AllianceCORE products— licensed and supported by Xilinx’ partners— 25 partners provides industry’s widest selection
of cores and design expertise
Design services— 3rd party and Xilinx design centers— local expertise and services
46Design Methodology
PCI
Channel Manager
TransmitterChannelInterface
A/D
Virtex V400 FPGA
CPU and Software
Spectral Analysis
Xilinx CORE Generator Xilinx CORE Generator IP Delivery SystemIP Delivery System
47Design Methodology
Benefits of Using Xilinx CoresBenefits of Using Xilinx Cores
Reference Design,Generic Core
Complete FPGACore Solution
Design From Scratch
Pre-verified Designs
Area & Timing Optimized
Complete & Flexible Design
Little Knowledge of Function Required
L
Design
D
Verify
V
Learn
V
I
Implement
IL
D
2 Months 9 Months 12 Months
48Design Methodology
Benefits of Using Xilinx CoresBenefits of Using Xilinx Cores
“75% of all new designs will have Cores in them” - Designer feedback from IP usage survey
“The high performance of the Xilinx PCI LogiCORE solution combined with the short time to market and flexibility of a programmable FPGA solution, made Xilinx the obvious
choice." - Tony Clark, R&D Mgr. - Management Graphics, Inc
“By using ‘Design Reuse’ as part of our design consulting services, on average we are able to save our customers 18-24 weeks” - Tim Smith of Memec Design Services
49Design Methodology
Data sheets
CoreLINX:
SystemLINX:
Web Mechanism to Download New Cores
Third-Party System Tools Directly LinkedWith Core Generator
Parameterized Cores
Free Software & Free Cores Included As Part of TheAlliance and Foundation Software Packages
CORE Generator Delivery SystemCORE Generator Delivery System Xilinx Smart-IP TechnologyXilinx Smart-IP Technology
50Design Methodology
Core Generator DemoCore Generator Demo
51Design Methodology
PCI
Channel Manager
TransmitterChannelInterface
A/D
Virtex V400 FPGA
CPU and Software
Spectral Analysis
Xilinx LogiCOREXilinx LogiCORE
52Design Methodology
Xilinx LogiCORE Xilinx LogiCORE
Licensed and supported by Xilinx
Highly optimized for Xilinx FPGAs — module based design flow— best possible performance, area and predictability
Building blocks— can be used as-is, or as foundation for high-level cores— give users access to architectural features through automatic tools
(e.g., LUT and memory)— examples: Basic Logic, Arithmetic, Counters, Memories
Standard cores— enable high-performance DSP and PCI applications— use unique implementation techniques to deliver unparalleled
performance, area and predictability
53Design Methodology
A Complete PCI Solution A Complete PCI Solution Enables Cost-Effective DesignsEnables Cost-Effective Designs
Widest range of compliant PCI cores— LogiCORE PCI32 (32-bit, 33 MHz cores)— LogiCORE PCI64 (64/32-bit, 33-66 MHz cores)— all support fully compliant 0 wait-state burst
Synthesizable bridge designs— reusable PCI bridge design examples
Hot PCI prototyping board - Virtual Computer Corp.
PCI driver development tools and reference drivers - Vireo Software Inc.
54Design Methodology
Power by
The Real-PCI™ 64/66 Solution The Real-PCI™ 64/66 Solution from Xilinxfrom Xilinx
Real compliance (PCI v2.2)— based on de-facto industry standard PCI FPGA core— only FPGA solution with guaranteed timing— Compact PCI Hot-Swap friendly
Real flexibility— first 66 MHz PCI core implemented in standard FPGAs
Real performance— full 528 MB/s sustained bandwidth
55Design Methodology
PCI32 Spartan - Lowest Cost PCIPCI32 Spartan - Lowest Cost PCI
Standard Chip
External PLD7K Gates
7K Gates Logic
Com
pone
nt c
ost 1
00K
uni
ts
Standard ChipPCI Master I/F
XCS20XL-4 TQ144*
Solution <$7Solution <$7
PCI Master I/F
* Supported devices:XCS20XLXCS30XLXCS40XL
Power by$5
$20
$10
$15
56Design Methodology
Combined Flexibility and Combined Flexibility and PredictabilityPredictability
Only PCI cores for FPGAs with guaranteed timing — including 2ns clock-to-out min timing, and 0 ns hold — FPGA characterized together with core— pre-defined critical placement and routing
First parameterizable PCI core on the web— instant access to new design files
First core with modular architecture— core de-coupled from back-end design— back-end customizable without affecting PCI timing
57Design Methodology
Design FlowDesign Flow
Functional Simulation
Timing Simulation
Design VerificationCORE Configuration Design Entry
User DesignHDL or Schematic
Netlist
Symbol
Sim.Model
SynthesisUser design only
CORE Designzip or tar
Netlist
ConstraintsNetlist
Design Implementation
Place & Route
58Design Methodology
Accelerate Your DSP ProcessorAccelerate Your DSP Processor
Performance of a custom IC
Flexibility of a DSP processor— >10 times the performance— lower cost— lower power
Replaces multiple DSP processors
Replaces DSP building block ICs
Implement the cycle intensivealgorithms in an FPGA
GIG
A-
MA
Cs
/Sec
S40HighestPerformance
DSP Processor
1
2
3
45
4085
6
7
8
9
10 16-bit FIR FilterBenchmark
Virtex
59Design Methodology
ApplicationsApplications
High performance— data sample rate (> 1MHz) or multiple channels— alternative to multiple DSP processors— alternative to custom ICs
Video, image processing, HDTV, set top boxes— image resizing, enhancement
Data communications, wired & wireless— narrow-band filters, multi-rate filters
Military communications, surveillance, radar, sonar
Data encryption - fast, wide multipliers
60Design Methodology
A Complete High-Performance A Complete High-Performance Programmable DSP SolutionProgrammable DSP Solution
Spartan, XC4000, Virtex
Design tools and DSP IP— LogiCORE & AllianceCORE— CORE Generator software — Elanix - SystemView - integration
DSP prototyping boards
DSP starter kit
DSP support— DSP FAEs, design services
System-LevelDSP Modeling
Tools
DSPFunctions
61Design Methodology
PCI
Channel Manager
TransmitterChannelInterface
A/D
Virtex V400 FPGA
CPU and Software
Spectral Analysis
Xilinx AllianceCOREXilinx AllianceCORE
62Design Methodology
ProgramProgram
Partnerships with leading third-party IP providers
Complete programmable logic solutions— proven Xilinx cores— test benches, debug software— hardware evaluation boards
License directly from partner— Xilinx netlist and source code versions— Partner guarantees functionality
Information on the Xilinx web site— www.xilinx.com/products/logicore/alliance/tblpart.htm
63Design Methodology
Released Products*Released Products*
Bus InterfacesCANFireWire (IEEE 1394)I2CPCMCIA (2 types)USB (3 types)
CommunicationsATM Cell AssemblerATM Cell Delineation10/100 Ethernet MAC (2)CRC (10- & 32-bit)DES EngineHDLC (2 types)Reed Solomon T1 FramerUTOPIA (master & slave)Viterbi Decoder
Image ProcessingYUV to RGB
Processor PeripheralsUARTs (7 types)2910A8237825182548255 (3 types)82568259 (2 types)82799128DRAM ControllerSDRAM Controller
RISC Processors (2 types)Demo Boards & Software (15)
*As of January, 1999
Design Methodology64
Partners*Partners*
Merged with…
G & AssociatesV
*As of January, 1999
65Design Methodology
PCI
Channel Manager
TransmitterChannelInterface
A/D
Virtex V400 FPGA
CPU and Software
Spectral Analysis
Xilinx XPERTS ProgramXilinx XPERTS ProgramXXilinx ilinx PProgram for rogram for EEngineering ngineering RResources from esources from TThird partiehird partieSS
66Design Methodology
Xilinx certified consultants
Local design services support— ease the targeting of new architectures— PCI, DSP specialists
– Accelerate IP design methodology
Cost advantage— Xilinx optimized solution
Partners in all major cities world wide
Xilinx XPERTS ProgramXilinx XPERTS ProgramXXilinx ilinx PProgram for rogram for EEngineering ngineering RResources from esources from TThird partiehird partieSS
67Design Methodology
Partner ProfilePartner Profile
Specialists in PCI Core customization and integration
DSP specialists — expertise and experience in datacom, telecom, XDSL,
networking, video and image processing algorithm designs
Specialists in HDL-based team-based designs and ASIC to FPGA conversions
Details on www.xilinx.com/company/consultants/index.htm
68Design Methodology
Benefits of Xilinx FPGA Benefits of Xilinx FPGA Design ImplementationDesign Implementation
Complete programmable logic solutions Xilinx CORE Generator
— pre-verified designs— complete and flexible design— module based design— improved time to market
LogiCOREs - “Expertise without the effort”— Smart IP technology— minimum knowledge of function required— design optimized for speed and area
AllianceCORE IP and XPERTS design services partnerships— Leading providers of third-party IP and design services— Smart IP technology*— world-wide access to expertise
*All AllianceCORE modules are optimized for Xilinx
69Design Methodology
PCI
Channel Manager
TransmitterChannelInterface
A/D
Virtex V400 FPGA
CPU and Software
Spectral Analysis
Software DemoSoftware DemoPutting It All TogetherPutting It All Together
70Design Methodology
Software Design Flow DemoSoftware Design Flow Demo
71Design Methodology
RoadmapRoadmap
Software
Cores
Web Access and Resources
72Design Methodology
Major Software Features 2.1Major Software Features 2.1
Floorplanning— detailed and modular physical layout (manual or from synthesis)— interface to 3rd party RTL floorplanners
Implementation— place-and-route optimized for modular area constraints— critical timing path optimization within modules— much faster runtime for large designs
– Compile million gates under 1.5 hours in 1999— STAMP models for board-level static timing analysis
Guided iterations for synthesis designs— only changed modules must be re-placed and rerouted— reduces runtime and verification time for unchanged modules
73Design Methodology
Virtex IP RoadmapVirtex IP RoadmapReference LogiCORE with
Design Smart-IP
PCIPC164/33 1Q99PC132/33 1Q99PC164/66 2Q99PC132/66 2Q9964-bit Bridge with FIFO & DMA 1Q9932-bit Bridge with FIFO & DMA 1Q99Power Management 1Q99
Memory LibrarySingle-Port BlockRAMs NowDual-Port BlockRAMs NowSingle-Port Distributed RAMs 2Q99Dual-Port Distributed RAMs 2Q99Synchronous FIFOs Now 2Q99Asynchronous FIFOs Now 2Q99
Math LibraryCombinatorial Multipliers 2Q99Pipelined Multipliers 2Q99Constant Coefficient Multipliers 2Q99
Reference LogiCORE withDesign Smart-IP
PCIPC164/33 1Q99PC132/33 1Q99PC164/66 2Q99PC132/66 2Q9964-bit Bridge with FIFO & DMA 1Q9932-bit Bridge with FIFO & DMA 1Q99Power Management 1Q99
Memory LibrarySingle-Port BlockRAMs NowDual-Port BlockRAMs NowSingle-Port Distributed RAMs 2Q99Dual-Port Distributed RAMs 2Q99Synchronous FIFOs Now 2Q99Asynchronous FIFOs Now 2Q99
Math LibraryCombinatorial Multipliers 2Q99Pipelined Multipliers 2Q99Constant Coefficient Multipliers 2Q99
74Design Methodology
Virtex IP RoadmapVirtex IP RoadmapReference LogiCORE with
Design Smart-IP AllianceCORE
Filter LibraryFIR Building Blocks 2Q99FIR Filters 2Q99FFT 1Q99
Bus Application LibrarySDRAM Controller 1Q99 1Q99DMA Controller 2Q99PowerPC Interface 1Q99UART 1Q9982xx Cores 1Q99
Communication LibraryReed Solomon Encoder 1Q99Reed Solomon Decoder 1Q99Viterbi 2Q99HDLC 2Q99622 MBPS SONET 2Q99
Image Processing LibraryJPEG Encoder 2Q99
Reference LogiCORE withDesign Smart-IP AllianceCORE
Filter LibraryFIR Building Blocks 2Q99FIR Filters 2Q99FFT 1Q99
Bus Application LibrarySDRAM Controller 1Q99 1Q99DMA Controller 2Q99PowerPC Interface 1Q99UART 1Q9982xx Cores 1Q99
Communication LibraryReed Solomon Encoder 1Q99Reed Solomon Decoder 1Q99Viterbi 2Q99HDLC 2Q99622 MBPS SONET 2Q99
Image Processing LibraryJPEG Encoder 2Q99
75Design Methodology
Xilinx IP CenterXilinx IP CenterWeb-Based ResourcesWeb-Based Resources
Core solutions — What’s new— IP catalog
– LogiCORE– AllianceCORE– reference designs
— Products and services— Departments
– PCI– DSP– telecom
— Tools– Core Generator– PCI configuration demo
www.xilinx.com/ipcenter
76Design Methodology
High-Density FPGA LeadershipHigh-Density FPGA LeadershipAddressing the ChallengesAddressing the Challenges
Development platforms — SmartIP technology - predictable, high performance, flexible— Modular design - enables “system level FPGA”— Virtex - predictable high speed, high density, fast flexible I/O, RAM
Software methodologies— Open development system - joint development, early access— ASIC like design flows - min delays, pro-rate temp, verification flow— Access to device resources - technology independent, optimized for
Speed and area— Improved productivity - faster compile times, better performance
77Design Methodology
High-Density FPGA LeadershipHigh-Density FPGA LeadershipAddressing the ChallengesAddressing the Challenges
Design Implementation — Xilinx CORE Generator - Smart-IP technology, predictable, high
performance, flexible, updateable from the Xilinx web site
— Complete & Compliant PCI - 64/66MHz, low cost 32/33MHz, synthesizable bridge, prototyping boards & drivers
— Complete DSP Solutions - fast, low cost, low power, slew of DSP Cores, system level tools & prototyping boards
— AllianceCORE Partnerships - focused on vertical solutions, over 25 partners, over 50 cores, verification tools & prototype boards
— Multi-Level Support - expert FAE, 3rd party consulting, XPERTS, Xilinx design center
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