Decimal to binary Read from right to left 1001 = 2^0+2^3 = 1 + 8 = 9

Decimal to binary• Read from right to left

•1001 = 2^0+2^3 = 1 + 8 = 9

Unsigned and Signed Notation

1 0001101

• 1 0001101 in unsigned notation is 128+1+4+8 = 141

• 1 0001101 in signed notation is -1 + -4 + -8 = -13

• 1 means a negative number and 0 means a positive number.

Excess notation.10001101 in excess notation is the unsigned – 2^8 -1

Unsigned = 141 so;141 – 2^8-1 = 14 = excess value.

This is assuming it is 8bit. (if it was 16 bit it would be 2^16-1.

Two’s compliment with 1001100

• A quick method to find the solution is:• 1001100 (signed)• 0110100 (switch 0’s and 1’s after the first 1)

• -0110100 (the answer should be signed).

Ans: -01101002

Ans: -5210

Benefits and disadvantages

• Unsigned – cant be negative• Signed – two representations of 0• Signed – Difficult for arithmetic• Signed – Can represent negative values• Excess – Two numbers can be compared easily• Excess – Can represent negative numbers• Twos Compliment – Arithmetic easily done and

can represent negative numbers easily.

Floating point representation• 11000011100010100000000000000000• Signed bit, Biased Exponent, Normalised Mantissa

• Signed bit determines if its negative or positive• Biased Exponent can be used to workout the real exponent

which is 2^8-1(127) less than the 8 digit value shown.• Normalised Mantissa should be converted to the real

mantissa by adding a 1. at the beginning and continuing the number until you reach the last 1 in the sequence. So:

• Real mantissa = 1.000101• Final representation is –(1.000101)*2^8 = -100010100.• The decimal point is moved 8 places along because of multiplying by 2^8

Ans: 100010100 = -256+-16+-4 = -276.

Cache Memory• Enhances a computers performance using temporal

locality principle and spatial locality principle.• Temporal Locality Principle holds recently used data• Spatial Locality Principle collects nearby nodes to

recently used pieces/chunks of data.

CPU CacheMain

memory

Cache Mapping

• Associative mapped cache – Each memory block can be stored in any slot within the cache.

• Direct Mapped Cache – Each block in the main memory is assigned its own slot in the Cache memory.

• Set Associative Mapped Cache – Blocks in the main memory can be stored in a set of slots in the cache

Address Bus, Data Bus and Control Bus

Control unit

ALU

RegistersMAR

MBR

Address bus

Data bus

Control bus

• Address bus: this determines the location in memory that the processor will read data from or write data to.

• Data bus: this contains the contents that have been read from the memory location or are to be written into the memory location.

• Control bus: this manages the information flow between components indicating whether the operation is a read or a write and ensuring that the operation happens at the right time.

Address Bus, Data Bus and Control Bus

CPU fetch execute cycle

• Without pipelining

• A two-stage cycle.• Suppose we have 3 instruction I1, I2, I3.

– Without pipelining this will take 6 time units.

1 2 3 4 5 6Fetch I1 I2 I3

Execute I1 I2 I3

CPU fetch Execute cycle with pipelining

• With pipelining

• A two-stage cycle.• Suppose we have 3 instruction I1, I2, I3.

– With pipelining it will take only 4 time units.

1 2 3 4 5 6Fetch I1 I2 I3

Execute I1 I2 I3

Disadvantages of Pipelining

• Data hazards - Data hazards occur when data is modified. For example one instruction may still be running before another one ends.

(Hence why increasing the number of pipeline stages doesn’t necessarily increase performance. )

• Structural hazards – occurs when two instructions are trying to access the same memory resource. Causing a ‘queue’.

• Control hazards – occurs when the processor is told to branch. Can cause the processor to perform unwanted actions.

Memories: CPU register

• Program Counter (PC) – Contains the Address of the Next Instruction

• Instruction Register (IR) – Holds instructions just fetched from the main memory.

• Accumulator(AC) – A temporary register for when the instructions executed.

• Memory Address Register (MAR) – Stores the address of the cell the CPU is about to execute.

• Memory Buffer Register (MBR) – Contains Instruction or data just read from the memory.

• (think back to the audio array buffer in AV)

Memories: CPU register

A model of an operation System

Operation System

User command interface

Resource management

Process Manager

Memory manager

Device Manager

File manager

Network manager

Resource Management

Resource management

Process Manager:• Determines the next program to be

executed. • Time to be given to each program?

Memory manager:• Best use of the memory to run as many programs as possible

I/O Device (e.g.printer) Manager:• Determines which program should use a

particular I/O device.Network manager:

• Determines which computer should execute a particular program.

Starting up

OperatingSystem

Main memory

BootstrapProgram

Operating System

Disk storage ROM

RAM

Input/Output (I/O) Management

• There are four main I/O operations.–Control: tell the system to perform

some action (e.g. rewind tape).–Test: check the status of the device–Read: read data from the device–Write write data to the device.

Polling (Programmed) I/O

• The CPU controls the device directly via the module.

• The CPU sends a command to the module and waits until the operation is completed before sending another command.

• The performance is BAD as the CPU spends too much time waiting for the device.

Issue Read to I/O module

Check status

Read word from I/O module

Write word To memory

done

yes

NO

Next instruction

Ready

Interrupt Driven I/O Management.

• The CPU issues a command to the I/O module and then continues executing other instructions.

• The I/O module interrupts the CPU when it is ready with the data. Then the CPU takes the data.

Issue Read to I/O module

Check status

Read word from I/O module

Write word To memory

done

yes

NO

Ready

CPU goes to do Other things

When the statusIs ready the I/O module sendsAn interrupt-signal

Disadvantages of Interrupt Driven I/O

• CPU is responsible for managing I/O data transfer.

• Every transferred word must go through the CPU.

• Devices with large transfer, e.g. disk drive, the CPU wastes time dealing with data transfer.

• Solution: Direct-memory-access(DMA).

Direct-Memory Access (DMA)

• Directly accesses the memory without intervention from the CPU

• Special-purpose processor.• Handles data transfer.• DMA sends an interrupt to the CPU when the

transfer is completed.

System bus

CPUMain

memoryI/O module

I/Odevice

DMA

Memory management

• When a process is executed it has to be in main memory as the main memory can be accessed quicker.

• An efficient use of the main memory is an important task of the operation system.

• Different memory management techniques are used for this purpose.

Memory Partitions• How processes are arranged in the main memory

before been executed?• Fixed-sized partitions Variable-sized partitions

OS 8M

8M

8M

8M

8M

OS 8M

2M

4M

8M

18M

Memory Management TechniqueSwapping

• I/O operations are slow • If a running process requires an I/O

operation. The CPU will move to another process in the main memory.

• Suppose the main memory is full of processes waiting on I/O.

• CPU becomes idle• To solve this problem Swapping technique

is used.

Simple Paging (inefficient)

• Better than fixed and variable-sized partitions.• OS - loads all pages of a process in the main

memory.• However, not all pages of a process need to be

in the main memory in order to be executed.• OS - can still execute a process if only some of

the pages are loaded

Demand Paging (efficient)

• Loads a page only when it is required• No swapping in or out of unused

pages is needed.• Better use of memory.• CPU can access only a number of

pages of a process at one time then asks for more pages to be loaded.

Multithreading vs Single Threading

HTML, XML, XHTML, CSS

• Hypertext Mark-up Language (HTML)• eXtensible Mark-up Language (XML)• eXtensible Hypertext Mark-up language

(XHTML)• Cascading Stylesheets (CSS)

XHTML• ADVANTAGES AND DISADVANTAGES

XHTML has better security features.XHTML elements must be properly nestedXHTML elements must always be closedXHTML elements must be in lowercaseXHTML documents must have one root elementXHTML Does not have error tolerance

HTML

• Easy to use• Loose Syntax (error tolerance)• Widely used• Compatible with nearly every browser.• Security features offered by HTML are limited• Deprecated tags because of updates

• ADVANTAGES AND DISADVANTAGES

XML

• You can define your own tags• Reflects the structure and semantics of

documents and better navigation.• Tagging is separate from display.• Allows a single document to be used many

ways.

Why XHTML?

• XHTML is a combination of HTML and XML (EXtensible Markup Language).

• XHTML consists of all the elements in HTML 4.01, combined with the strict syntax of XML.

(The browser doesn’t have to fix it for you)

HTML to XHTML• Change tags to lowercase• Quote attribute values and expand attributes.• Closing open elements• Nesting inline elements inside block elements• Removing presentational mark-up• Changing name to id and encoding

ampersands• Changing the document type

Advantages of CSS

• Allows you to format a whole website in one single file by creating variables to reference to from your XHTML or HTML files.

• Ability to edit multiple pages just by changing a single variable in the CSS file.

• Consistency of look across pages.

ID and Class Selector

• The id selector is used to specify a style for a single, unique element.

• #para1{text-align:center;color:red;}

• The Class Selector is used to specify a style for a group of elements.

• .center {text-align:center;}• p.center {text-align:center;}

Computer Networks

• TCP/IP model • Layer 4: Application• Layer 3: Transport• Layer 2: Internet• Layer 1: Network access

Figuring out the Subnet AddressWhat is the subnetwork address if the destination address is 200.45.34.56 and the subnet mask is 255.255.240.0?

Convert the address to binary

11001000 00101101 00100010 00111000

200 . 45 . 34 . 56

Convert the subnet mask to binary

11111111 . 11111111 . 11110000 . 00000000

255 . 255 . 240 . 0

Apply the AND operation to the subnet (address AND subnet)

11001000 . 00101101 . 00100000 . 00000000 (are both a 1? Else 0).