CSC 6001 VLSI CAD (Physical Design)

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CSC 6001VLSI CAD (Physical Design)

January 23 2006

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“Graph Based Algorithms for Boolean Function Manipulation”, Randal E. Bryant, IEEE Transactions on Computers, Vol C-35, No. 8, 1986

Graph-based Representation of Boolean Functions

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Motivation

If you have 2 boolean functions:

f(x1, x2, …, xk) and g(x1, x2, …, xk)

How do you know if they represent the same function?

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Motivation

f(x1, x2, …, xk) g(x1, x2, …, xk)

Gf Gg

Then we can compare graph Gf and Gg.What properties should these graphs have foreasy comparison?

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Motivation

We want the graph representation to be:

– Unique for each boolean function.

– Can be operated on just like the boolean functions.

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Ordered BDD

• A data structure to represent boolean function.

• Directed acyclic graph (DAG)• Only one root node and two terminal nodes.• One terminal node labeled 0 and the other 1.• All non-terminal nodes are labeled with

variable names.

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Ordered BDD

a

cb

0 1

a=0a=1

b=1b=0

c=1c=0

This representsthe function:

f = ab + c

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Ordered BDD

• Every internal node has 2 successors.

• “Ordered” means that if x < y, then all nodes labeled x precede all nodes labeled y in the BDD.

• From now onwards, we will label the non-terminals with the orders of the variables only.

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Examples

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1 0

01

1

2 2

1 0

0 1

3 3

011

0

•••

•••

What are these functions?

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Notations

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32

0 1

01

1

0

10

index(v)

vnon-terminal

terminalvalue(u)

u

high(v)

low(v)

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BDD Boolean Function For each node v, the subgraph rooted at v

represents a function fv defined recursively as follow:– If v is a terminal node:

• If value(v) = 1, then fv = 1.

• If value(v) = 0, then fv = 0.

– Else, v is a non-terminal with index(v) = i: fv(x1, …, xn) = xi f low(v) (x1, …, xn) +

xi f high(v) (x1, …, xn)

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Example1

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0 1

01

1

01

0 4

10

What boolean functiondoes it represent?

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Reduced BDD A BDD is reduced if it contains no:

– node v with low(v) = high(v), nor– distinct nodes v and v’ such that he subgraphs

rooted at v and v’ are identical.

1

3

2

0 1

3

2

0 1

1

11

10

0 0

How to reducethis BDD?

0

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Uniqueness of Reduced BDD

Theorem: For any boolean function f(x1, …, xn), there is a unique reduced BDD representing f with variable ordering x1< …< xn.

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Ordering Dependency1

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4

5

6

0 1

1

1

1

1

1

10

0

00

0 What is this function?

What if we change the order to:1 3 5 2 4 6

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Ordering Dependency

Consider x1xn+1 + … + xnx2n

fb1,…bn(xn+1, …, x2n) = b1xn+1 + … + bnx2n

For all 2n possible combinations of the values b1, …, bn, each of these functions is distinct and they must be represented by distinct subgraphs in the BDD. Therefore, there exists at least 2n nodes in the reduced BDD.

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Inherently Complex Functions

Integer multiplier: Input: a1, …, an and b1, …, bn

Output: c1, …, c2n representing the integer ab.

Theorem: For any ordering of the inputs, at least one of the 2n functions for c1, …, c2n requires a graph containing at least 2n/8 nodes.

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Circuit Partitioning by Network Flow Approach

“Efficient Network Flow Based Min-Cut Balance Partitioning”, Yang and Wong, ICCAD, pp.50-55, 1994.

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k-Way Partitioning Problem Formulation:

Given a netlist of n cells V = {v1, v2, …, vn}, assign the cells to k clusters Pk = {C1, C2, …, Ck} satisfying some given constraints such that an objective function F(Pk) is optimized.

Partitioning: k is small O(1) Clustering: k is large O(n) Technology Mapping: Constraints on the clusters.

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Network Flow Technique

s t

a b

c d

16

13

10 4 9 7

12

20

4

11

s t

a b

c d

11/16

12/13

10 1/4 9 7/7

12/12

19/20

4/4

11/11

min-cut = max-flow

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Network Flow Technique

• The network flow technique can find the min-cut bipartition optimally, but not necessarily balanced.

• Apply the algorithm repeatedly to obtain a balanced bipartition.

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Network Flow Technique

• The network flow technique is very useful in different research areas.

• Many sophisticated improvements have been made to the original algorithm.

• Edmonds-Karp: O(|V||E|2)

• Ford & Fulkerson: O(|E||f|) where |f| is the size of the total flow. Note that for unit capacity, |f| |E|, so O(|E|2) time.

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Circuit Partitioning

• We can apply the network flow algorithm in partitioning circuits.

• The biggest problem is that the two partitions may not be balanced.

• The problem of obtaining two balanced partitions with minimum cut is NP-complete.

• However we can apply some heuristics to balance the two partitions.

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Flow-Balanced-Bipartition (FBB)

1 Find a min-cut C = (X,Y) in the network N.2 If (1-)W/2 w(X) (1+)W/2, stop and

return C.3 If w(X) < (1-)W/2 then

– Collapse all nodes in X to s.– Collapse to s a node vY incident on a net in C.– Goto to step 1.

4 If w(X) > (1+)W/2 … (similarly) ...

Why do we needthis step?

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Circuit Representation

Another problem in applying the network flow technique in circuit partitioning is how to represent a circuit correctly by a graph.

A B C D

How to represent this netlist by a simple graph?

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Hypergraph

A B C D

H(V,E) whereV = {A, B, C, D}E = {n1, n2, n3}n1 = {A, B, C, D}n2 = {A, B}n3 = {C, D}

In hypergraph, an edge is a set of vertices.

Circuits can be represented by hypergraphs, but the net-work flow method can only be used in simple graphs.

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Circuit Representation

Use a clique to model a net:

A B C D

What should be the edge weights?

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Circuit Representation

A B C D

1/4

1/4 1/4

1/41/41/4

1/2 1/2

Cut size = 4*1/4 = 1 (Actual cut size = 1)

Cut size = 3*1/4+1/2 = 5/4 (Actual cut size = 2)

edge weight =

n(k) = no. of cells in net k

)(

1

in

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Circuit Representation

A B C D

1/3

1/3 1/3

1/31/31/3

1 1

Cut size = 4*1/3 = 4/3 (Actual cut size = 1)

Cut size = 3*1/3+1 = 2 (Actual cut size = 2)

edge weight = 1)(

1in

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Circuit Representation

• It is proved that exact modeling of a hyper-graph by a graph with positive weights is impossible. [Ihler, Wagner & Wager, 1993]

• However, we can model a hypergraph H by a simple graph G such that when we apply the network flow algorithm, the min-cut in G is equal to the min-cut in H.

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Circuit Representation

A

B

C

A

B

C

1

What will happen when we apply the max-flow min-cutalgorithm to the graph G?

Original circuit C: G:

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Circuit Representation

A B C D

1

1

1

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Modeling a Circuit

d

ab

c

e

f

g

d

s

b

c

e

f

t

C: G:

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Modeling a Circuit

Lemma: If C has a cut (X,Y) of size K, G has a cut (X’,Y’) of size K. If G has a cut (X’,Y’) of size K, C has a cut (X,Y) of size less than or equal to K.

Corollary: If (X’,Y’) is the min-cut of G of size K, the corresponding cut (X,Y) in C is also a min-cut of C of size K.