CS141-L4-1Tarun Soni, Summer’03 Single Cycle CPU Previously: built and ALU. Today: Actually…

CS141-L4-1 Tarun Soni, Summer’03

Single Cycle CPU

Previously: built and ALU.Today: Actually build a CPU

Questions on CS140 ? Computer Arithmetic ?

•Attend office hours with TAs or me.•Do the exercises in the text.

Instruction Set Architectures Performance issues 2s complement, Addition, Subtraction Multiplication, Division, Floating Point numbers

The Story so far:

Basically ISA & ALU stuff

CPU: Building blocks

• Adder

• MUX

• ALU

Result

Select

CarryIn

Select

3232A[31..0]

B[31..0]32

Sum[31..0]

CarryIn

32A[63..32]

B[63..32]32

Sum[63..32]

CarryIn

• Building a 64-bit adder from 2x32-bit adders

Sum[63..32]32

Select

A[31..0]

B[31..0]32

Sum[31..0]

CarryIn

A[63..32]

B[63..32]32

A[63..32]

B[63..32]32

Cin=11

Select

• Silicon is cheap – sort-of

Single Cycle CPU

The Big Picture: Where are We Now?

• The Five Classic Components of a Computer

• Datapath Design, then Control Design

Control

Datapath

Memory

ProcessorInput

Output

CPU: The big picture

InstructionFetch

InstructionDecode

OperandFetch

Execute

ResultStore

NextInstruction ° Design hardware for each of these steps!!!

Execute anentire instruction

CPU: Clocking

Don’t CareSetup Hold

Setup Hold

• All storage elements are clocked by the same clock edge

The Big Picture: The Performance Perspective

• Execution Time = Insts * CPI * Cycle Time• Processor design (datapath and control) will determine:

– Clock cycle time– Clock cycles per instruction

• Starting today:– Single cycle processor:

• Advantage: One clock cycle per instruction• Disadvantage: long cycle time

• We're ready to look at an implementation of the MIPS• Simplified to contain only:

– memory-reference instructions: lw, sw – arithmetic-logical instructions: add, sub, and, or, slt– control flow instructions: beq

• Generic Implementation:– use the program counter (PC) to supply instruction address– get the instruction from memory– read registers– use the instruction to decide exactly what to do

• All instructions use the ALU after reading the registersmemory-reference? arithmetic? control flow?

Inst. Count Cycle Time

Review: The MIPS Instruction Formats

op target address02631

6 bits 26 bits

op rs rt rd shamt funct061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits

op rs rt immediate016212631

6 bits 16 bits5 bits5 bits

°The different fields are:•op: operation of the instruction•rs, rt, rd: the source and destination register specifiers•shamt: shift amount•funct: selects the variant of the operation in the “op” field•address / immediate: address offset or immediate value•target address: target address of the jump instruction

• R-type– add rd, rs, rt– sub, and, or, slt

• LOAD and STORE– lw rt, rs, imm16– sw rt, rs, imm16

• BRANCH:– beq rs, rt, imm16

op rs rt displacement016212631

• Memory– instruction & data

• Registers (32 x 32)– read RS– read RT– Write RT or RD

• PC• Extender• Add and Sub register or extended immediate• Add 4 or extended immediate to PC

Requirements to implement the ISA

• Combinational Elements• Storage Elements

– Clocking methodology

StateElement

C = f(A,B,state){State[n] = f(A,B,state[n-1])}

CombinationalLogic

BC = f(A,B)

CPU: Storage unit

• The set-reset latch– output depends on present inputs and also on past inputs

CPU: D-flip flop

• Two inputs:– the data value to be stored (D)– the clock signal (C) indicating when to read & store D

• Two outputs:– the value of the internal state (Q) and it's complement

• Output changes only on the clock edge

Dlatch

CPU: Clocking Methodology

• An edge triggered methodology• Typical execution:

– read contents of some state elements, – send values through some combinational logic– write results to one or more state elements

Clock cycle

Stateelement

1Combinational logic

Stateelement

CPU: Storage block

• Register– Similar to the D Flip Flop except

• N-bit input and output• Write Enable input

– Write Enable:• 0: Data Out will not change• 1: Data Out will become Data In (on the clock edge)

Data In

Write Enable

Data Out

CPU: Register Files

• Register File consists of (32) registers:– Two 32-bit output buses:– One 32-bit input bus: busW

• Register is selected by:– RA selects the register to put on busA– RB selects the register to put on busB– RW selects the register to be written

via busW when Write Enable is 1• Clock input (CLK)

• Factor only during write-enable=1;• Otherwise, this unit acts just like combinational logic.

Write Enable

32busB

5 5 5RW RA RB

32 32-bitRegisters

CPU: Register Files

Register 0Register 1

Register n – 1Register n

Read data 1

Read data 2

Read registernumber 1

Read registernumber 1 Read

data 1

Readdata 2

Register fileWriteregister

Writedata Write

n-to-1decoder

Register 0

Register 1

Register n – 1C

DRegister n

Register number

Register data

n – 1

Built using D-flip flopsStill use the real clock (not shown here) to do the actual write

CPU: Memory

• Memory (idealized)– One input bus: Data In– One output bus: Data Out

• Memory word is selected by:– Address selects the word to put on Data Out– Write Enable = 1: address selects the memory

word to be written via the Data In bus• Clock input (CLK)

– The CLK input is a factor ONLY during write operation– During read operation, behaves as a combinational logic block:

• Address valid => Data Out valid after “access time.”

Data In

Write Enable

32 32DataOut

Address

CPU: RTL

• is a mechanism for describing the movement and manipulation of data between storage elements:

R[3] <- R[5] + R[7]PC <- PC + 4 + R[5]R[rd] <- R[rs] + R[rt]R[rt] <- Mem[R[rs] + immed]

Register Transfer Language (RTL)

CPU: More building blocks

Instructionmemory

Instructionaddress

Instruction

a. Instruction memory b. Program counter

Add Sum

c. Adder

ALU control

RegWrite

RegistersWriteregister

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Writedata

ALUresult

Registernumbers

a. Registers b. ALU

16 32Sign

extend

b. Sign-extension unit

MemRead

MemWrite

Datamemory

Writedata

Readdata

a. Data memory unit

Address

CPU: The big picture

InstructionFetch

InstructionDecode

OperandFetch

Execute

ResultStore

NextInstruction ° Design hardware for each of these steps!!!

CPU: Instruction Fetch

• RTL version of the instruction fetch step: • Fetch the Instruction: mem[PC]– Update the program counter:

• Sequential Code: PC <- PC + 4 • Branch and Jump: PC <- “something else”

Instruction WordAddress

InstructionMemory

Next AddressLogic

CPU: Binary arithmetic for PC

• In theory, the PC is a 32-bit byte address into the instruction memory:– Sequential operation: PC<31:0> = PC<31:0> + 4– Branch operation: PC<31:0> = PC<31:0> + 4 + SignExt[Imm16] * 4

• The magic number “4” always comes up because:– The 32-bit PC is a byte address– And all our instructions are 4 bytes (32 bits) long

• In other words:– The 2 LSBs of the 32-bit PC are always zeros– There is no reason to have hardware to keep the 2 LSBs

• In practice, we can simplify the hardware by using a 30-bit PC<31:2>:– Sequential operation: PC<31:2> = PC<31:2> + 1– Branch operation: PC<31:2> = PC<31:2> + 1 + SignExt[Imm16]– In either case: Instruction Memory Address = PC<31:2> concat “00”

CPU: Instruction Fetch unit

• The common RTL operations– Fetch the Instruction: inst <- mem[PC]– Update the program counter:

• Sequential Code: PC <- PC + 4 • Branch and Jump PC <- “something else”

CPU: Register-Register Operations (Add, Subtract etc.)

• R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt– Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields– ALUctr and RegWr: control logic after decoding the instruction

32Result

ALUctr

32busB

Rw Ra Rb32 32-bitRegisters

Rs RtRd

° Worry about instruction decode to generate ALUctr and RegWr later.

CPU: Register - Register Timing

32Result

ALUctr

32busB

Rs RtRd

Rs, Rt, Rd,Op, Func

Clk-to-Q

ALUctr

Instruction Memory Access Time

Old Value New Value

RegWr Old Value New Value

Delay through Control Logic

busA, B

Register File Access TimeOld Value New Value

busWALU Delay

Old Value New Value

New ValueOld Value

Register WriteOccurs Here

CPU: Logical Immediate Op.• R[rt] <- R[rs] op ZeroExt[imm16] ]

Result

ALUctr

32busB

RtRdRegDst

ZeroExt

3216imm16

ALUSrc

6 bits 16 bits5 bits5 bits rd?

immediate016 1531

16 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Handle Rt as destination

HandleImmediate asoperand

CPU: Load Operations

• R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16

6 bits 16 bits5 bits5 bits rd

ALUctr

32busB

RtRdRegDst

Extender

ALUSrc

Data InWrEn

DataMemory

MemWr Mux

Need dataMemory!

Reg-Write could be from result or data memory

CPU: Store Operations

• Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16

ALUctr

32busB

RdRegDst

Extender

3216imm16

ALUSrcExtOp

Data InWrEn

DataMemory

W_SrcReg can

write to Data Memory

CPU: Branching

• beq rs, rt, imm16

– mem[PC] Fetch the instruction from memory

– Equal <- R[rs] == R[rt] Calculate the branch condition

– if (COND eq 0) Calculate the next instruction’s address• PC <- PC + 4 + ( SignExt(imm16) x 4 )

– else• PC <- PC + 4

CPU: Datapath for Branching

• beq rs, rt, imm16 Datapath generates condition (equal)

4nPC_sel

32busB

PC Ext

Inst Address

Calculate (PC+4) as well as (imm16+PC+4) and choose one

Calculate the “condition” part of the branch op.

CPU: The Aggregate Datapathim

ALUctr

32busB

RdRegDst

Extender

3216imm16

ALUSrcExtOp

MemtoReg

Data InWrEn32 Adr

DataMemory

MemWrA

Instruction<31:0>

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel

InstMemory

Still need to worry about Instruction Decode

CPU: Datapath: High-level view• Register file and ideal memory:

– The CLK input is a factor ONLY during write operation– During read operation, behave as combinational logic:

• Address valid => Output valid after “access time.”

Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew

Data In

DataAddress Ideal

DataMemory

Instruction

InstructionAddress

IdealInstruction

Memory

323232

CPU: Control Signals

ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal

Instruction<31:0>

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

InstMemory

DATA PATH

Control

<21:25>

CPU: Control Signals: Meaning

InstMemory

• Rs, Rt, Rd and Imed16 hardwired into datapath• nPC_sel: 0 => PC <– PC + 4; 1 => PC <– PC + 4 + SignExt(Im16) || 00

nPC_sel

PC Extim

CPU: Control Signals: Meaning• ExtOp: “zero”, “sign”• ALUsrc: 0 => regB; 1 =>

immed• ALUctr: “add”, “sub”, “or”

ALUctr

32busB

RdRegDst

Extender

3216imm16

ALUSrcExtOp

MemtoReg

Data InWrEn32 Adr

DataMemory

° MemWr: write memory° MemtoReg: 1 => Mem° RegDst: 0 => “rt”; 1 =>

“rd”° RegWr: write dest register

CPU: Control Signals for various operations

inst Register Transfer

ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4

ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”

SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4

ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”

ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4

ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”

LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4

ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”

STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4

ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”

BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4

nPC_sel = EQUAL, ALUctr = “sub”

CPU: Control Signals: Logic Design

• nPC_sel <= if (OP == BEQ) then EQUAL else 0• ALUsrc <= if (OP == “000000”) then “regB” else “immed”• ALUctr <= if (OP == “000000”) then funct

elseif (OP == ORi) then “OR”elseif (OP == BEQ) then “sub”

else “add”• ExtOp <= _____________• MemWr <= _____________• MemtoReg <= _____________• RegWr: <=_____________• RegDst: <= _____________

CPU: Control Signals: Logic Design

• nPC_sel <= if (OP == BEQ) then EQUAL else 0• ALUsrc <= if (OP == “000000”) then “regB” else “immed”• ALUctr <= if (OP == “000000”) then funct

elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add”

• ExtOp <= if (OP == ORi) then “zero” else “sign”• MemWr <= (OP == Store)• MemtoReg <= (OP == Load)• RegWr: <= if ((OP == Store) || (OP == BEQ)) then 0 else 1• RegDst: <= if ((OP == Load) || (OP == ORi)) then 0 else 1

CPU: Example: Load

ALUctr

32busB

RdRegDst

Extender

3216imm16

ALUSrcExtOp

MemtoReg

Data InWrEn32 Adr

DataMemory

MemWrA

LUEqual

Instruction<31:0>

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel

PC Ext

InstMemory

sign ext

addrt+4

R[rt] <- Mem[R[rs] + SignExt[imm16]]Viz., lw rt, rs, imm16

CPU: The abstract version

• Logical vs. Physical Structure

DataOut

Data In

DataAddress Ideal

DataMemory

Instruction

InstructionAddress

IdealInstruction

Memory

323232

Control

Datapath

Control Signals Conditions

CPU: The real thing

CPU: 5 steps to design

• 5 steps to design a processor– 1. Analyze instruction set => datapath requirements– 2. Select set of datapath components & establish clock methodology– 3. Assemble datapath meeting the requirements– 4. Analyze implementation of each instruction to determine setting of control points that

effects the register transfer.– 5. Assemble the control logic

• MIPS makes it easier– Instructions same size– Source registers always in same place– Immediates same size, location– Operations always on registers/immediates

• Single cycle datapath => CPI=1, CCT => long

CPU: Control Section

• The Five Classic Components of a Computer

Control

Datapath

Memory

ProcessorInput

Output

CPU: Add Instruction

• add rd, rs, rt

– mem[PC] Fetch the instruction from memory

– R[rd] <- R[rs] + R[rt] The actual operation

– PC <- PC + 4 Calculate the next instruction’s address

CPU: The Add Instruction

Instruction Fetch Unit at the Beginning of Add

• Fetch the instruction from Instruction memory: Instruction <- mem[PC]– This is the same for all instructions

InstMemory

nPC_sel

16Instruction<31:0>

The Single Cycle Datapath during Add

ALUctr = Add

RegWr = 1

32busB

RdRegDst = 1

Extender

3216imm16

ALUSrc = 0

MemtoReg = 0

Data InWrEn

DataMemory

MemWr = 0A

InstructionFetch Unit

Instruction<31:0>• R[rd] <- R[rs] + R[rt]

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel= +4

Instruction Fetch Unit at the End of Add

• PC <- PC + 4– This is the same for all instructions except: Branch and Jump

InstMemory

nPC_sel

16Instruction<31:0>

CPU: The Or Immediate Instruction

• R[rt] <- R[rs] or ZeroExt[Imm16]

ALUctr =

RegWr =

32busB

RdRegDst =

Extender

3216imm16

ALUSrc =

ExtOp =

MemtoReg =

Data InWrEn

DataMemory

MemWr = A

Instruction<31:0>

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel =

CPU: The Or Immediate Instruction

The Single Cycle Datapath during Or Immediate

ALUctr = Or

RegWr = 1

32busB

RdRegDst = 0

Extender

3216imm16

ALUSrc = 1

ExtOp = 0

MemtoReg = 0

Data InWrEn

DataMemory

MemWr = 0A

Instruction<31:0>

• R[rt] <- R[rs] or ZeroExt[Imm16]

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel= +4

CPU: The Load Instruction

The Single Cycle Datapath during Load

ALUctr = Add

RegWr = 1

32busB

RdRegDst = 0

Extender

3216imm16

ALUSrc = 1

ExtOp = 1

MemtoReg = 1

Data InWrEn

DataMemory

MemWr = 0A

Instruction<31:0>

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

• R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

nPC_sel= +4

CPU: The Store Instruction

The Single Cycle Datapath during Store• Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

ALUctr =

RegWr =

32busB

RdRegDst =

Extender

3216imm16

ALUSrc =

ExtOp =

MemtoReg =

Data InWrEn

DataMemory

MemWr = A

Instruction<31:0>

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel =

CPU: The Store Instruction

The Single Cycle Datapath during Store

ALUctr = Add

RegWr = 0

32busB

RdRegDst = x

Extender

3216imm16

ALUSrc = 1

ExtOp = 1

MemtoReg = x

Data InWrEn

DataMemory

MemWr = 1A

Instruction<31:0>

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

• Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

nPC_sel= +4

CPU: Datapath during branch

ALUctr = Subtract

RegWr = 0

32busB

RdRegDst = x

Extender

3216imm16

ALUSrc = 0

ExtOp = x

MemtoReg = x

Data InWrEn

DataMemory

MemWr = 0A

Instruction<31:0>

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

• if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

nPC_sel= “Br”

CPU: Datapath during branch

Instruction Fetch Unit at the End of Branch

• if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

InstMemory

nPC_sel

16Instruction<31:0>

CPU: Creating control from Datapath

ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

InstMemory

DATA PATH

Control

<21:25>

CPU: Control Signals

inst Register Transfer

ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4

ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”

SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4

ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”

ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4

ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”

LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4

ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”

STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4

ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”

BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4

nPC_sel = “Br”, ALUctr = “sub”

CPU: Summary of Control Signals

add sub ori lw sw beq jumpRegDstALUSrcMemtoRegRegWriteMemWritenPCselJumpExtOpALUctr<2:0>

1001000x

Subtract

01010000

01110001

x1x01001

x0x0010x

Subtract

xxx0001x

op target address

op rs rt immediate

R-type

I-type

J-type

add, sub

ori, lw, sw, beq

funcop 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010Appendix A

10 0000See 10 0010 We Don’t Care :-)

CPU: Summary of Control Signals

The Concept of Local Decoding

R-type ori lw sw beq jumpRegDstALUSrcMemtoRegRegWriteMemWriteBranchJumpExtOpALUop<N:0>

1001000x

“R-type”

01010000

01110001

x1x01001

x0x0010x

Subtract

xxx0001x

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

MainControl

ALUControl(Local)

6ALUop

ALUctr3

CPU: Encoding of ALUop

• In this exercise, ALUop has to be 2 bits wide to represent:– (1) “R-type” instructions– “I-type” instructions that require the ALU to perform:

• (2) Or, (3) Add, and (4) Subtract• To implement the full MIPS ISA, ALUop has to be 3 bits to represent:

– (1) “R-type” instructions– “I-type” instructions that require the ALU to perform:

• (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi)

MainControl

ALUControl(Local)

6ALUop

ALUctr3

R-type ori lw sw beq jumpALUop (Symbolic) “R-type” Or Add Add Subtract xxx

ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx

CPU: Decoding of the ‘func’ field

R-type ori lw sw beq jumpALUop (Symbolic) “R-type” Or Add Add Subtract xxx

ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx

MainControl

ALUControl(Local)

6ALUop

ALUctr3

R-type

funct<5:0> Instruction Operation10 000010 001010 010010 010110 1010

addsubtractandorset-on-less-than

ALUctr<2:0> ALU Operation000001010110111

AddSubtract

Set-on-less-than

Recall

ALUctr

CPU: Truth table for ALUctr

R-type ori lw sw beqALUop(Symbolic) “R-type” Or Add Add Subtract

ALUop<2:0> 1 00 0 10 0 00 0 00 0 01

ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>

0 0 0 x x x x

ALUctrALUOperation

Add 0 1 0bit<2> bit<1> bit<0>

0 x 1 x x x x Subtract 1 1 00 1 x x x x x Or 0 0 11 x x 0 0 0 0 Add 0 1 01 x x 0 0 1 0 Subtract 1 1 01 x x 0 1 0 0 And 0 0 01 x x 0 1 0 1 Or 0 0 11 x x 1 0 1 0 Set on < 1 1 1

funct<3:0> Instruction Op.00000010010001011010

addsubtractandorset-on-less-than

CPU: Logic Equation ALUctr[2]

The Logic Equation for ALUctr<2>

ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3> ALUctr<2>

0 x 1 x x x x 11 x x 0 0 1 0 11 x x 1 0 1 0 1

• ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0>

This makes func<3> a don’t care

ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3>

0 0 0 x x x x 1ALUctr<1>

0 x 1 x x x x 11 x x 0 0 0 0 11 x x 0 0 1 0 11 x x 1 0 1 0 1

• ALUctr<1> = !ALUop<2> & !ALUop<0> + ALUop<2> & !func<2> & !func<0>

ALUop funcbit<2> bit<1> bit<0> bit<2> bit<1> bit<0>bit<3> ALUctr<0>

0 1 x x x x x 11 x x 0 1 0 1 11 x x 1 0 1 0 1

• ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

CPU: ALU Control block

The ALU Control Block

ALUControl(Local)

6ALUop

ALUctr3

• ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0>

• ALUctr<1> = !ALUop<2> & !ALUop<0> + ALUop<2> & !func<2> & !func<0>

• ALUctr<0> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

CPU: Main Control

R-type ori lw sw beq jumpRegDstALUSrcMemtoRegRegWriteMemWriteBranchJumpExtOpALUop (Symbolic)

1001000x

“R-type”

01010000

01110001

x1x01001

x0x0010x

Subtract

xxx0001x

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

ALUop <2> 1 0 0 0 0 xALUop <1> 0 1 0 0 0 xALUop <0> 0 0 0 0 1 x

MainControl

ALUControl(Local)

ALUctr3

RegDstALUSrc

CPU: Main Control The “Truth Table” for RegWrite

R-type ori lw sw beq jumpRegWrite 1 1 1 0 0 0

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

• RegWrite = R-type + ori + lw= !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type) + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw)

op<5>. .op<5>. .

op<5>. .

R-type ori lw sw beq jumpRegWrite

CPU: Main Control PLA Implementation of the Main Control

op<5>. .op<5>. .

op<5>. .

R-type ori lw sw beq jumpRegWrite

ALUSrc

MemtoRegMemWrite

BranchJump

RegDst

ALUop<2>ALUop<1>ALUop<0>

CPU Putting it All Together: A Single Cycle Processor

ALUctr

32busB

RdRegDst

Extender

3216imm16

ALUSrc

MemtoReg

Data InWrEn

DataMemory

MemWrA

Instruction<31:0>

01<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

MainControl

ALUControlfunc

3ALUop

ALUctr3

RegDst

ALUSrc:

Instr<5:0>

Instr<31:26>

Instr<15:0>

nPC_sel

CPU Worst Case Timing (Load)

PCRs, Rt, Rd,Op, Func

Clk-to-Q

ALUctr

Instruction Memoey Access Time

Old Value New Value

Delay through Control Logic

busARegister File Access Time

Old Value New Value

busBALU Delay

Old Value New Value

New ValueOld Value

ExtOp Old Value New Value

ALUSrc Old Value New Value

MemtoReg

Old Value New Value

Address

Old Value New Value

busW Old Value New

Delay through Extender & Mux

RegisterWrite Occurs

Data Memory Access Time

CPU: Single Cycle Solution

• Long cycle time:– Cycle time must be long enough for the load instruction:

PC’s Clock -to-Q +Instruction Memory Access Time +Register File Access Time +ALU Delay (address calculation) +Data Memory Access Time +Register File Setup Time +Clock Skew

• Cycle time for load is much longer than needed for all other instructions

CPU: Single Cycle Solution

° Single cycle datapath => CPI=1, CCT => long

° 5 steps to design a processor• 1. Analyze instruction set => datapath requirements• 2. Select set of datapath components & establish clock methodology• 3. Assemble datapath meeting the requirements• 4. Analyze implementation of each instruction to determine setting of control points

that effects the register transfer.• 5. Assemble the control logic

° Control is the hard part

° MIPS makes control easier• Instructions same size• Source registers always in same place• Immediates same size, location• Operations always on registers/immediates

Control

Datapath

Memory

ProcessorInput

Output

CPU: Interrupts

° Datapath for interrupts

° Interrupt: basically hardware line requesting an immediate jump

° PC = Int[I] if Int[I] = 1;

° May or maynot save registers

° May or maynot be maskable.

° Useful for multitasking control & real-time processing

° Signal Processing

° Harder to implement in case of a multi-cycle/pipelines system !

CS141-L4-1Tarun Soni, Summer’03 Single Cycle CPU Previously: built and ALU. Today: Actually…

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