Computer Science 101

Computer Science Computer Science 101101

Computer SystemsComputer Systems

OrganizationOrganization

MEMORYMEMORY

Pappaw, our puter broke.Pappaw, our puter broke.

What’s a man to do?What’s a man to do?

Perfectly clear, huh?Perfectly clear, huh?

I think I’m getting a I think I’m getting a headache.headache.

Von Neumann Von Neumann ArchitectureArchitecture

Basic Architecture of most Basic Architecture of most computerscomputers

Four Major SubunitsFour Major Subunits• MemoryMemory• Input-outputInput-output• Arithmetic-logic unit (ALU)Arithmetic-logic unit (ALU)• Control UnitControl Unit

Stored ProgramsStored Programs

Von Neumann ArchitectureVon Neumann Architecture

Execution CycleExecution Cycle• Fetch InstructionFetch Instruction• DecodeDecode• ExecuteExecute

giga- G 1000^3 1024^3 = 2^30 = 1,073,741,824Hz- cycle per second

2.8 billion cycles per second2.8 billion cycles per second

HP Pavilion Media Center Processor speed: 2.8GHz

Major Major ComponentsComponents

Memory

CPU

ControlUnit

ALU

InputOutputUnits

Bus

HP Pavilion Media Center

Bus Speed: 800MHz Front Side Bus

MemoryMemory Stores: Numbers, text, programs, addresses, Stores: Numbers, text, programs, addresses,

graphics, sound, video, etc. that are currently graphics, sound, video, etc. that are currently in use.in use.

Divided into fixed size cells (fixed number of Divided into fixed size cells (fixed number of bits).bits).

This size is commonly 8 bits, and this 8-bit unit This size is commonly 8 bits, and this 8-bit unit is called a is called a bytebyte..

The simple hypothetical lab machine uses 16 The simple hypothetical lab machine uses 16 bit cells. The lab machine is a simulated version bit cells. The lab machine is a simulated version of a very simple, but illustrative computer.of a very simple, but illustrative computer.HP Pavilion Media Center

Memory: 1024MB PC2-4200 DDR2 SDRAM memory (expandable to

2GB)

A bit is what the dentist uses A bit is what the dentist uses to fix your byte?to fix your byte?

Memory AddressesMemory Addresses

Each cell has Each cell has an an addressaddress, an , an unsigned unsigned integer.integer.

All accesses to All accesses to memory are via memory are via a specific a specific addressaddress

Address Cell Content

0 00100110

10100110

00111110

10101010

1

2

3

Basic Memory OperationsBasic Memory Operations Memory FetchMemory Fetch

• Given a specific memory address.Given a specific memory address.• Retrieve the content stored at that address.Retrieve the content stored at that address.

Memory StoreMemory Store• Given a specific memory address andGiven a specific memory address and• a specific value,a specific value,• store the given value in the cell with the store the given value in the cell with the

specified address.specified address.

Memory FetchMemory Fetch

Address Cell Content

2002 00100110

10100110

00111110

10101010

2003

2004

2005

Given Address: 2004Content:

Memory FetchMemory Fetch

Address Cell Content

2002 00100110

10100110

00111110

10101010

2003

2004

2005

Given Address: 2004Content:

Memory FetchMemory Fetch

Address Cell Content

2002 00100110

10100110

00111110

10101010

2003

2004

2005

Given Address: 2004Content:

Memory FetchMemory Fetch

Address Cell Content

2002 00100110

10100110

00111110

10101010

2003

2004

2005

Given Address: 2004Content:

Memory FetchMemory Fetch

Address Cell Content

2002 00100110

10100110

00111110

10101010

2003

2004

2005

Given Address: 2004Content: 00111110

Memory StoreMemory Store

Address Cell Content

2002 00100110

10100110

00111110

10101010

2003

2004

2005

Given Address: 2004Given Value: 10101010

Memory StoreMemory Store

Address Cell Content

2002 00100110

10100110

00111110

10101010

2003

2004

2005

Given Address: 2004Given Value: 10101010

Memory StoreMemory Store

Address Cell Content

2002 00100110

10100110

00111110

10101010

2003

2004

2005

Given Address: 2004Given Value: 10101010

Memory StoreMemory Store

Address Cell Content

2002 00100110

10100110

00111110

10101010

2003

2004

2005

Given Address: 2004Given Value: 10101010

Memory StoreMemory Store

Address Cell Content

2002 00100110

10100110

10101010

10101010

2003

2004

2005

Given Address: 2004Given Value: 10101010

Memory Facts and Memory Facts and TerminologyTerminology

A cell is the minimum unit of access.A cell is the minimum unit of access.

Access time is same for all cells - Random Access time is same for all cells - Random Access Memory or RAM (nanoseconds - Access Memory or RAM (nanoseconds - billionths of second)billionths of second)

ROM - Read only Memory (fetch but not ROM - Read only Memory (fetch but not store)store)

Some data items require more than one Some data items require more than one cell. For example, an instruction might need cell. For example, an instruction might need four cells. Note: ints require 4 cells (bytes)four cells. Note: ints require 4 cells (bytes)

More on MemoryMore on Memory

All addresses are of some fixed number of All addresses are of some fixed number of bits, say N. Addresses would bebits, say N. Addresses would be

0000…0 0000…0 0 00000…1 0000…1 1 Total of 2 1 Total of 2NN cells cells

……1111…1 1111…1 2 2NN – 1 – 1

Note: This is an application of unsigned Note: This is an application of unsigned numbers.numbers.

TerminologyTerminology Storage capacity: Storage capacity:

• K K 2 21010 = 1024 = 1024 Kilo as in Kb Kilo as in Kb• M M 2 22020 = 1,048,576 = 1,048,576 Mega as in Mb Mega as in Mb• G G 2 23030 = 1,073,741,824 = 1,073,741,824 Giga as in Gb Giga as in Gb

SpeedSpeed• 1 1 = 1 microsecond = 1 millionth of second = 1 microsecond = 1 millionth of second• 1 ms = 1 millisecond = 1 thousandth of 1 ms = 1 millisecond = 1 thousandth of

secondsecond• 1 ns = 1 nanosecond = 1 billionth of second1 ns = 1 nanosecond = 1 billionth of second

Cycle rate: Hertz is cycle per secondCycle rate: Hertz is cycle per second

Memory RegistersMemory Registers A A registerregister is an extremely fast cell - more is an extremely fast cell - more

expensive than RAM cells - fewer of them - expensive than RAM cells - fewer of them - for special purposes.for special purposes.

MAR - Memory Address RegisterMAR - Memory Address Register - size is - size is same as size of an address - holds the same as size of an address - holds the address of the cell to access.address of the cell to access.

MDR - Memory Data RegisterMDR - Memory Data Register - size is - size is multiple of RAM cell size - holds content of multiple of RAM cell size - holds content of cell fetched or value to be stored.cell fetched or value to be stored.

MAR of size N bits gives 2MAR of size N bits gives 2NN possible possible addresses; so up to 2addresses; so up to 2NN possible possible memory locations.memory locations.

This HP has maximum memory of This HP has maximum memory of 2GB or 22GB or 23131; so MAR must be 31 bits.; so MAR must be 31 bits.

HP Pavilion Media CenterMemory: 1024MB PC2-4200 DDR2 SDRAM

memory (expandable to 2GB)

MAR and Max Memory SizeMAR and Max Memory Size

Memory Fetch- More DetailMemory Fetch- More Detail

Fetch (address)Fetch (address) To obtain data at a given address: To obtain data at a given address:

• Load address into MARLoad address into MAR

• Address is decoded and cell is selectedAddress is decoded and cell is selected

• Contents of cell put into MDRContents of cell put into MDR

Fetch(10110)Fetch(10110)

Address Cell Content

10100 00100110

10100110

00111110

10101010

10101

10111

MAR 10110

MDR 0011110

10110

Memory Store- More DetailMemory Store- More Detail Store (address,value)Store (address,value)

To store a given value at a given To store a given value at a given address:address:

• Load address into MARLoad address into MAR

• Load value into MDRLoad value into MDR

• Address is decoded and cell is selectedAddress is decoded and cell is selected

• Value from MDR is put into the selected cellValue from MDR is put into the selected cell

Store(10110,11111111)Store(10110,11111111)

Address Cell Content

10100 00100110

10100110

00111110

10101010

10101

10111

MAR 10110

MDR 11111111

10110 11111111

Address DecodingAddress Decoding Recall: Decoder has n inputs, 2Recall: Decoder has n inputs, 2nn outputs, outputs,

inputs select one output to be 1, others 0.inputs select one output to be 1, others 0.

MAR

---n---

n to

2n

decoder

00100110

10100110

00111110

10101010

00100110

10100110

00111110

10101010

2n lines

Address decoding (cont.)Address decoding (cont.)

Note: If we have 26 bit addresses, Note: If we have 26 bit addresses, this allows for 2this allows for 22626 = 64M cells. = 64M cells.

In the diagram before, the decoder In the diagram before, the decoder would have 26 input lines and would have 26 input lines and 67,108,864 output lines.67,108,864 output lines.

That’s a lot of lines.That’s a lot of lines.

Two-dimensional memory Two-dimensional memory layoutlayout

Now picture the 64M memory laid out as a Now picture the 64M memory laid out as a 2-dimensional grid. There would be 22-dimensional grid. There would be 21313 rows and 2rows and 21313 columns. columns.

Suppose we use half of the address (13 Suppose we use half of the address (13 bits) to choose a row and half to choose bits) to choose a row and half to choose the column in order to locate the cell.the column in order to locate the cell.

This would use two decoders - one for the This would use two decoders - one for the row and one for the column.row and one for the column.

Two-dimensional Memory Two-dimensional Memory LayoutLayout

Here we have 2* Here we have 2* 221313= 16384 lines as = 16384 lines as opposed to opposed to 67,108,864 as in 1-dimensional67,108,864 as in 1-dimensional

MAR 13 13

n to

213

n to

213