Computer Organization Lecture 10

Fall 2006

Lillevik 333f06-l10 1University of Portland School of Engineering

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Computer OrganizationLecture 10

Exam 1 resultsProject 3: program counter

R-type control

Fall 2006

Lillevik 333f06-l10 2University of Portland School of Engineering

EE 333

Exam 1Prob Std Ave

1/10 1.2 9.3

2/10 1.7 8.0

3/10 2.6 8.8

4/10 1.9 8.8

5/10 2.1 8.1

6/10 0.4 9.9

7/10 2.1 7.6

8/10 3.2 8.3

9/10 2.9 5.3

10/10 2.6 7.1

Ave 13.8 81.2

Fall 2006

Lillevik 333f06-l10 3University of Portland School of Engineering

EE 333

Problem 10

Reset asynchronous to clock and overrides it Flip-flops only change on rising edge of clockData at D input transferred to FF each clock

Fall 2006

Lillevik 333f06-l10 4University of Portland School of Engineering

EE 333

Problem 10 solution

• Sin always H• Q3 input always H• Q2 input = Q3• Q1 input L when (Sin and Q3) both H• Q0 input H when (Q2 and Q3) both L

Fall 2006

Lillevik 333f06-l10 5University of Portland School of Engineering

EE 333

Problem 10 state tablePresent State Next State

0000 11111111 10001000 10011001 1001

Fall 2006

Lillevik 333f06-l10 6University of Portland School of Engineering

EE 333

Project 3 overview

Design a 16-bit, writable program counter

Input FunctionReset Forces the output to all zeros

CLK Synchronous clock for entire MDP16 design

PCin Port with 16-bit number to load into counter

PCinc Causes the circuit to count at next rising edge of CLK

PCwr Causes the number at PCin to be written into the circuit on the next rising edge of CLK

Fall 2006

Lillevik 333f06-l10 7University of Portland School of Engineering

EE 333

Project 3 block diagram

ResetClockPCincPCwr

PCin PC

Fall 2006

Lillevik 333f06-l10 8University of Portland School of Engineering

EE 333

Datapath and controller

Controller Input

ck1

ck2

ck3

ck4

ck5

Fall 2006

Lillevik 333f06-l10 9University of Portland School of Engineering

EE 333

Datapath timingInstruction fetch

Instruction decode, register read

Execution

Memory access

Register write

1 2 3 4 5

Timing similar to shift register

Fall 2006

Lillevik 333f06-l10 10University of Portland School of Engineering

EE 333

Instruction fetch

• Operations– IR = memory[PC]– PC = PC + 4

• Functional units– PC addresses memory– Memory read, then written to IR– PC address sent to ALU and incremented by 4– PC+4 written (unconditional)

Clock 1

Fall 2006

Lillevik 333f06-l10 11University of Portland School of Engineering

EE 333

Determine control for IF Clock 1

00

Fall 2006

Lillevik 333f06-l10 12University of Portland School of Engineering

EE 333

Inst decode & reg read• Operations

– A = Reg [IR(25-21)]– B = Reg [IR(20-16)]– ALUout = PC + (sign-extend( IR(15-0))<<2)

• Functional units– Reg file read and clocked into A, B– ALU determines branch address, ALUout clocked

Clock 2

Fall 2006

Lillevik 333f06-l10 13University of Portland School of Engineering

EE 333

Determine control for ID Clock 2

00

Optimistic branch address

Fall 2006

Lillevik 333f06-l10 14University of Portland School of Engineering

EE 333

Execution

Opcode determines instruction type– R-Type

ALUout = A funct B– Memory reference

ALUout = A + sign-extend (IR[15-0])– Branch

If (A == B), PC = ALUout – Jump

PC = PC[31-18] || (IR[25-0]<<2)

Clock 3

Fall 2006

Lillevik 333f06-l10 15University of Portland School of Engineering

EE 333

Control for R-type EX? Clock 3

Fall 2006

Lillevik 333f06-l10 16University of Portland School of Engineering

EE 333

R-type register write

• Operation– Reg [ IR(15-11)] = ALUout

• Functional units– ALUout contains result data– Data written to Reg file

Clock 4

We often call this write-back or WB

Fall 2006

Lillevik 333f06-l10 17University of Portland School of Engineering

EE 333

Control for R-type WB? Clock 4

Fall 2006

Lillevik 333f06-l10 18University of Portland School of Engineering

EE 333

Complete R-type

001000

Fall 2006

Lillevik 333f06-l10 19University of Portland School of Engineering

EE 333

R-type instruction timing

Inst

ruct

ion

Fetc

h

Dec

ode,

Reg

Rea

d

Func

tion

Reg

iste

r Writ

e

Clock

Inst

ruct

ion

Fetc

h

Fall 2006

Lillevik 333f06-l10 20University of Portland School of Engineering

EE 333

Fall 2006

Lillevik 333f06-l10 21University of Portland School of Engineering

EE 333

Control for R-type EX? Clock 3

10

Fall 2006

Lillevik 333f06-l10 22University of Portland School of Engineering

EE 333

Control for R-type WB? Clock 4