Computer Architecture (CS-213) · Computer Architecture (CS-213) Main Objectives • Introduction...

Computer Architecture (CS-213)

Main Objectives

• Introduction to MIPS Architecture • MIPS Architecture Based Single Cycle

Processor • Datapath Design • Control Unit Design

Revision

• Remember these Names ? • Register File • ALU • Instruction Memory • Data Memory • Program Counter • Instruction Set Architecture (ISA)

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Design of Processor

1. Analyze the instruction set architecture 2. Select the datapath elements each

instruction needs 3. Assemble the datapath 4. determine the controls required 5. Assemble the control logic

5

A Basic MIPS Implementation

• MIPS 32-bit architecture has 32-bit instruction size and 32-bit data bus width.

• We will implement the following subset of MIPS core instructions – lw, sw – add, sub, and, or, slt – beq, j

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A Basic MIPS Implementation Instruction Function Description

lw Load Word Similar to LD (load). It copies data from memory and loads into a register.

sw Store Similar to ST (store). It copies data from a register into a memory location

add Add Adds Two Registers and Stores the result in third.

sub Subtract Subtracts Two Registers and Stores the result in third.

and AND ANDs Two Registers and Stores the result in third.

slt Set Less Than Similar to CMP (compare) , Compares to see if one register is less than the other and Stores the value 1 in third if true and 0 if false.

beq Branch Equal Similar to BEQ, compares to register if the result is equal, than it branches the PC to new address calculated by adding a register and offset address

j Jump Makes the PC Jump unconditionally to new value.

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Registers in MIPS

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Instruction Formats • R-Type Instruction Fromat(add,sub,or)

• Branch Type and Memory Format(beq,lw,sw)

Write reg./ Read reg. B

Opcode RS RT Immediate Data

31-26 25-21 20-16 15-0

To ctrl logic

Read reg. A

Memory address or Branch Offset

Opcode RS RT RD ShAmt Function 31-26 25-21 20-16 15-11 10-6 5-0

To ctrl logic

Read reg. A

Read reg. B

Write reg.

To ALU Control

Not Used

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Steps in executing add instruction

add $t0, $t1, $t2 • Send PC to memory that contains the code

and fetch instruction • PC = PC+4 • Read $t1 and $t2 from register file • Perform $t1 + $t2 • Store result in $t0

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Steps in executing lw instruction

lw $t0, offset($t1) • Send PC to memory that contains the code and

fetch instruction • PC = PC+4 • Read $t1 from register file • Perform $t1 + sign-extend(offset) • Read value at Mem[$t1 + sign-extend(offset)] • Store result in $t0

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Steps in executing lw instruction

sw $t0, offset($t1) • Send PC to memory that contains the code and

fetch instruction • PC = PC+4 • Read $t1 from register file • Perform $t1 + sign-extend(offset) • Store contents of $t0 at Mem[$t1 + sign-

extend(offset)]

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Steps in executing beq instruction

beq $t0, $t1, Label • Send PC to memory that contains the code

and fetch instruction • PC = PC+4 • Read $t0 and $t1 from register file • Perform $t0 - $t1 • If result = 0, set PC=Label

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Steps in implementing these instructions

• Common steps – Send PC to memory that contains the code and fetch the instruction – Set PC = PC+4 – Read one or two registers

• Steps dependent on instruction class – Use ALU

• Arithmetic/logical instr for operation execution • lw/sw for address calculation • beq for comparison

– Update memory or registers • lw/sw read or write to memory • Arithmetic/logical instr write to register • beq updates PC

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Components needed for Fetching and Incrementing PC

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Datapath for Fetching and Incrementing PC

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Components needed for R-format Instructions

add $t0, $t1, $t2: $t0= $t1 + $t2

and $t0, $t1, $t2: $t0= $t1 AND $t2

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Register File • Consists of a set of 32 registers

that can be read and written • has two read ports and one

write port • Register number are 5 bit long • To write, you need three

inputs: – a register number, the data to

write, and a clock (not shown explicitly) that controls the writing into the register

– The register content will change on clock edge

5

5

5

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Portion of datapath for R-format instruction

4

31-26 25-21 20-16 15-11 10-6 5-0 opcode rs rt rd shamt funct

R-format

rs

rt

rd

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Components needed for load and store instructions

lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]

sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0

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Memory Unit

• MemRead to be asserted to read

• MemWrite to be asserted to write

• Both MemRead and MemWrite not to be asserted in same clock cycle

• Memory is edge triggered for writes

MemRead

MemWrite

Address

Write Data

ReadData

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Load/Store instruction Datapath

4

lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]

sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0

31-26 25-21 20-16 15-0 opcode rs rt offset

I-format

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Load instruction datapath

4

lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]

31-26 25-21 20-16 15-0 opcode rs rt offset

I-format

rs

rt

offset

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Store instruction datapath

4

sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0

31-26 25-21 20-16 15-0 opcode rs rt offset

I-format

rs

rt

offset

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Branch Instruction Datapath

31-26 25-21 20-16 15-0 opcode rs rt C

If ($rs-$rt)=0, PC=PC+4+(C.4)

rs

rt

C

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Creating a single Datapath

Simplest Design: Single Cycle Implementation • Any instruction takes one clock cycle to execute

– This means no datapath elements can be used more than once per instruction

– But datapath elements can be shared by different instruction flows

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4

27

Composite Datapath for R-format and load/store instructions

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Composite Datapath for R-format and load/store instructions

P

C

Instruction Memory

4 +

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Composite datapath for R-format, load/store, and branch instructions

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Composite datapath for R-format, load/store, and branch instructions

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Datapath for for R-format, load/store, and branch instructions

4

ALU Operation

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Instruction RegDst RegWrite ALUSrc MemRead MemWrite MemToReg PCSrc ALU operation

R-format 1 1 0 0 0 0 0 0000(and) 0001(or) 0010(add) 0110(sub)

lw 0 1 1 1 0 1 0 0010 (add)

sw X 0 1 0 1 X 0 0010 (add)

beq x 0 0 0 0 X 1 or 0 0110 (sub)

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Control

• We next add the control unit that generates – write signal for each state element – control signals for each multiplexer – ALU control signal

• Input to control unit: instruction opcode and function code

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Control Unit

• Divided into two parts – Main Control Unit

• Input: 6-bit opcode • Output: all control signals for Muxes, RegWrite,

MemRead, MemWrite and a 2-bit ALUOp signal

– ALU Control Unit • Input: 2-bit ALUOp signal generated from Main Control

Unit and 6-bit instruction function code • Output: 4-bit ALU control signal

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What do we need to control?

Instruction Memory

Data Memory

Add Add

4

Read address Instruction [31-0]

Read address

Write address

Write data

Read data Result

Zero

Result

Result Sh. Left

2

0

1

1

0 0

1

sign extend

PC

16 32

ALU - What is the Operation?

Memory- Read/Write/neither?

Mux - are we branching or not?

Mux - Where does 2nd ALU operand come from?

Registers- Should we write data? Mux - Result from

ALU or Memory?

Almost all of the information we need is in the instruction!

Read reg. num A

Registers Read reg num B

Write reg num

Write reg data

Read reg data A

Read reg data B

Read reg num A

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Control Signals

1. RegDst = 0 => Register destination number for the Write register comes from the rt field (bits 20-16) RegDst = 1 => Register destination number for the Write register comes from the rd field (bits 15-11) 2. RegWrite = 1 => The register on the Write register input is written with the data on the Write data input (at the next clock edge) 3. ALUSrc = 0 => The second ALU operand comes from Read data 2 ALUSrc = 1 => The second ALU operand comes from the signextension unit 4. PCSrc = 0 => The PC is replaced with PC+4 PCSrc = 1 => The PC is replaced with the branch target address 5. MemtoReg = 0 => The value fed to the register write data input comes from the ALU MemtoReg = 1 => The value fed to the register write data input comes from the data memory 6. MemRead = 1 => Read data memory 7. MemWrite = 1 => Write data memory

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38

Truth Table for Main Control Unit

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Main Control Unit

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ALU Control Unit

• Must describe hardware to compute 4-bit ALU control input given – 2-bit ALUOp signal from Main Control Unit – function code for arithmetic

• Describe it using a truth table (can turn into gates):

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ALU Control bits

0010

0010

0110

0010

0110

0000

0001

0111