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Introducción a VLSI

EAMTA 2006

Introducción a VLSI

Clase 4: Lógica Secuencial y Subsistemas

3Escuela Argentina de Microelectrónica , Tecnología y Aplicaciones

Programa

El Transistor MOSLayers y LayoutLógica CombinacionalLógica Secuencial y Subsistemas

Organización

Lógica secuencialSumadoresOtros subsistemasMemorias

Sequential Logic Circuits

Sequential Logic

2 storage mechanisms• positive feedback• charge-based

COMBINATIONALLOGIC

Registers

Outputs

Next state

Current State

Inputs

Naming Conventions

In our text:a latch is level sensitivea register is edge-triggered

There are many different naming conventionsFor instance, many books call edge-triggered elements flip-flopsThis leads to confusion however

Timing Definitions

tc 2 q

tsetup

Q DATASTABLE

DATASTABLE

Register

Characterizing Timing

Register Latch

tC 2 Q

tD 2 Q

Maximum Clock Frequency

FF’s

tp,comb

Also:tcdreg + tcdlogic > thold

tcd: contamination delay = minimum delay

Data is hold long enough so it can be output

tclk-Q + tp,comb + tsetup = T

Latch versus Register

Latchstores data when clock is low

Registerstores data when clock rises

Clk Clk

Latches

Positive Latch

Outstable

Outfollows In

Negative Latch

Outstable

Outfollows In

“transparent” “transparent”

Positive Latch

Outstable

Outfollows In

Negative Latch

Outstable

Outfollows In

Storage Mechanisms

Dynamic (charge-based)Static

Race might occur with a Race might occur with a mastermaster--slave slave

Mux-Based Latches

Negative latch(transparent when CLK= 0) Positive latch

(transparent when CLK= 1)

InClkQClkQ ⋅+⋅= InClkQClkQ ⋅+⋅=

Mux-Based Latch

Number of transistor that the clock has to drive is an important metric.

In this case, there are 4 (four) transistors in the CLK line

Mux-based latch

3-state

Mux-based latch

Mux-Based Latch

NMOS only Non-overlapping clocks

Simple but degrades a High input to Vdd-Vtn

Master-Slave (Edge-Triggered) Register

Two opposite latches trigger on edge. Also called master-slave latch pair This is a positive edge-triggered Reg. A negative edge-triggered can be realized by switching registers.

Master-Slave Register

Multiplexer-based latch pair

I 3 T4I 5

DFF PC

Avoiding Clock Overlap

(a) Schematic diagram

(b) Overlapping clock pairs

CLKCLK and CLKB are 1 at the same time, then D passes directly to output (race)

Output can change in the rising edge of the CLK for a negative edge-triggered FF

Non-overlapping Clocks

(a) Schematic diagram

(b) Non-Overlapping clock pairs

CLK1CLK1 and CLK2 are non-overlapping

T non-overlap has to be small enough so that the charge in the intermmediate nodes is preserved (gates are in tri-state)

T non-overlap

Overpowering the Feedback Loop ─Cross-Coupled Pairs

NOR-based set-reset

Forbidden State

010 1011 0

Clocked SR Added clock

This is not used in datapaths any more, but is a basic building memory cellTransistors M5-M6 (M7-M8) has to be sized to overpower M2 (M4) and pull that node down

M8 CLK

Sizing Issues

Output voltage dependenceon transistor width

Transient response

4.03.53.0W/L5 and 6

2.52.00.0

Q (Volts)

time (ns)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

W = 1 mµ

W = 0.9 mµW = 0.8 mµ

W = 0.7 mµW = 0.6 mµ

W = 0.5 mµ

Other Latches/Registers: C2MOS

“Keepers” can be added to make circuit pseudo-static

Master Stage

CLK M8

Slave Stage

Insensitive to Clock-Overlap

(a) (0-0) overlap

(b) (1-1) overlap

Insensitive as long as the rise and fall times are sufficiently small

Hold time must be imposed

Adders

Important subsystem in digital design, so we care about performanceGood example of ways to think about building systems larger than 1-2 gatesBasic problem: Bit N of the result depends on 0 - (N-1) input bits.

Could build separate circuits to compute partial sumsFast but very Big

Use bit adders that compute the value of each bit and connect them together to form N-bit adders

Half adders

Full adders

Multi-Bit adders

Gate level implementation

Better full adder (Mirror adder)

Bit slice layout

Multi-bit adders can be obtained by repeating automatically the cell

Bit-slice Full Adder

Eight-bit Adder

Serial Adder

Datapath organization

Substraction

Otros Subsistemas

Comparison

Want to compare two numbers, A and BIf A=B, A-B=0If B>=A, A-B will generate a carry out in the last bit (overflow)Comparison can be implemented using a substractor

Parity

Crossbar as shifter

Counters

RULE # 1 of making a digital system work right: never gate clock signal !!

Counter

Adder with a constant inputSelection used to define up (sum) or down (substraction)Synchronous – all signals change with clock

Multiplication

Parallel Multiplication

Serial-Parallel multiplier

Requires M+N clock cycles

Pipeline technique

Reference Pipelined

Pipelined Serial to Parallel

Memories

Organization

Static row decoder

Row decoder

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