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Fundamentals of Microelectronics Jintae Kim
1
Chapter 6: Physics of MOS Transistor
□ MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor
- A dominant type of transistor in modern integrated circuit (IC) for consumer products Ex) Memory (Flash, DRAM), CPU, Image Sensor, Wireless LAN transceiver, Bluetooth transceiver, etc are all designed using MOSFETs - We learned BJT first, but why is MOSFET so much more popular than BJT?
• 1) Technology Scaling: The size of transistor has been getting smaller and smaller by innovations in transistor technology over the last 40 years Called “Moore’s law”
10nm x 10nm
Size of Transistor
2017Year 1993
Transistor Size 600nm x 600nm
~3600x smaller
2) The cost of single MOSFET has been dropping continuously
Fundamentals of Microelectronics Jintae Kim
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3) Can be used for both analog and digital circuits can build an integrated system on a single silicon die
Digital
Analog
4mm
Example) 801.11 Wifi Chip Die Photograph
□ MOS Capacitor
- Review of Parallel Plate Capacitor: Q=CV, C = ϵ𝐴
𝑑
+V
+++
++
+ + ++
+
++
d
Area: A=WL
Fundamentals of Microelectronics Jintae Kim
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- MOS capacitor
````
Metal or Conductor
Insulator
Semiconductor
(P-type for now)
1) What happens when V1 > 0?
- Top Plate:
- Bottom-Plate:
2) With V1 > 0 , what happens if we apply V2?
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□ MOSFET
i) MOSFET is a 3-terminal device
Gate: Oxide: Drain & Source:
ii) MOSFET is built on “silicon substrate”
iii) There are two types of MOSFETS: NMOS and PMOS
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□ Formation of Channel in MOSFET and Threshold Voltage
1) Scenario 1: When VGS = 0
2) Scenario 2: When VGS > 0 Holes near the oxide-substrate interface are repelled 3) Scenario 3: When VGS >> 0
Minority carrier is pulled toward the interface
D
G
p-substrate
n+ n+
S
Fundamentals of Microelectronics Jintae Kim
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4) With VGS > VTH, let’s apply VDS > 0
- Let’s plot ID versus VDS
Observation: The MOSFET is similar to “voltage-controlled resistor”
- Let’s plot Id versus VGS
D
G
p-substrate
n+ n+
S
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□ Channel Pinchoff
D
G
p-substrate
n+ n+
S
x0 L
- Channel Potential V(x): potential along the channel from 0 to x V(0) = 0, V(L) = VDS
- Voltage difference between gate and channel at x = VGS – V(X)
- What happens if At x=0, VGS-V(0) > VTH Channel exists near the source AT x=L, VGS-V(L) <VTH Channel doesn’t exist near the drain Called “Channel Pinchoff”
- How does current flow when there is channel pinchoff?
D
G
p-substrate
n+ n+
S
- Electrons reaching at the end of the channel is pulled toward the drain by the electric field in the depletion region
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□ Derivation of MOSFET current 1) When there is no pinchoff
i) Gate capacitance per unit area: Cox
ii) Channel Charge per unit length: Qch(x) At x=0 At arbitrary x, iii) Drain Current : ID iv) Finding closed form of ID by using boundary condition
GS D
WL
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Note: This equation is valid only when Q(x)>0 for all x from 0 to L (No pinchoff)
At x=0: At x=L: - When is the ID at its maximum?
- Special Case when VDS << VGS-VTH
VDS
ID
VGS-VTH
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2) Drain current when there is channel pinchoff: “Square-Law”
Note: With pinchoff, Q(x) = WCOX[VGS-VTH-V(X)] is not valid where there is no channel Modified ID is found by performing the integration only for Q(x)>0
D
G
p-substrate
n+ n+
S
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- Combined Drain Current Model: Square-Law & Mode of Operation
BJT MOSFET
Main Mode (Voltage-Controlled
Current Source)
Condition
Current
Mid-Terminal
Integrated Circuit Design
VDS
ID
VGS-VTH
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□ MOSFET Nonideality: Channel-Length Modulation - Just like Early effect in BJT, people experimentally found out that ID actually
depends on VDS called “Channel Length Modulation”
D
G
p-substrate
n+ n+
S
DG
p-substrate
n+ n+
S
L1
L2
v) Drain Current with Channel Length Modulation
VDS
ID
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□ MOSFET Small-Signal Model
VGS-VTH
gm
W/L 2x, ID 2x
W/L 2x, ID 1x
W/L 1x, ID 2x
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□ PMOS Transistor
NMOS PMOS
Gate
Source/Drain
Substrate (Body)
Channel Carrier
Channel Turn-On
Saturation condition
- CMOS Process
D
G
N-substrate
P+ P+
S
L1
D
G
N-Well
P+ P+
SD
G
p-substrate
n+ n+
S
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