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8/11/2019 Chapter 2 Op-Amp
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Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.
Figure 2.1 Circuit symbolfor the op amp.
The Op-amp
Figure 2.2 The op amp shownconnected to dc power supplies.
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The Ideal Op-amp
1. Infinite input impedance
2. Zero output impedance
3. Zero common-mode gain
(i.e., infinite common-mode
rejection
4. Infinite loop-gain A
5. Infinite bandwidth
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Differential and Common-mode signals
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Model of internal of an op-amp by circuit
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The inverting closed-loop configuration.
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicatethe order of the analysis steps.
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Figure 2.7 Analysis of the inverting configuration taking intoaccount the finite open-loop gain of the op amp.
Inverting Configuration, taking gain A into account
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Example 2.2. The circled numbers indicate the sequence of thesteps in the analysis.
)1(3
4
2
4
1
2
RR
RR
RR
vvI
O++=
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A weighted summer.
A weighted summer capable of implementing summing coefficients of both signs.
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Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.Figure 2.13 Analysis of the noninverting circuit. The sequence of the steps in theanalysis is indicated by the circled numbers.
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Non-Inverting Configuration
1. Effect of finite loop gain
2. Input/output impedance- Infinite input- Zero output
3. Voltage follower
AR
R
R
R
V
VG
i )(1
1
)(1
1
2
1
2
0
+
+
+
=
100
)(1
)(1
__%
1
2
1
2
x
R
R
A
R
R
errorgain
++
+
=
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Figure 2.15 Representing theinput signals to a differential
amplifier in terms of their
differential and common-mode components.
Difference Amplifiers
2
1
2
1
2
43
422 )1( IIO v
R
R
R
R
RR
Rvv =+
+
=
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Figure 2.20 A popular circuit for an instrumentation amplifier. (a) Initial approach to thecircuit (b) The circuit in (a) with the connection between node X and ground removedand the two resistors R1 and R1 lumped together. This simple wiring change
dramatically improves performance. (c) Analysis of the circuit in (b) assuming ideal opamps.
Instrumentation Amplifier
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Figure 2.22 The inverting configuration with general impedances in the feedback
and the feed-in paths.
Integrators Differentiator
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Figure 2.28 Circuit model for an op amp with input offset voltageVOS.
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Figure E2.21 Transfer characteristic of an op amp with VOS= 5 mV.
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Figure 2.29 Evaluating the output dc offset voltage due to VOS in a closed-loop amplifier.
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Figure 2.30 The output dc offset voltage of an op amp can be trimmed to zero by connecting a potentiometer to thetwo offset-nulling terminals. The wiper of the potentiometer is connected to the negative supply of the op amp.
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Figure 2.31 (a) A capacitively coupled inverting amplifier. (b) The equivalent circuit for determining its dc output offset voltageVO.
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Figure 2.32 The op-amp input bias currents represented by two current sources IB1 and IB2.
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Figure 2.33 Analysis of the closed-loop amplifier, taking into account the input bias currents.
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Figure 2.34 Reducing the effect of the input bias currents by introducing a resistor R3.
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Figure 2.35 In an ac-coupled amplifier the dc resistance seen by the inverting terminal is R2; hence R3 is chosen equal to R2.
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Figure 2.36 Illustrating the need for a continuous dc path for each of the op-amp input terminals. Specifically, notethat the amplifier will notwork without resistor R3.
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Figure 2.37 Determining the effect of the op-amp input offset voltageVOSon the Miller integrator circuit.Note that since the output rises with time, the op amp eventually saturates.
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Figure 2.38 Effect of the op-amp input bias and offset currents on the performance of the Mil ler integrator circuit.
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Figure 2.39 Open-loop gain of a typical general-purpose internally compensated op amp.
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Figure 2.40 Frequency response of an amplifier with a nominal gain of +10 V/V.
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Figure 2.41 Frequency response of an amplifier with a nominal gain of 10 V/V.
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Figure 2.42 (a) A noninverting amplifier with a nominal gain of 10 V/V designed using an op amp that saturates at13-V output voltage and has 20-mA output current limits.
(b) When the input sine wave has a peak of 1.5 V, the output is clipped off at 13 V.
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Figure 2.44 Effect of slew-rate limiting on output sinusoidal waveforms.
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Figure P2.2
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Figure P2.8
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Figure P2.16
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Figure P2.22
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Figure P2.25
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Figure P2.30
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Figure P2.31
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Figure P2.32
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Figure P2.34
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Figure P2.43
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Figure P2.46
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Figure P2.50
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Figure P2.51
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Figure P2.59
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Figure P2.62
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Figure P2.68
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Figure P2.70
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Figure P2.71
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Figure P2.77
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Figure P2.78
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Figure P2.84
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Figure P2.85
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Figure P2.89
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Figure P2.92
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Figure P2.93
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Figure P2.102
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