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7/29/2019 CH04 Fabrication of CMOS Integrated Circuits
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FABRICATION OF CMOSINTEGRATED CIRCUITS
Mohammed Morsy
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Faculty of Engineering - Alexandria University 2013aculty of Engineering - Alexandria University 2013
Metal Growing and DepositionOverview of CMOS Fabrication ProcessesThe CMOS Fabrication Process FlowDesign Rules
Outline
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Silicon ICs are created on large circular sheets of silicon called wafers (typically 100-300 mm diameter and 0.4-0.7 thickness)Many dies (1cmx1cm) can be created on a singlewafer
Starting with a bare polished surface, thewafer is subjected tothousands of steps in themanufacturing processMost steps are for creatingand patterning materials of layers and cleaning and
rinsing of the wafer
Overview of Silicon Processing
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An integrated circuit is created by stackinglayers of various materials in a prespecifiedorder
Device characteristics are determined by both the
electrical properties of the material and thegeometrical patterns of the layers
Most layers are created first, and thempatterned using the lithographic process
Doped silicon layers are the exception to this ruleThey are created with the desired shapes by usingthe lithographic process to define where thedopants can enter the silicion
Material Growth and Deposition
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SiO2, generally known as quartz glass, is a
critically important material in IC fabricationbecause
It is an excellent electrical insulator
It adheres well to most materialsIt can be grown or deposited on a silicon wafer
There are two types of SiO 2 layers in VLSI
circuitsThermal oxideChemical vapor deposition (CVD) oxide
Silicon Dioxide SiO 2
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Thermal Oxide
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A thermal oxide formed by the reaction Si+O 2 50 1100 SiO 2, where the silicon required for the reactionis obtained from the silicon wafer itself
This process is called thermal oxide growthThe oxide layer thickness depends on the temperature,crystal orientation, and growth time
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Thermal oxide can be grown above silicon layers,yet other layers need SiO 2 where no silicon isavailableIn this case, SiO 2 molecules are created using
gaseous reactions ( SiH 4 (gas)+2O 2 (gas) SiO 2(solid)+2H 2O (gas) ) and then deposit them onthe surface to provide an oxide coating
CVD Oxide
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The oxide layer thickness is controll ed
using the growth rateand deposition timeThis technique is calledCVD
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Silicon nitride Si 3N4 is another useful layer in ICfabricationSi 3N4 is created using gaseous reactionsNitrides are strong barriers to most atoms which
make them ideal for use as an overglass layer (a final proactive coating on a chip to protect itfrom contaminants)Si 3N4 have a relatively high dielectric constant
( = 7.8 )Silicon nitride is used to isolate adjacent FETsand act as a dielectric material in variouscapacitor structures
Silicon Nitride Si 3N4
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If we deposit silicon atoms on top of an amorphousSiO 2 layer, the silicon attempts to crystalize butcant find a crystal structure for reference This results in a formation of small crystallitesThis material is called polycrystal silicon or polysiliconPolysilicon is universally used as the gate materialin FETs because
It adheres well to silicon dioxideIt can be coated with a high-melting temperaturemetals to reduce the sheet resistance
A basic reaction to form Poly is (SiH4
500 600
Si+2H 2)
Polycrystal Silicon
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Aluminum Al is the most common metal used for interconnect wiring in ICsIt can be evaporate by heating in a vacuumchamber with the resulting flux used to coat the
wafer Al has good adhesion characteristics and iseasy to pattern
Aluminum exhibits some problems that can beavoided by adjusting the minimum linewidthCopper Cu has recently been introduced as areplacement to aluminum because of its highconductivity
Metals
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Doped layers are created by introducing donor or acceptor atoms into the wafer that can beeventually incorporated into the silicon crystalThis is accomplished by a technique called ionimplantation
The atoms are ionized in a chamber and then accelerated to high energiesThis beam pass though a mass separation unit that
selects the desired charge using a magnetic fieldThe fast moving ions are literally smashed into thesubstrate at typical energiesThe ions come to rest after several collisions
Doped Silicon Layers
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The slowing mechanismdamages the crystalThe wafer is heated in ananneal step to heal thecrystal and set dopants into
proper locations due toparasitic diffusionThe ion distribution into thesilicon can be approximated
to Gaussian
=
I =
Doped Silicon Layers (2)
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Basic sections of an ion implanter
The ion stoppingprocess
Gaussian implant profile
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Faculty of Engineering - Alexandria University 2013aculty of Engineering - Alexandria University 2013
Metal Growing and DepositionOverview of CMOS Fabrication ProcessesThe CMOS Fabrication Process FlowDesign Rules
Outline
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Processes include:
Wafer GrowthPhotolithographyDopingDiffusionImplantation
OxidationDepositionDielectricPolysiliconMetals
EtchingChemicalChemical-MechanicalMechanicalEpitaxial Growth
Overview of CMOS FabricationProcesses
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Methods - (1) Czochralski(CZ) (2) HorizontalBridgman (3) Float Zone
we will discuss only method #1 as it is the dominantproduction for Si
Wafer Growth
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Create large ingots of semiconductor materialby heating, twisting, and pulling. (~ 1-2 meterslong by 100-300mm diameter)Entire ingot aligned to the same crystal lattice
orientation (single-crystal)Remove all impurities all one elementSlice ingot into very thin (~400-750 m) discs
called wafersSome wafer are uniformly doped with specificimpurities (e.g. Boron for p-type wafer with N A=10 14 cm -3)
Wafer Growth (2)
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Photolithography is used to create a pattern oneach layer with submicron features to a materiallayer In photolithography, the shadow of a pattern is
optically projected onto the surface of the chipPhotographic-type techniques are employed totransfer the pattern to the surface
Photolithography
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l f l d 2013l f l d 2013
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Transfer desired pattern to an optical mask thatis clear except where a pattern/shape is desiredCover the entire wafer surface with photoresist(PR) ~1m thick (positive or negative types)
After exposure, the photoresist is developedusing a chemical rinse
Photolithography (2)
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Expose the wafer to light through the opticalmask (a piece of glass with the desired pattern)
takes ~ 1-5 seconds exposureUse chemical processing to remove PR only
where it has been exposed to lightthe pattern is now transferred from the optical mask towafer surface
Photolithography (3)
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In positive photoresist, regions shielded from thelight are hardened in the development process,while regions that are exposed to the light arerinsed away
The hardened resist layer protects underlyingregion from the etching process (reactive-ionetch)Negative photoresist has opposite characteristics
Photolithography (4)
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Subsequent process steps (e.g. oxidation,diffusion, deposition, etching) are performed.
only areas without PR will be affected; PRblocks/masks remaining areas
After all necessary processing through PRpattern, remove all PR using a chemicalprocessFigure below shows etching of poly silicon
Photolithography (3)
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photolithography and an example of etchingpolysilicon
Photolithography (4)
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Patterning an oxide layer for diffusion of impurities
(forming a pn junction)
Example Photolithography Process
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Doping: addition of impurities (Phosphorus,Boron) to Si to change electrical properties byadding holes/electrons to the substrateDiffusion: movement of something from area of
high concentration to area of low concentration
Masking layer (e.g. PR) used to block the wafer surface except where the dopants are desired
Doping: Diffusion
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Doping: Diffusion (2)
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Wafer placed in high-temperature furnace(~1000C) with source of the impurity atom
high temperature speeds diffusion process
Impurities uniformly spread into the exposed
wafer surface at a shallow depth (0.5 - 5m )takes ~0.5 10 hoursconcentration can be reliably controlled (10 12 -10 19 cm -3)
Profile different for (a) constant source and (b)finite source of impurities
Diffusion
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Diffusion (2)
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Implantation functionally similar to diffusionatoms are shot into the wafer surface short (~10min.) high temperature (~800C)annealing step fits the implanted atoms into the
substrate crystal lattice
Doping: Ion Implantation
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Implantation advantagesmore uniform across thewafer than diffusionallows for very precise
control of where impuritieswill bepeak concentrations canbe beneath the wafer
surfaceit does not require a longperiod of time at hightemperature (which can
be harmful)
Implantation vs. Diffusion
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y g g yy g g y
Disadvantagesimplanted junction must remain near wafer surface (~0.1 - 2m) cannot go as deep as a diffused junction
Impurity concentration profile (concentration vs.depth) is different for diffusion and implantation,but both are well known and predictable
Implantation vs. Diffusion
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Diffusion Implantation
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y g g yy g g y
Insulating dielectric layerskey element in semiconductor fabricationisolate conductive layers on the surface of the wafer.
Si has a good native oxideSilicon oxidizes (combines with Oxygen) to form adielectric oxide called silicon dioxide, SiO 2One of the most important reasons for the success of Silicon
SiO2a good insulating layer can be created by exposing Si to an O 2 environmenthas similar material properties (e.g. thermal expansioncoefficient, lattice size, etc.) of the native material (Si)
can be grown without creating significant stresses
Oxidation
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y g g yy g g y
At elevated temperatures (~1000C) the oxidegrows quickly
native oxides grown at elevated temperatures arereferred to as thermal oxides
thermal oxide grown in Si can be masked by PRSi thermal oxide consumes 44% of its depth in Si
Oxidation (2)
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y g g yy g g y
Deposition: addition of materials to the top of wafer surface
Dielectrics:Offer a variety of dielectric materials including SiO 2and SiN.Can be deposited on top of all other materials usedin semiconductor fabrication.Can be deposited in thick layers (~1-2 m ).
Deposition
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Polysilicon:
Granular Si with similar material properties to single-crystalSi and SiO2.Used to form MOS gates, resistors, capacitors, and memorycells.Native thermal oxide, SiO 2 , can be grown on top of polysilicon.Can withstand subsequent high temperature steps (unlikemetal)Can be doped to set resistance (low for interconnects, highfor resistors)
Metals:Form low resistance interconnections.Can not withstand high temperature process steps.Many metal interconnect layers can be used, insulated by
Deposition (2)
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Etching (2)
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Various deposition processes on a wafer produce rough surfaces with many hills andvalliesChemical-mechanical polishing (CMP) uses a
combination of chemical etching andmechanical sanding to produce planar surfacesas shown
Chemical-Mechanical Polishing
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Epitaxial growth: process of creating single-crystal
silicon from a thick layer of deposited silicon(polysilicon)Process is somewhat complex and involves the use of aseed crystal that allows an annealing process to alignthe crystals of the deposited material
Create single-crystal material from deposited (non-single-crystal) materialEpitaxial layer has constant doping profile
important for buried layers in bipolar transistorsEpi doping can be higher or lower and of same or opposite type than substrate dopingEpi layer can be very thick (~1-20 m ).Epi layer formed by annealing a deposited layer from aseed crystal
Epitaxial Growth
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Metal Growing and DepositionOverview of CMOS Fabrication ProcessesThe CMOS Fabrication Process FlowDesign Rules
Outline
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Isolation between devices
thick insulator called Field Oxide, FOXWhat is a process
sequence of step used to form circuits on a wafer use additive (deposition) and subtractive (etching) steps
n-well processstarts with p-type wafer (doped with acceptors)
can form nMOS directly on p-substrate
add an n-well to provide a place for pMOS
The CMOS Fabrication Process Flow
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Initial Sequence in CMOS Fabrication
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p-epitaxial layer isgrown on the top of ap+ wafer by droppingsilicon atoms on theheated wafer n-well regions arecreated in the epitaxialsubstrate using a
masking step Active areas aredefined by a maskingstep and a silicon nitride
layer is patterned on a
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Initial Sequence in CMOS Fabrication(2)
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Silicon is etched fromthe defined regionsOxide is the growth or deposited in the
etched regions to formFOX isolating regionsThe silicon nitride andoxide layers areremoved to get thewafer ready for transistor fabrication
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Formation of nFETs and pFETs
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FETs are formed using aself-aligned gate processFirst, the gate oxide isgrown as shown in (a)
Next, the polysilicon layer is deposited andpatterned to formtransistor gates (b)
pSelect and nSelectmasks are used to createpActive and nActiveregions, respectively,using the
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First metal interconnect layer
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CVD oxide is used tocoat the surface (a)Electrical contact withn+ and p+ regions is
established by etchingholes in the oxide usingan active contact mask(b)The first metal layer isdeposited andpatterned with a Metal1
mask (c)
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Chip Packaging
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After all of the metal layers have been added, the
entire chip is covered with a silicon nitride overglasslayer A pad frame arrangement is used to interface thesilicon circuitry to the outside worldLarge metal bonding pads surround the central chipcore areaWires are attached between the pads and outputpins on the package
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Metal Growing and Deposition
Overview of CMOS Fabrication ProcessesThe CMOS Fabrication Process FlowDesign Rules
Outline
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Design rules (DRs) are a set of geometrical
specifications that dictate the design of the layoutmasksSuch rules provide numerical values for minimumdimensions, line spacing, and other geometrical
quantitiesDRs are derived from the limits on a specificprocessing line and must be followed to insurefunctional structures on the fabricated chip
There are given numerical values in the DR listing;violating these values may lead to failure. In our notationw = minimum width specifications
s = minimum spacing value
Design Rules
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DRs have units of length (usually m)DRs change with the fabrication technologyThe popularity of VLSI fabrications hasintroduced the concept of the silicon foundry
A foundry allows designers to submit designsusing a state-of-the-art processMost foundry operations allow the submission of designs using a simpler set of design rules that
can be easily scaled to different processesThese are called lambda design rules where allDRs are expressed in terms of lambda( = 1
2)
Design Rules (2)
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Design rules can be classified into:Minimum widthMinimum spacingSurround
ExtensionExample of minimum spacing and width rules(poly)
Design Rules (3)
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Example of a surround rule (an active contact)This rule guards against a misaligned contactcut patterns during the lithographic exposuresetup
Design Rules (4)
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The accuracy of photolithography is the mainfactor that can lead to misalignment problemsFigure shows a potential problem with activecontacts due to misalignment
Design Rules (5)
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Extension-type design rules also rend to bebased on misalignment problemsFigure shows the extension distance rule for polysilicon gate and a potential misalignment
failure
Design Rules (6)
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Some geometrical design rules originate fromphysical considerations such as
The linewidth limitation of an imaging systemThe reticle shadow projected to the surface of the photoresistdoes not have sharp edges due to optical diffraction
For example, a lightwave with an optical wavelength of cannotaccurately image a feature size much less than
The etching process introduces another type of problemas shown in Figure
Physical Limitations
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