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Appendix B: System Development Example MTT48 V2.1 B - 1
APPENDIX B:
SYSTEMDEVELOPMENT
Appendix B: System Development Example MTT48 V2.1 B - 3
68HC08 SYSTEM EXAMPLE
Simple application set-up
• Power-On / Reset
• CPU Initialization
• Memory initialization
Appendix B: System Development Example MTT48 V2.1 B - 4
APPLICATION DESCRIPTION
Basic automotive instrument cluster panel
• Displays PRNDL setting based on 3 discrete inputs– Port A PTA2-PTA0
• Calculates and displays vehicle speed by measuring a pulse frequency– 1 Pulse indicates 1 revolution of wheel axle– Input on timer channel 1
• Receives data relating to warning lamps from powertrain control module via
SCI at 9600 baud– Eight warning lamp discrete outputs on Port B
(Engine over-temp, low oil pressure, low fuel, service engine, etc.)
Appendix B: System Development Example MTT48 V2.1 B - 5
APPLICATION DESCRIPTION (CONT.)
• Receives battery voltage, coolant temperature, and outside air temperature values
from 8 bit A/D converter via SPI– Port A Bit 7 as SS line for A/D
• Key in ignition generates an external Interrupt on IRQ2
• 4 MHz external crystal and desire 8 MHz bus frequency
Appendix B: System Development Example MTT48 V2.1 B - 6
INSTRUMENT PANEL CONTROLLER
IRQ2Key in ignition
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
Warning Light 1
Warning Light 2
Warning Light 3
Warning Light 5
Warning Light 6
Warning Light 7
Warning Light 8
Warning Light 4
68HC708XL36 8-Bit A/D
SSPTA7
SPSCKMOSIMISO
SPSCKMOSIMISO
Battery Voltage
Coolant Temp
Air Temperature
(SCI) TXD
(SCI) RXD
To Powertrain Control Module
From Powertrain Control Module
PTA2
PTA1
PTA0
From PRNDL Switch 3
From PRNDL Switch 2
From PRNDL Switch 1
TCH1Axle Ref. Pulses
Appendix B: System Development Example MTT48 V2.1 B - 7
POWER-ON RESET
At Reset, the following occurs
• All registers set to initial default values
• Interrupts are disabled
• Stack Pointer set to $00FF
• Program Counter load with value at $FFFE-$FFFF
• Program execution begins
Appendix B: System Development Example MTT48 V2.1 B - 8
CPU INITIALIZATION
Set proper bus frequency of 8 MHz
• Configure CGM for proper bus frequency– Must use PLL, N = 8, L = 6– See CGM exercise
May wish to move stack location
• Example: Move stack to address $0100LDHX #$0101 TXS ; Subtracts 1 in
process
Initialize/clear RAM to known state
• Could be performed using DMA– See DMA exercise part 4
Appendix B: System Development Example MTT48 V2.1 B - 9
CPU INITIALIZATION
If using interrupts
• Initialize interrupt service routines– TIM Channel 1– SCI Transmit and Receive– SPI Transmit and Receive– IRQ2
Enable interrupts
Appendix B: System Development Example MTT48 V2.1 B - 10
I/O PORT INITIALIZATION
NOTE: Order of submodule initialization may or may not be critical to
application
Configure I/O Ports
• PRNDL– Set Port A Data Direction Bits 2-0 as inputs (default)
• A/D Slave Select Line– Set Port A Data Bit 7 to 1 to disable SS line– Set Port A Data Direction Bit 7 as an output
• Warning lamps – Write $00 to Port B Data register to deactivate warning lamps– Set all Port B Data Direction bits to outputs
Appendix B: System Development Example MTT48 V2.1 B - 11
SPI MODULE INITIALIZATION
Configure SPI module
• Select Master mode, polarity, phase and baud rate– SPMSTR bit = 1– CPOL,CPHA = 01 Idle low, Read data on 2nd clock edge– SPR1:SPR0 = 10 Baud rate of 250 KHz (8 MHz bus)
• Turn on SPI– Set SPE bit in SPI Control register
• Interrupts– Enable interrupts as required by application
• SPIE bit for transmission complete interrupt (SPIF) • TDIE bit for transmit register empty interrupt (TDRE)
Appendix B: System Development Example MTT48 V2.1 B - 12
SCI MODULE INITIALIZATION
Configure SCI module to communicate with Powertrain Control Module
• Select number of data bits, parity, and baud rate– M = 0 8 data bits– PEN,PTY = 0X Parity disabled, Parity Type is don’t care– SCP1:SCP0 = 01 Prescaling of 3– SCR2:SCR1:SCR0 = 001 Divisor of 2 9600 baud
from 4 MHz external crystal frequency
• Turn on SCI– Set ENSCI bit in SCI Control Register 1
• Interrupts– Enable interrupts as required by application
• TCIE bit for transmission complete interrupt (TC) • TIE bit for transmit register empty interrupt (TDRE)• RIE bit for data received interrupt (RDRF)• Error interrupts (OR, NF, FE, PE)
Appendix B: System Development Example MTT48 V2.1 B - 13
TIM INITIALIZATION
Initialize TIM module for measuring wheel speed reference pulse frequency
• Configure prescaler value smallest resolution– PS2:PS1:PS0 = 000 System clock ÷ 1 (default)
• Resolution = 125 ns at 8 MHz bus clock
• Configure channel 1 for input capture on rising edge – MS1A = 0 Input capture– ELS1B:ELS1A = 01 Rising edge detection
• Interrupt as needed by application– Set CH1E bit for interrupt generation on capture
• Enable Timer – Clear TSTOP bit in Timer Control Register
Appendix B: System Development Example MTT48 V2.1 B - 14
ADDITIONAL INITIALIZATION
Initialize any RAM locations as required by application
Begin Program execution
Appendix B: System Development Example MTT48 V2.1 B - 15
OPTIONAL INITIALIZATION
Configure DMA module as needed by application
• Could use DMA to service SCI or SPI interrupts
• Set channel source and destination register addresses
• Set-up register
• Set-up Source/Destination address calculation– Interrupt source– Byte/Word Count
• Enable channel in DMA Control Register 1 (DC1)– Set Channel enable bit
• Interrupt on complete of transfer– Set Channel interrupt enable bit in DC1
Appendix B: System Development Example MTT48 V2.1 B - 16
OPTIONAL INITIALIZATION
Enable COP module
• Clear COPD bit MOR register– Must be done at EPROM programming time
Enable LVI module
• Set LVIPWR bit in LVI Status and Control register
• Enable Reset Generation if desired– Set LVIRST bit
• Lock LVI– Set LVILCK bit to write protect register– Think low power modes
Appendix B: System Development Example MTT48 V2.1 B - 17
ADDITIONALSYSTEM CONFIGURATION
Before executing WAIT or STOP configure XIRQ module
• Enable IRQ2 interrupt
• Clear IMASK2 in IRQ Status and Control register
Appendix B: System Development Example MTT48 V2.1 B - 18
SYSTEM CONFIGURATION EXAMPLE
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