Analog to Digital Conversion - Heidelberg University · 2018-01-19 · Analog to Digital Conversion...

Analog to Digital Conversion

Florian ErdingerLehrstuhl für Schaltungstechnik und Simulation

Technische Informatik der Uni Heidelberg

VLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 1

Content

§ Introduction§ ADC Characteristics / Terminology§ Sampling & Quantization§ ADC Properties: ENOB, INL, DNL§ ADC Architectures

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Analog to Digital Conversion

§ Why process signals in the digital domain?§ Effect of reduced CMOS feature size and supply voltages:

• Do not really improve performance of analog signal processing, same Cs needed (see later) (kT/C noise)

• Digital circuits: more compact, faster, automated design less power dissipation

§ à Convert analog signals into the digital domain for processing

§ Rapid progress in digital signal progress has put high demands on AD converters

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DSP DACADCanalogeInformation

analogeInformation

DigitaleSignalProcessor

Basic Principle of Conversion

§ ADC function: quantize signal, find digital representation• digital output codes represent analog values• converter finds output code which best matches input signal

§ Basic ADC components:• Sample & hold (S&H) circuit for the input signal• Reference circuit to define the conversion steps• A DAC to provide comparison levels• Comparator to compare the input signal to the reference levels• Some (digital) logic to store intermediate values, control

switches etc.

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ADC Characteristics (1)

§ Resolution N: number of bits (8 bit à 28 = 256 steps)• resolution is often confused with accuracy

§ Signal to Noise Ratio SNR§ Effective Number Of Bits ENOB

• number of bits that are noise free• lower bits can be used when averaging over many samples• SNR, determines ENOB

§ Transfer Characteristic:• Missing codes, monotonicity• Differential Non-Linearity DNL: ‘quality’ of bin sizes• Integral Non-Linearity INL: deviation from straight line

§ Sampling Rate fs à speed• Bandwidth BW, usually 0..fs/2 (Nyquist criterion)

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ADC Characteristics (2)

§ Accuracy

Offset Error Gain Error

• can usually be fixed by calibration

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ADC Characteristics (3)

§ Full Scale Range FSR (max. / min. input)• Vfs = analog full scale signal that can be converted

§ LSB / MSB: Least and Most Significant Bit§ ALSB = FSR / 2N : step size in analog domain § PADC : power consumption

§ FoM: Figure of Merit• FoMs try to incorporate ADC properties in a single number for

quick comparison• give an estimate of the quality of the design• most importantly: PADC, BW and ENOB (SINAD)• different FoMs exist• classical: Walden FoM, newer: Schreier FoM• definitions later

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Sampling & Quantization

§ ADC circuit performs two step process: sampling & quantization

§ Sampling: conversion of a time continuous signal to a time discrete signal

§ Nyquist CriterionSignal can be reconstructed if: fs > 2 x fmax,sig

§ Quantization: conversion of an analog (amplitude continuous) signal to a discrete value from a finite set of values

§ Quantization is a non-linear operation, many input values are mapped to the same output value

VLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 8

Sampling

§ Switch and sampling cap form an RC, R is noisyvn2 = sqrt(4kTR)

VLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 9

§ The RC circuit “filters” the noise of the resistor

§ Choose C so that thermal noise is less than quant. noise

N req. Chold (*) VkTC

8 0.3 fF 1.2 mV

10 0.5 pF 0.3 mV

12 0.8 pF 70 uV

14 13 pF 17uV

16 213 pF 4.4uV

§ Oversampling converters can use smaller Cs à see later …

(*) for Vfs = 1V

Quantization Error

§ low resolution (N<7) à quantization strongly depends on the signal, shows up as distortion

§ for larger resolution: quantization can be approximated as white noise (in the band 0..fs/2)

§ assumption: probability densityof the signal is uniform across the conversion range à error varies linearly from

-0.5 LSB to +0.5 LSB§ Quantization error power (Q2) is estimation value of the

variance:

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Signal to Noise Ratio (SNR)

§ Signal-to-quantization-noise:

compares power of full scale sine wave to quant. error power

With and

we can approximate

§ SNQR = 62 dB for a 10 bit ADC74 dB for a 12 bit ADC

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Effective Number of Bits

§ How many bits are noise free?§ Calculation uses signal-to-noise-and-distortion ratio

(SINAD or SNDR)

§ Effective Number of Bits (ENOB) is given by:

(using eq. on prev. slide and solving for N)

§ @ 8 bit, 0.5 LSB if loss is tolerable, @ 12 bit, 1bit§ ENOB is used in figure of merits to compare the

performance of different ADCs (see later slides)

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Differential Linearity

§ The Differential Non-Linearity (DNL) is the deviation of each step to the ideal step ALSB:

§ usually specifiedas max(DNL)

§ sometimes: DNLrms

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Integral Linearity

§ The Integral Non-Linearity (INL) is deviation of the actual conversion curve from the ideal curve

§ INL is calculated with

where A(i) is the actual conversion curve

§ usually, the extremes arestated: min,max(INL)

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ADC ARCHITECTURES

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ADC Architectures

§ Two main categories: Nyquist rate / oversampled§ Nyquist rate ADCs: fsig,max = fs / 2

• maximum achievable signal bandwidth determined by Nyquist criterion

• larger bandwidth achievable than with oversampled converters• usually limited to 12-14 bits

§ Oversampled ADCs: fsig,max << fs• oversampling trades speed versus resolution• very high resolution up to 18-20 bits achievable

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Nyquist Rate ADCs

§ Parallel Search (Flash Converters)• one step à very fast• requires 2N reference levels and comparatorsà very expensive (power & area)

• scaling bad, exponential growth in power and area§ Sequential Search (Successive Approximation)

• reference level is switched, for instance in binary fashion• N clock cycles for N bits• scales better than flash converter

§ Linear Search Converter• compare to ALL reference levels• must provide all reference levels successively• extremely slow but with minimum amount of hardware • can be made very robust w.r.t component variation

VLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 17

Flash ADC

§ Vin compared simultaneously to 2N

reference levelsà therm. code.

§ Very fast§ Expensive in power &

area§ usually only 6-7 bit§ Design challenges:

• cap load @ input• all comp. switch @

same time à XTALK• matching of Rs• Comp may not draw

current

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Two Stage Flash ADC

§ 2 flash stages: coarse & fine§ 1st stage: coarse conversion to for inst. half range for MSBs§ conversion to analog & subtraction from input signal§ 2nd stage: fine conversion for LSBs

§ slower than full flash architecture but substantially reduces cost (power & hardware)

§ error correction possible in 2nd stage by using more bits§ very popular for fast ADCsVLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 19

4 BitFlashUin DAC 4 Bit

Flashx 16

4 MSB 4 LSB

Successive Approximation

§ Compare input signal to DAC voltage (binary search)§ Output = DAC code generates V that is closest to Vin

§ 1st: compare to Vref / 2Vin < Vref/2 Vin < Vref/2

§ 2nd step: compare to Vref/4 compare to 3/2 Vref

§ ...§ N step required

§ Needs a precise DAC(matching)

§ no way back if an early decision was wrong

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S&H

Vref

Vin

Logik

Comparator

DAC

Single Slope ADC

§ Principle: • Convert input voltage to current • Integrate current à Vramp

• Measure time until Vramp reaches Vref using dig. counter• Use digital counter to measure time

§ Problem: time depends on devices characteristic• integration capacitor, current source

VLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 21

Vref

Vin time meas,dig. logic

t

Vrmp

sample Vin

T

T = (Vref-Vin)*C/Irmp

Slopesconstant

Vin

Vref

Dual Slope ADC

Trick to solve dependency on devices: dual slope architect.

VLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 22

RVref

Vin

time meas.dig. logic

Integrator Comparator

t

Vint

ResetT1 T

2

Vsig = T1Vin/RC

constant slopesSlope

depends on Vin

2 integrations to cancel out RC:Qsig = -T1 x Vin/R = -T2 x Vref /Rà Vin = T2 / T1 x Vref

à T2 = Vin/Vref x T2

§ T1 is fixed, measure T2 for digital output value

Exersice

§ In the mixed-mode simulation tutorial, you have designed a simple single slope ADC. Implement the current source with real devices and simulate the transfer characteristic.

§ What determines the INL of your ADC?§ Estimate the INL, then simulate.§ Can you improve it?§ What determines the DNL?§ Make a simple dual slope design as shown in the slides.

• Make an analog simulation first.§ Change R and C.§ If you still have time, implement a comparator.

Hint: start with a differential amplifier.

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Algorithmic ADCs

§ Type: sequential search§ SAR: uses DAC to provide reference levels§ Here: signal is modified and reference is constant§ Operation principle:

• N steps required for N bits, start with MSB• if (Vin > Vref) dig[i] = 1; out = 2 x (Vin-Vref);• else dig[i] = 0; out = 2 x Vin

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Uin

Bit i

Uref

Uref x 2

next stageComparator

Algorithmic ADCs

§

§ Principle is quite simple à very popular§ Can stage single stage stage or pipeline with more stages§ Implementation: current mode (SPADIC), capacitive§ Quality of stage (comparator, x2) determines number of bits§ Error correction possible in every stage

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Uin

Bit i

Uref

Uref x 2

next stageComparator

Pipelining

§ Use several (possibly identical) stages§ Compute result and forward to next stage§ Usually 1 bit / stage§ Very fast sample rate possible§ Digital output appears with latency, usually N clock cycles§ Well suited for algorithmic ADCs

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Sigma Delta ADC

§ Concepts:• Oversampling à fclk >> fs• Noise shaping à shift quant. noise out of signal band• Digital filtering à filter out of band noise• Decimation à output rate = fs

§ 1st order and higher order ΣΔ Modulators can be used à can get very complex

§ Two principal topologies of ΣΔ Modulators exist:• Time continuous• Time discrete

§ Here: time discrete modulators, 1st order...

VLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 27

§ Oversampling ratio is defined as

§ Nyquist converter: Quantization power is uniformly distributed over frequency till half the sample rate

§ Total noise power is found by integrating from 0 to fb

Oversampling

VLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 28

fb fs = fs,ny fs = 4 x fs,ny

BW

§ Reduced quantization error results in a reduced SNR and more ENOB:

§ Oversampling is only effective when the quantization error can be approximated as whiteà not effective for DC signals

§ A ’helper’ signal can be added to DC signals to be able to exploit oversample, for inst. white noise

§ Oversampling can be employed to improve ENOB not only valid for ΣΔ-ADCs but for any ADC

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Noise Shaping

§ Basic idea:§ Oversampling creates an additional frequency range

• mirror images of the signal in the frequency domain around fs(created by DTFT) are shifted further away due to oversampling

VLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 30

fb fs,ny 4 x fs,ny

BW

fb fs,ny 4 x fs,ny

BW

fs = fs,ny

fs = 4 x fs,ny

mirrors due to sampling

Noise Shaping

§ Push the quantization noise to higher frequencies§ Filter in later stage to remove out of band noise

§ In Z-domain we get:

§ using a unit delay for J(z) we get:

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Noise Shaping

§ Noise transfer to the output in the frequency domain using z-1 = ejωπ:(NTF = Noise Transfer Function)

total noise in band from 0 to f/2:

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fb fs /2

Org. quantizationenergy

Shaped quantizationenergy

freq (linear)

Noise Shaping

§ In band noise:

§ Reminder: this is only possible with oversampling§ In band noise power is related with a cube power

• OSR1 from oversampling• OSR2 from noise shaping loop

§ OSR x 2 à noise power / 8 (=9dB) à ENOB += 1.5

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Sigma Delta Modulator Scheme

§ Basic Scheme:

§ Input signal (X(s)) is oversampled with fs >> fb§ Signal component and quantization error are

circulated in a loop § Construct transfer function such that signal passes,

quantization error filtered (in signal band)§ Output: bit stream, average is the input signal§ Simplest form, 1st order modulator with 1 bit

quantizer (ADC) and 1 bit DACVLSI Design - Mixed Mode Simulation © F. Erdinger, ZITI, Uni Heidelberg Page 34

Exercise 2

§ Implement a simple Sigma Delta Modulator using VerilogA§ Simulate for a couple of DC input values§ Reconstruct the input signal from the bit stream using an

analog low pass filter

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