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HIGH SPEED LINEAR DESIGN SEMINARSWITZERLAND – NOVEMBER 2001
EurIng James M. Bryant – Head of European Applications
(+44) 7785-305598
james.bryant@analog.com
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Several different factors are encouraging the use of low voltage analog circuits:-
High density (sub-micron) IC processes have low breakdown voltages(these processes are valuable for their higher speed and smaller size – which leads to lower cost)
Battery powered equipment is more easily designed with low supply voltages
Low supply voltage tends to result in lower power dissipation,leading to fewer thermal problems, slower ageing, and longer battery life
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Present sub-micron processes have breakdowns of 7 V or less
There are both bipolar and CMOS processes with these feature sizes
The bipolar processes (XFCB and others) are used to manufacturehigh speed analog circuitry such as amplifiers and transceivers
CMOS processes make digital circuits, but are also used to makehigh speed and/or high performance data converters (ADCs and DACs)
and related products such as Direct Digital Synthesis (DDS) circuits
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Present sub-micron processes have breakdowns of 7 V or less
As circuit densities become higher breakdown voltages will be even lower
These processes allow very complex circuitsto be made very cheaply so the trend will continue
Smaller feature sizes also permit faster operation
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
But low voltage analog circuits have some problems:-
Reducing the supply voltage does not reduce noise
Techniques to improve headroom affect circuit performance
Low voltage circuitry is often single supply – which complicatesthe design of circuits which work with bipolar signals
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Reducing the supply voltage does not reduce noise
Classical precision analog circuitry used ±15 V supplieswhich allowed signal swings of ±10 V or 20 V pk-pk
Circuits operating from a modern 2.7 V supply will have a signalswing of a little over 2 V pk-pk – a 20 dB loss of dynamic range
Some users cannot tolerate this(Professional audio designers continually request amplifiers and converters with much higher supply voltages!)
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BIT SIZES FOR 2.5 V FULLSCALE CONVERTERS
RESOLUTION
N
2-BIT
4-BIT
6-BIT
8-BIT
10-BIT
12-BIT
14-BIT
16-BIT
18-BIT
20-BIT
22-BIT
24-BIT
2N
4
16
64
256
1,024
4,096
16,384
65,536
262,144
1,048,576
4,194,304
16,777,216
VOLTAGE
(10V FS)
625 mV
156 mV
39.1 mV
9.77mV
2.44 mV
610 V
153 V
38 V
9.54 V
2.38 V
596 nV
149 nV*
ppm FS
250,000
62,500
15,625
3,906
977
244
61
15
4
1
0.24
0.06
% FS
25
6.25
1.56
0.39
0.098
0.024
0.0061
0.0015
0.0004
0.0001
0.000024
0.000006
dB FS
-12
-24
-36
-48
-60
-72
-84
-96
-108
-120
-132
-144
*149nV is the Johnson Noise in a 27kHz BW of a 50 Resistor @ 25°C
Remember: 10-bits and 2.5 V FS yields an LSB of 2.5mV, 1000ppm, or 0.1%.All other values may be calculated by powers of 2.
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Techniques to improve headroom affect circuit performance
The commonest is to make low-voltage analog circuitry “rail-rail”
The term “rail-rail” can apply to input or output circuitry, or both
Rail-rail input stages have disadvantages over classical types
Rail-rail output stages have disadvantages too, but minor ones
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ISSUES WITH RAIL-RAIL INPUT STAGES
CLASSICAL BIPOLAR TRANSISTOR INPUT STAGE
VIN
Low Offset: As Low as 10V
Low Offset Drift: As Low as 0.1V/ºC
Temperature Stable Ibias
Well-Matched Bias Currents
Low Voltage Noise: As Low as 1nV/Hz
High Bias Currents: 50nA - 10A (Except Super-Beta: 50pA - 5nA, More
Complex and Slower)
Medium Current Noise: 1pA/Hz
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ISSUES WITH RAIL-RAIL INPUT STAGES
BIAS-CURRENT COMPENSATED BIPOLAR INPUT
VIN
Low Offset Voltage: As Low as 10V
Low Offset Drift: As Low as 0.1V/ºC
Temperature Stable Ibias
Low Bias Currents: <0.5 - 10nA
Low Voltage Noise: As Low as 1nV/Hz
Poor Bias Current Match (Currents May Even Flow in Opposite Directions)
High Current Noise
Not Very Useful at HF
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ISSUES WITH RAIL-RAIL INPUT STAGES JUNCTION FIELD EFFECT TRANSISTOR (JFET) INPUTOP AMP STAGE SHOWING OFFSET AND DRIFT TRIMS
Offset as Low as 50V
Offset TC ~ 5V/°C
Low Current Noise
Bias Current as Low as 20fA
Ib doubles every 10°C
Tradeoff Between Voltage Noise and Input Capacitances
1
DRIFTTRIM
2
OFFSETTRIM
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RAIL-TO-RAIL INPUT STAGES
Require two long-tailed pairs with inputs in parallel:
Vos, Ib, and CMRR vary over their common mode range
An on-chip inverter may be used to generate a power rail outside the external power supplies, but this adds noise.
It is often possible to use a ‘single-supply” op ampwhich allows the input signal to go to only one ofthe rails (usually ground).
OR
One with NPN BJTs (or P-Channel FETs)One with PNP BJTs (or N-Channel FETs)
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OP-90 PNP INPUT STAGE ALLOWSINPUT TO GO TO THE NEGATIVE RAIL
(“SINGLE-SUPPLY” INPUT)+VS
-VS
+VBIAS
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RAIL-RAIL INPUT STAGE
+VS
-VS
Bias compensation impossible
Bias current changes polarity with common-mode voltage
CMRR is poor at changeover
Circuit is more complex(it is actually two input stages)
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
Techniques to improve headroom affect circuit performance
The commonest is to make low-voltage analog circuitry “rail-rail”
The term “rail-rail” can apply to input or output circuitry, or both
Rail-rail input stages have disadvantages over classical types
Rail-rail output stages have disadvantages too, but minor ones
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CLASSICAL OP AMP OUTPUT STAGE
+VS
-VS
OUTPUT
NPN
PNP Unity (X1) voltage gain
Poor headroom
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RAIL-TO-RAIL OUTPUT STAGESHave very small headroom but high gain – which may cause stability problems
SWINGS TO RAILS LIMITEDBY SATURATION VOLTAGE
SWINGS TO RAILS LIMITEDBY FET “ON” RESISTANCE (~100)
+VS
-VS
OUTPUT
PNP
+VS
OUTPUT
NPNNMOS
PMOS
-VS
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
A basic problem with modern low voltage analog circuitsis that their supplies are generally unipolar
Classic precision analog circuits had bipolar supplies (usually ±15 V)
Unsurprisingly unipolar supplies complicate systems with bipolar signals
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
There are three simple ways of handling bipolar signalsin a system with a unipolar power supply
Generate a negative supply
Provide an offset reference
Use differential signals
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
There are three simple ways of handling bipolar signalsin a system with a unipolar power supply
Generate a negative supply
Provide an offset reference
Use differential signals
ADM660
Positivesupply
Negativeoutput
Capacitors are 10 µFlow-ESR types
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
There are three simple ways of handling bipolar signalsin a system with a unipolar power supply
Generate a negative supply
Provide an offset reference
Use differential signals
VoltageReference OR
POSITIVE SUPPLY
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LOW VOLTAGE, HIGH SPEEDPRECISION ANALOG CIRCUITRY
There are three simple ways of handling bipolar signalsin a system with a unipolar power supply
Generate a negative supply
Provide an offset reference
Use differential signals
ADC
POSITIVE SUPPLY
AD8138
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BASIC PROBLEMS OF HIGH-SPEEDPRECISION ANALOG CIRCUITRY
Most problems with the applications ofprecision high-speed analog circuitry
arise from overlooking basic laws of physics
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MURPHY’S LAW
Any effect which you think can be disregarded, can’t.
Nature always sides with the hidden flaw.
IN ANY SET OF CIRCUMSTANCESTHE WORST THING THAT CAN HAPPEN - WILL
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IMPORTANT COROLLARIES TO MURPHY’S LAW
After it has worked successfully for two weeks, it will fail during the first public demonstration.
Equipment blows to protect fuses.
Interchangeable parts aren’t.
Fail-safes don’t.
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BASIC LAWS INVOLVED IN THE DESIGNOF HIGH SPEED MIXED SIGNAL CIRCUITRY
Ohm’s Law
Kirchoff’s Law
Faraday’s Laws
Lenz’s Law
MURPHY’S LAW!
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PRINTED CIRCUIT BOARD TRACK RESISTANCEOHM’S LAW PREDICTS 1 LSB DROP IN
5cm OF STANDARD PCB TRACK — BUT WHO BELIEVES OHM’S LAW?
FOR 1 OZ. COPPER:
= 1.724 X 10-6 = CM, Y = 0.0038cm
R = 0.45 m
= “NUMBER OF SQUARES”
R = SHEET RESISTANCE FOR 1 SQUARE (Z - X),R = 0.45m/SQUARE
ZX
ZX
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SKIN EFFECT
TOP
BOTTOM
COPPER CONDUCTOR
HF Current flows onlyin thin surface layers
-7
Skin Depth: 6.61 f cm, f in Hz
Skin Resistance: 2.6 x 10 f ohms per square, f in Hz
Since skin currents flow in both sides of a PC track, the value ofskin resistance in PCBs must take account of this
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SKIN EFFECT
GROUND PLANE
PC BOARD(DIELECTRIC)
MICROSTRIPCONDUCTOR(CURRENT FLOW NORMALTO DIAGRAM)
HF CURRENT FLOWS IN ONESIDE OF THE CONDUCTOR ONLY
REGION OF RETURNCURRENT FLOW
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LEAKAGE RESISTANCE ON PC BOARDS
SURFACE LEAKAGE ON A PCB IS UNPREDICTABLE. R1 IS NOT NECESSARILY LESS THAN R2.
IF A VULNERABLE CONDUCTOR IS SURROUNDED BY A GUARD RING (ON BOTH SIDES OF THE BOARD) WHICH IS AT THE SAME POTENTIAL AS THE CONDUCTOR IT IS GUARDING, THE EFFECT OF LEAKAGE RESISTANCE WILL BE MINIMIZED.
LEAKAGE RESISTANCE BETWEEN SURFACE TRACKS ON A PCB IS GENERALLY MUCH LARGER THAN BETWEEN PLATED HOLES.
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A VIRGIN TEFLON STANDOFF INSULATORHAS MUCH LOWER LEAKAGE THAN A
PRINTED CIRCUIT BOARD TRACK
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ELECTROSTATIC DISCHARGE (ESD)
All ICs are vulnerable to ESD damage – sub-micron circuits are especially so
Internal ESD protection circuits may degrade performance: This is a design tradeoff
ESD damage may not be catastrophic, but may degrade performance
Keep IC out of potential discharge paths:Touch conductive foam or the equipment chassisbefore removing or inserting an IC
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THE EQUIVALENT CIRCUITOF A RESISTOR IS NOT
BUT
++
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GAIN OF 100 STAGE
-
+
100 9.9k
INPUT0 - 100mV
OUTPUT0 - 10V
Resistor mismatch due to mismatch of temperature coefficients, mismatch of temperature (possibly due to self-heating), or both, can cause errors.
Ideally, all resistors whose matching can affect accuracy should be fabricated on a single substrate.
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HIGH VALUE RESISTORS
Likely to be Less Stable
and
Non-Linear with Voltage
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RESISTOR JOHNSON NOISE
All Resistors Have Noise: Vn = (4kTBR)
It is possible to reduce the noise of a resistor by reducing T, B, or R but it is NOT possible to reduce k because Boltzmann is dead.
T is Absolute TemperatureB is Bandwidth in HertzR is the Resistance in Ohmsk is Boltzmann’s Constant
(1.38E-23 J/K)
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RESISTOR CAPACITANCE
All Resistors Have Capacitance
There is capacitance between the terminals -there is also capacitance to nearby circuitry
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CAPACITANCE
d
0.00885 E A
dr
r
r
2
2A
Commonest type of PCB uses 1.5mmglass-fiber epoxy material with E = 4.7
Capacity of PC track over ground planeis roughly 2.8pF/cm
C = pF
A = plate area in mm
d = plate separation in mm
E = dielectric constant relative to air
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CAPACITIVE COUPLING EQUIVALENT CIRCUIT
CIN
VN Z1
+
VCOUPLED
-
Z1 = CIRCUIT IMPEDANCE
Z2 = 1/jC
VCOUPLED = VN
Z1
Z1 + Z2
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CAPACITIVE SHIELDING
CAPACITIVE SHIELD INTERRUPTS THE COUPLING ELECTRIC FIELD
EQUIVALENT CIRCUIT ILLUSTRATES HOW A CAPACITIVE SHIELD CAUSES THE NOISE CURRENTS TO RETURN TO
THEIR SOURCE WITHOUT FLOWING THROUGH Z1
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CAPACITIVE EFFECTS DUE TO METAL LIDS
METAL (KOVAR) LID
CERAMIC
SIDEBRAZE CERAMIC D.I.L. PACKAGES SOMETIMES HAVE ISOLATED METAL LIDS.
THESE ARE VULNERABLE TO CAPACITIVE INTERFERENCE AND SHOULD BE GROUNDED (IF POSSIBLE).
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STRAY CAPACITY BETWEEN CHIP BONDWIRES
0.2pF
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WITH A HIGH PERFORMANCE CONVERTER ON AHIGH SPEED DATA BUS, IT IS NOT POSSIBLE TO SHIELD
THE ANALOG PORT FROM THE DIGITAL NOISE
IC
ANALOG PORTFASTDATABUS
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BUFFER LATCH IN A SEPARATE PACKAGEUSED AS A FARADAY SHIELD
LATCH/BUFFER
ANALOG PORTFASTDATABUS
CONVERTER
A BUFFER/LATCH CAN ACT AS A FARADAY SHIELD BETWEEN A FAST DATA BUS AND A HIGH PERFORMANCE CONVERTER.
IT ADDS COST, BOARD AREA, POWER CONSUMPTION, RELIABILITY REDUCTION, DESIGN COMPLEXITY, AND IMPROVED PERFORMANCE.
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EQUIVALENT CIRCUITS OF A REAL CAPACITOR
IDEAL CAPACITOR
MOST GENERAL MODEL OF A REAL CAPACITOR
LEAKAGE CURRENT MODEL
HIGH CURRENT MODEL
HIGH FREQUENCY MODEL
DIELECTRIC ABSORPTION (D.A.) MODEL
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HIGH FREQUENCY DECOUPLING(REQUIRED EVEN BY LF ANALOG CIRCUITS)
SURFACE MOUNTCAPACITOR
IDEAL HF DECOUPLING HAS
1. LOW INDUCTANCE CAPACITOR (MONOLITHIC CERAMIC) 2. MOUNTED VERY CLOSE TO THE IC 3. WITH NO LEADS (SURFACE MOUNT) OR VERY SHORT LEADS 4. AND SHORT, WIDE PC TRACKS
IT MAY BE SHUNTED WITH A TANTALUM BEAD ELECTROLYTIC TO PROVIDE GOOD LF DECOUPLING AS WELL
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CAPACITORS HAVING SIGNIFICANT DIELECTRICABSORPTION ARE USELESS FOR
SAMPLE-AND-HOLD APPLICATIONS
VC
B
+V AV
CAPACITORVOLTAGE
OA B C
SWITCH POSITION
TIME
DIELECTRIC ABSORPTION CAUSES A BRIEFLY DISCHARGED CAPACITOR TO RECOVER A PERCENTAGE OF ITS PREVIOUS
CHARGE ON BEING OPEN CIRCUITED
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INDUCTANCE
L
2R L, R in mm
L
W H
EXAMPLE: 1cm of 0.5mm o.d. wire has an inductance of 7.26nH(2R = 0.5mm, L = 1cm)
2L
R
2L
LW+HW+H
( )
)WIRE INDUCTANCE = 0.0002L ln - 0.75 H
)
(
STRIP INDUCTANCE = 0.0002L ln + 0.2235 + 0.5 H(
EXAMPLE: 1cm of 0.25 mm PC track has an inductance of 9.59 nH
(H = 0.038mm, W = 0.25mm, L = 1cm)
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NONIDEAL AND IMPROVED SIGNAL ROUTING
LOAD
LOAD
LOAD
NONIDEAL SIGNAL TRACE ROUTING
IMPROVED TRACE ROUTING
LOAD
LOAD
LOAD
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BASIC PRINCIPLES OF INDUCTIVE COUPLING
INTERFERENCE CIRCUIT SIGNAL CIRCUIT
M = MUTUAL INDUCTANCEB = MAGNETIC REFLUX DENSITYA = AREA OF SIGNAL LOOP
N = 2fN = FREQUENCY OF NOISE SOURCE
V = INDUCED VOLTAGE = NMIN = wAB
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PROPER SIGNAL ROUTING REDUCESMUTUAL INDUCTANCE
V1
V2
Z1
Z2
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MUTUAL INDUCTANCE AND SIGNAL COUPLINGIN RIBBON CABLE
FLAT RIBBON CABLE WITH SINGLE RETURN HAS LARGE MUTUAL INDUCTANCE BETWEEN CIRCUITS
SEPARATE AND ALTERNATE SIGNAL AND RETURN LINES FOR EACH CIRCUIT REDUCE MUTUAL INDUCTANCE
TWISTED PAIRS REDUCE MUTUAL INDUCTANCE STILL FURTHER
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MAGNETIC SHIELDING
Magnetic shielding is not as easily accomplished as electrostatic shielding, but may be done at HF with a simple conducting screen, and at LF and DC with a screen of high
permeability material such as Mu-metal.
PC Copper foil is effective as a magnetic shield above 20 MHz
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RESONANT CIRCUITS FORMED BYDECOUPLED POWER LINES
SMALL SERIES RESISTANCECLOSE TO THE IC REDUCES THE Q
EQUIVALENT CIRCUITOF DECOUPLED POWERLINE - RESONANT AT
f =1
2 LC
IC IC
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SATURATION
Inductors with solid cores (magnetic alloy or ferrite) will behave non-linearly if required to carry too much current
This is unlikely to be a direct problem in precision circuitry but may affect power supply noise performance and thus affect precision circuitry indirectly.
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STRAY CAPACITANCE MAKES ALL INDUCTORSINTO TUNED CIRCUITS
1
2 LC
RESONANT FREQUENCY =
f =
L
STRAY C
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Q OR “QUALITY FACTOR”
The Q of an inductor or resonant circuit is a measure of the ratio of its reactance to its resistance.
The resistance is the HF and NOT the DC value.
The 3 dB bandwidth of a single tuned circuit is Fc/Q where Fc is the center frequency.
Q = 2f L/R
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KIRCHOFF’S LAW
I
IGROUND RETURN CURRENT
SIGNALSOURCE
ADC
AT ANY POINT IN A CIRCUITTHE ALGEBRAIC SUM OF THE CURRENTS IS ZERO
ORWHAT GOES OUT MUST COME BACK
WHICH LEADS TO THE CONCLUSION THATALL VOLTAGES ARE DIFFERENTIAL
(EVEN IF THEY’RE GROUNDED)
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THE IDEAL GROUND
SIGNAL
INFINITE CONDUCTIVITYZERO VOLTAGE
SIGNALSOURCE
ADC
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A MORE REALISTIC GROUND
SIGNAL
EXTERNALCURRENTSOURCE
SIGNALSOURCE
ADC
VOLTAGE DUE TO SIGNAL CURRENT AND (PERHAPS)
EXTERNAL CURRENT FLOWING IN GROUND IMPEDANCE
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SUPPLY AND GROUND NOISE
Digital circuitry is noisy
Analog circuitry is quiet
Circuit noise from digital circuitry carried by power and ground leads can corrupt precision analog circuitry
It is advisable to separate the power and ground of the digital and analog parts of a system
Analog and digital grounds must be joined at ONE point
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ANALOG AND DIGITAL GROUND
Monolithic and hybrid ADCs frequently have separate AGnd and Dgnd pins which must be joined together at the device.
This is not done from a desire to be difficult, but because the voltage drop in the bondwires is too large to allow the connection to be made internally.
The best solution to the grounding problem arising from this requirement is to connect both pins to system “analog ground.”
It is likely that neither the digital noise so introduced in the system Agnd, nor the loss of digital noise immunity, will seriously affect the system performance.
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Grounding ADCs & DACs
Data Converters (ADCs and DACs)are accurate and sensitive analog devices whose
analog ports are vulnerable to unwanted noise(most advice in this lecture applies to both ADCs & DACs)
Mixed Signal Systems(systems with both analog and digital processing)
often have separate analog and digital ground planesin order to isolate their sensitive analog signals fromthe noise which is often present on the digital ground
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Grounding ADCs & DACs
ADCs & DACsfrequently have separate analog and digital ground pins
(labelled, respectively, AGND and DGND)
These should be connected together andto the analog ground plane of the system
Even if the data sheet suggests otherwise!
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AGND
CONVERTER
DGND
ANALOGCIRCUITRY
DIGITALCIRCUITRY
Grounding ADCs & DACs
A PHILOSOPHICAL PROBLEM!
AGND and DGND should bothbe connected to the analogground plane of the system
The pin description DGND doesNOT imply that this pin shouldgo to the system digital ground
Systemanalogground
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Grounding ADCs & DACs
WHY NOT USE ONE PIN?At high current or high frequency the
impedance of the converter leadsprevents the use of a single ground pin
Low current/low frequency convertersoften do have just one
CONVERTER
AGND DGND
LEAD IMPEDANCES
DIGITALCIRCUITRY
ANALOGCIRCUITRY
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Grounding ADCs & DACs
SO WHY MUST THEY BEJOINED AT THE PACKAGE?
Ground noise at X can affect theanalog circuitry of the converter
via stray capacitances
This noise can be minimisedby minimising the impedancebetween DGND, AGND and the
system analog ground
CONVERTER
AGND DGND
XSTRAYCAPACITANCE
DIGITALCIRCUITRY
ANALOGCIRCUITRY
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Grounding ADCs & DACs
SUPPLY DECOUPLINGThe supply to the digital part of theconverter must be decoupled to the
DGND pin with a low inductancecapacitor having minimum possible
lead and PC track impedance
Digital VDD may be fed from thesystem analog or digital supplies,but should be isolated by a small
impedance in either case
AGND
CONVERTERAnalogVdd
DigitalVdd
ANALOGCIRCUITRY
DIGITALCIRCUITRY
DGND
Analog ordigital supply
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Grounding ADCs & DACs
GROUND RETURN CURRENT
The only current which flowsbetween Analog and digital
system grounds is the returncurrent of the digital interfaces
AGND
CONVERTER
DGND
DIGITALCIRCUITRY
SYSTEMANALOGGROUND
SYSTEMDIGITALGROUND
CIRCULATINGDIGITALCURRENTS
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Grounding ADCs & DACs
BEWARE OF THE BUS!NEVER connect a major data bus
directly to an ADC or DAC
It is a source of noise and mostADCs cannot drive the load
AGND
CONVERTER
DGND
SYSTEMANALOGGROUND
MAJORDATA BUS
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Grounding ADCs & DACs
BUFFER ITPut a buffer between a
data bus and a converter
Even if the converter hasan internal buffer
It minimisesnoise feedthrough
And may improve ADCaccuracy by lowering
power dissipation
AGND
CONVERTER
DGND
SYSTEMANALOGGROUND
SYSTEMDIGITALGROUND
BUFFERBETWEENCONVERTER&ACTIVEOR LOWIMPEDANCEDATA BUS
MINIMALCIRCULATINGDIGITALCURRENTS
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Grounding ADCs & DACs
SLOW DOWN!(If you can)
Fast logic edges at aconverter’s digital portsare a source of noise
Slowing them down withRC networks canreduce this noise
But system timing maynot allow it – take care
AGND
CONVERTER
DGND
SYSTEMANALOGGROUND
R
R
C
C
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Grounding ADCs & DACs
SAMPLINGCLOCKS
In order to minimise phasenoise (jitter), which can
devastate the performanceof a sampled data system,
the sampling clock oscillatorshould be built on the system
analog ground
AGND
CONVERTER
DGND
SYSTEMANALOGGROUND
SAMPLINGCLOCKGENERATOR
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MicroConverter®ANALOGCIRCUITRY
DIGITALCIRCUITRY
AGND DGND
8052MICROCONTROLLER
Grounding ADCs & DACs
THIS GROUNDING SCHEMEIS ALMOST UNIVERSAL
If a converter contains nocomputation, or draws lessthan 30mA supply currentit should use this scheme
If the data sheet suggestsotherwise the data sheet is
probably incorrect
Even the MicroConverter® should be grounded this way System
analogground
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Grounding ADCs & DACsANALOGCIRCUITRY
DIGITALCIRCUITRY
AGND DGND
BIG DSP with CODEC
DSPPROCESSOR
Systemanalogground
Systemdigitalground
BIG DSP DEVICESWITH CODECS
AREAN EXCEPTION
These devices have high(>100 mA) transient current
on DGND and are usuallydesigned to have goodnoise isolation between DGND and the analog
circuitry – they should have DGND and AGND separately
grounded unless thedata sheet says otherwise
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Grounding ADCs & DACs
If in doubt – join AGND & DGND
and connect them tosystem analog ground
a
System AGND & DGND
Sometimes it is not possible to reducecommon-mode ground noise to a levelcompatible with the noise immunity of
ADCs and the digital circuitry that they drive
In the past this problem was solved byoptical isolators – today there is a faster
cheaper and lower-powered solutionusing surface micromachine technology
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Introducing iCoupler Technology
Magnetic RatherThan Optical Transmission
High-Fidelity Galvanic Isolation Performance, Power, and Cost
Improvements Over Optocouplers
Magnetic RatherThan Optical Transmission
High-Fidelity Galvanic Isolation Performance, Power, and Cost
Improvements Over Optocouplers
ADuM1100 Digital Isolator
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Magnetic-Based Isolation Technology
Standard CMOS Driver and Receiver Circuits iCoupler Channels Integrated Easily With Other
Semiconductor Circuits Optocoupler Mechanical and Electrical Limitations
Eliminated
Driver Chip Receiver Chip
Driver
IN OUT
Semiconductor Top Metal Coil
Insulation LayerChip-to-ChipBond Wires
Receiver
Micromachined Low Loss Coil
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ADuM1100 Receiver Chip
CMOS Circuitry
-- Insulation --
MEMS Coil
Coil/Insulation Cross-Section
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iCoupler Product Offerings to Provide Performance and Integration Benefits
Performance Benefits:
iCoupler
Technology
Optocoupler Technology
Max. Data Rate (MBd, min.)
100 25
Prop. Delay (ns, max.)
18 40
Pulse Width Distortion (ns, max.)
2 8
Trans. Immunity (kV/s, min.)
25 10
Power @25 MBd (mW, max.)
23 105
Integration Benefits:
Multi-Channel:
Multi-Function:
OptocouplerSolution
µmIsolationSolution
µmIsolationSolution
OptocouplerSolution
ADC optos Isolated ADC
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GROUND PLANES
One entire side or layer of a PCB is continuous grounded conductor.
This gives minimum ground resistance and inductance but is not always sufficient to solve all grounding problems.
Breaks in ground planes can improve or degrade circuit performance — there is no general rule.
Twenty years ago ground planes were difficult to fabricate. Today they are not.
If your PCB facility objects to fabricating ground planes — GET A NEW PCB FACILITY!
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A SLIT IN THE GROUND PLANE CAN RECONFIGURE CURRENT FLOW FOR BETTER ACCURACY
a
MICROSTRIP TRANSMISSION LINE
DIELECTRIC
GROUND PLANE
CONDUCTOR
wh
o377h
Z = ohms
rw E
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BREAKS IN GROUND PLANE RAISE RESISTANCE
VIEW FROMCONDUCTORSIDE OF PCB
BREAK IN GROUND PLANE
CROSSOVER ONGROUND PLANE SIDE
SIGNALCURRENT A
SIGNAL CURRENT B
RETURN CURRENT ADIVERTS AROUND BREAKIN GROUND PLANERAISING INDUCTANCE
RETURN CURRENT BDIVERTS AROUNDBREAK IN GROUNDPLANE RAISINGINDUCTANCE
RETURN CURRENTS A AND B MAY INTERACT
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DIFFERENTIAL TRANSMISSIONMINIMIZES GROUND ERRORS
ONE CARD ANOTHER CARD
SIGNALYOUWANT
WHEREYOUWANT IT
DIFFERENTIAL SIGNAL
RECEIVER:DIFFERENTIAL
TO
SINGLE-ENDED,HIGH C.M.R.R.
GROUND NOISE
At DC and LF the receiver will be an instrumentation amplifier
At HF the receiver will be a transformer
There is no ideal receiver for video signals which have components from DC to HF
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POWER SUPPLY NOISE
Long-term variation (Long-term variations in voltage or AC line voltage)
AC Line noise (Both 100/120 Hz ripple on rectifier output and transient noise on the AC line which passes to the DC output)
Switching Noise (Digital noise from switching-mode power supplies)
Power line noise transfer (Unwanted signals which pass from one part of a circuit to another via the common power supply)
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SWITCHING-MODE POWER SUPPLIES
Generate every imaginable type of noise and some inconceivable ones as well
DO NOT USE THEM WHERE NOISE IS IMPORTANT
If their use is unavoidable, do not relax and enjoy it, but take extreme precautions against all forms of noise
Remember that a manufacturer’s design change in a bought-in switching mode power supply may alter its effects on your system noise without altering its published specification.
When developing a system using a switching mode supply, it is instructive and often frightening to temporarily replace the switching supply with a battery or a linear supply and to remeasure the system noise!
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ELECTROMAGNETIC NOISE GENERATION
Circuits must be designed so that external E/M fields are minimized.
This is done by shielding, decoupling, minimizing the area of HF current loops, and designing circuits which generate as little EMI as possible.
IT’S NOT JUST A GOOD IDEA
IT’S THE LAW!!
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ELECTROMAGNETIC NOISE INTERFERENCE
The world is full of radio transmitters.
Police, taxis, broadcast, amateur, CB, cellular and cordless telephones, telemetry, and garage door openers.
Do not imagine that your circuit will never encounter one!
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EMI PREVENTION
PCB
FERRITEBEAD
INTEGRATEDPI-FILTER
SINGLE CERAMIC CAPACITOR
FERRITE BEAD AND CAPACITOR
INTEGRATED PI-FILTER
WHERE HIGH E-M FIELDS ARE ENCOUNTERED,CIRCUITRY SHOULD BE SCREENED BY AGROUNDED CONDUCTING ENCLOSURE
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Clock Noise in Sampled Data Systems
Input signal
Sampling clock
Samples
Sampled Data System
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Clock Noise in Sampled Data Systems
Basic Sampled Data Systemconsists of an ADC and a DSP
Both require clocks, which may or may not be synchronised to each other – but using the clock oscillator in the DSP to
drive the ADC can cause severe problems
ADC DSP
Clock
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Clock Noise in Sampled Data Systems
Clock timing errors (jitter) produce amplitude errors
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Clock Noise in Sampled Data Systems100pS
10pS
1nS
10nS
100nS
20-Bit
16-Bit
12-Bit
8-Bit
4-Bit
ENOB
10KHz 30KHz 100KHz 1MHz300KHz
120
100
80
40
20
0
60
SNR(dB)
FULLSCALE SINEWAVE INPUT FREQUENCY
j10 ft2
1log20SNR
SNR & ENOB vs tj
for various input frequencies
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Clock Noise in Sampled Data Systems
SOURCES OF JITTERJitter in the converter and its SHA
The sampling clock generator itself
The signal route from the clock to the converter(s)
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Clock Noise in Sampled Data Systems
SOURCES OF JITTERJitter in the converter and its SHA
The sampling clock generator itself
The signal route from the clock to the converter(s)
Twenty years ago one of the most important specifications of a sample and hold circuit (SHA) was its jitter, today, although jitter is still as important as ever, the circuitry used in SHAs and converters has
improved so much that circuit jitter is rarely a problem, although jitter due to power supply noise can still occur when decoupling is
inadequate
You should still check the data sheet carefully for this specification!
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Clock Noise in Sampled Data Systems
SOURCES OF JITTERJitter in the converter and its SHA
The sampling clock generator itself
The signal route from the clock to the converter(s)
There are two types of clock generator with poor phase noise:-
Oscillator circuits which are intrinsically noisy
Low-noise oscillators which have been affected by interference
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Clock Noise in Sampled Data Systems
Vref
V+
Relaxation Oscillators(such as the well-known 555)
are vulnerable to noise, which causes their threshold circuit to operate early or late and thus
causes jitter
Do not use themas sampling clocks
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Clock Noise in Sampled Data Systems
Phase-shift & tuned-circuit oscillatorsare much more stable, and the ones using
LC tuned circuits have higher Q, and thereforeless phase noise, than ones with RC networks
But both sorts can be used as sampling clocks
Resonant (LC) orphase-shift (RC)
circuitry
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Clock Noise in Sampled Data Systems
V+A Crystal Oscillatoris a resonant oscillator using a quartz crystal, which has a Q of many thousand, as a resonator
This results in better phase noise
They may be built with ICs but a single bipolar transistor or FET may give better performance
than an IC
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Clock Noise in Sampled Data SystemsA Crystal Oscillator
built with logic gates is not nearly such a good oscillator as a
purpose-built one
Especially if other gates on the same chip are handling high-
speed digital signals which are not synchronous with the
oscillator – cross-talk in such a case can cause very bad phase
noise
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Clock Noise in Sampled Data Systems
Power Line Interference
Any Crystal Oscillatormust have its power supply adequately decoupled lest
power line noise causesevere phase modulation
This is a very common causeof poor oscillator performanceand great care is needed to
avoid it
V (Plus noise!)
OSCILLATOR
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Clock Noise in Sampled Data Systems
SOURCES OF JITTERJitter in the converter and its SHA
The sampling clock generator itself
The signal route from the clock to the converter(s)
As the sampling clock goes from the clock oscillatorto the ADC/SHA it can be affected by two noise sources:-
Cross-talk from other digital lines
Common-mode noise between analog and digital ground
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Clock Noise in Sampled Data Systems
RETURN
RETURN
RETURN
RETURN
RETURN
RETURN
SIGNAL 1
SIGNAL 2
SIGNAL 3
SIGNAL 4
SIGNAL 5
SIGNAL 1
SIGNAL 2
SIGNAL 3
SIGNAL 4
SIGNAL 5
SIGNAL 6
SIGNAL 7
SIGNAL 8
RETURN
Crosstalk between linesDigital signal lines couple capacitively and magnetically if they run in parallel
Because of logic noise immunity this is not too serious for most digital signals (unless the lines are too long) but it isa problem for analog signals – and for
sampling clocks
A ground return path between each signal line and the next minimises
this effect at the cost of an increasein board area
A better solution for a sampling clockis to run the line well away from all
other digital signals
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Clock Noise in Sampled Data Systems
CLOCK ADC
Ground
Noise
Ground noise
(Internal) Clock with Jitter
Clock
(Internal) Clock
Clock + Ground noise
ADC ClockThresholdLevel
WITHGROUNDNOISE
WITHOUTGROUNDNOISE
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Clock Noise in Sampled Data SystemsCLOCK ADC
GroundNoise
CLOCK ADC
Ground Noise
The best way to eliminatejitter caused by ground
noise is to put the sampling clock on the system analog
ground
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Clock Noise in Sampled Data Systems
Ground Noise
Other ways to eliminatejitter caused by ground
noise include minimising common-mode noise bythe use of a transformeror a differential amplifier
CLOCK ADC
CLOCK ADC
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Clock Noise in Sampled Data Systems
Noisy External Clock
If a sampled data system must be operated with an externally-provided clock which has intolerable amounts of jitter it is possible to
remove the jitter by reconstructing the clock signal with a carefully designed PLL
PLL ADCCleaned-upClock
External Clockwith Jitter
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HIGH SPEED LINEAR DESIGN SEMINAR
EurIng James M. Bryant – Head of European Applications
(+44) 7785-305598
james.bryant@analog.com
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