2015/9/12Digital Circuit IC Design1 數位電路晶片設計及實習講義...

112/04/19 Digital Circuit IC Design 1

數位電路晶片設計及實習講義數位電路晶片設計及實習講義

半導體學院半導體學院數位電路設計人才培訓班數位電路設計人才培訓班

郭英哲編撰郭英哲編撰國立勤益技術學院電機系

92.10.12

數位電路晶片設計及實習數位電路晶片設計及實習• 授課教師：郭英哲 (04-23924505 ext:7271)

kuoyc@chinyi.ncit.edu.tw• 上課時數： 2 堂正課、 2 堂實習，計 3 學分。• 開課學期：四技一下選、在職二技一下選、進推部二技選• Text Book ：

J. Bhasker, “A VHDL Primer 3/e,” Prentic-Hall, 1999蕭如宣，蕭如宣， VHDLVHDL 數位電路設計，儒林出版，數位電路設計，儒林出版， SIM-829SIM-829

• Reference Book ：李宜達，數位邏輯電路設計與模擬 --- 使用 AHDL/VHDL ，全華出版唐佩忠， VHDL 與數位邏輯設計，高立出版 108328盧毅， VHDL 與數位電路設計，文魁出版 T0278林明權，數位控制系統設計 --- 使用 VHDL ，全華出版 05066

數位電路晶片設計及實習數位電路晶片設計及實習• 實習設備： 24 套

– P-4 2.4GHz PC– ALTERA 公司 (www.altera.com) MAX+Plus–II Baseline 設計軟體– 力浦電子 (www.leap.com.tw) LP-2900 實驗板一組 ( 含變壓器及 25-pin printer port

cable)

• 上課內容：– 晶片設計資源介紹– ALTERA MAX+Plus – II 設計軟體介紹– Schematic design – VHDL syntax– 組合邏輯電路設計– 序向邏輯電路設計– 期末專題

• 計分方式：– 平時 50% ( 有 5 次實驗，每個實驗 10%) – 期末專題 20%– 期末術科考試 30%

Using fixed function ICsUsing fixed function ICs

IC design approachIC design approach

Introduction Introduction passive components(1/2)passive components(1/2)

Introduction Introduction passive components(2/2)passive components(2/2)

Introduction Introduction IC and VLSIIC and VLSI

IntroductionIntroductionIC design methnologiesIC design methnologies

Active ComponentsActive Componentslogic Gates(1/12)logic Gates(1/12)

VHDL syntax

Y <= not A ;Y <= not A ;

VHDL syntax

Y <= A ;Y <= A ;

VHDL syntax

Y <= A nand B ;Y <= A nand B ;

VHDL syntax

Y <= A nor B ;Y <= A nor B ;

VHDL syntax

Y <= A xor B ;Y <= A xor B ;

Active ComponentsActive ComponentsCombinational CircuitCombinational Circuit

Active ComponentsActive Componentsexample of tri-state bufferexample of tri-state buffer

Active ComponentsActive Componentssequential Circuitsequential Circuit

Programmable Logic DeviceProgrammable Logic Device

• PROM: Programmable ROM• PLA : Programmable Logic Array• PAL: Programmable Array Logic• PEEL: Programmable Electrically Erasable Array• FPGA: Field Programmable Gate Array

PROMPROM

• AND 部份不可以規劃• OR 部份可以規劃

get symbolget symbol (schematic)(schematic)

• Symbol \ Enter symbol (or double-click)

AND2AND2

OR3OR3

INPUTINPUT

VCCVCC

DFFDFF

OUTPUTOUTPUT

4-bit asynchronous (4-bit asynchronous ( 非同步非同步 )ripple down-)ripple down-countercounter

(schematic)(schematic)

Steps of simulationSteps of simulation(schematic)(schematic)

• File / New / Waveform Editor File

• Node / Enter Nodes from SNF…

• Right-click / Enter Nodes from SNF…

Steps of simulationSteps of simulationend time / grid sizeend time / grid size

• File / End time– 延長模擬時間

• Options / grid size– 設定最小時間刻度

Steps of simulationSteps of simulationend time / grid sizeend time / grid size

Result of simulationResult of simulation

DelayDelay 會累會累加加

4-bit synchronous(4-bit synchronous( 同步同步 ) up-counter) up-counter

不會有 Delay 累積

Create user symbolCreate user symbol

Create symbolCreate symbol

Create user symbolCreate user symbol

• \File \Create Default Symbol

Create Default SymbolCreate Default Symbol

Create user libraryCreate user library

• step 1 : Options / User Libraries

Create user libraryCreate user library

• step 2 : assign the library directory

• step 3 : 將 xxx.gdf (schematic) 、 xxx.tdf (AHDL) 、xxx.vhd (VHDL) 、 xxx.sym (symbol) 等檔案 copy 至此 user libraries 目錄下

QuizQuiz

• Down counter ( 下數 ) → Up counter ( 上數 ) • Asynchronous ( 非同步 ) → Synchronous ( 同步 )

mod-10 (BCD) up-countermod-10 (BCD) up-counter

2-digit mod-10 up-counter2-digit mod-10 up-counter

個位數

拾位數

2-digit mod-10 up-counter2-digit mod-10 up-counter

實驗進度實驗進度

• Counter (falling-/rising-edge trigger, sync/ripple)– 4-/8-bit, mod-10/mod-12– 2-digit mod-10 up-counter

• 除頻電路 – 除 2/4/8/16/../2n, 50% duty-cycle– 除 10 ( 偶數 ), 50% duty-cycle ( 責任周期 )– 除 13 ( 奇數 ), 50% duty-cycle

mod-10 (BCD) up-countermod-10 (BCD) up-counterfor divide-10for divide-10

除除 22 波形波形

除除 22xx yy

P.S. 任何波形除 2 後會對稱

Disbounce circuitDisbounce circuit(schematic)(schematic)

INV_KEY

simulation result under 200ns clock ratesimulation result under 200ns clock rate

simulation result under 100ns clock ratesimulation result under 100ns clock rate

Conclusion of DISBOUNCE circuitConclusion of DISBOUNCE circuit

• clock 的 frequency 會對 disbounce 效果有所影響– clock 快按鍵較靈敏， disbounce 效果較差– clock 慢按鍵較遲鈍， disbounce 效果良好

• P.S. clock generator :• Crystal 石英晶體• Oscillator (O.S.C) 振盪器

Implementation of LED exampleImplementation of LED example

4-bitUp counter

Dis-bounce除 10000

O.S.C10MHz

實驗設備實驗設備 LP-2900(LP-2900( 力浦公司力浦公司 ))

實驗設備實驗設備 LP-2900(LP-2900( 力浦公司力浦公司 ))Altera FLEX10K family deviceAltera FLEX10K family device

EPF10K10TC144-4EPF10K10TC144-4

• 指定 IC\Assign \Device\

ALTERA FLEX 10K devicesALTERA FLEX 10K devices

Quad PackageQuad Package

• Quad Package family includes – QFP : Quad Flat Pack– LQFP : Low-profile Quad Flat Pack– TQFP : Thin Quad Flat PackTQFP : Thin Quad Flat Pack

• All of the Quad Packages are with Gullwing lead. With the same QFP outline, thermally enhanced QFP provides better thermal performance. LQFP (body thickness 1.4 mm) and TQFP (body thickness 1.0 mm) with reduced thickness are offered to meet thin profile requirement. Thermally enhanced structures are also applicable in LQFP and TQFP to improve the thermal performance.

• 封測廠封測廠 : : 矽品矽品 www.spil.com.tw• 日月光日月光 www.asecl.com.tw

TQFPTQFP

Configuration EPROMsConfiguration EPROMs

Appropriate configuration EPROM Appropriate configuration EPROM for each FLEX devicefor each FLEX device

EPC1 & EPC1V pin function during EPC1 & EPC1V pin function during FLEX 10K device configurationFLEX 10K device configuration

腳位配置腳位配置 floorplanfloorplan

• 腳位配置 floorplan(1) \Maxplus II \Floorplan Editor\

(2) \Layout\ Current Assignments Floorplan

Device programmingDevice programming

晶片規劃晶片規劃 programmingprogramming(1) \Maxplus II \ Programmer

(2) \Options \ Hardware Setup

Byte Blaster(MV), LPT1

(3) \JTAG \ Multi-Device JTAG Chain Setup

HDLHDL 硬體描述語言硬體描述語言

• HDL : Hardware Description Language– VHDL– Verilog HDL– AHDL (for Altera)– ABEL-HDL (for Xilinx and Lattice)

Introduction to VHDLIntroduction to VHDL

VHDLVHDL ： VVery High Speed Integrated Circuit HHardware DDescription LLanguage

1970-1980 美國國防部開始發展VHDL 成為 IEEE 制定的標準，稱為 IEEE 1076

IEEE : Institute of Electrical and Electronics Engineer, 電機暨電子工程師學會修改為 IEEE 1164將電路合成的程式標準與規格加入到 VHDL 電路設計語言中，稱之為 IEEE 1076.3

VHDLVHDL 可依據的標準：可依據的標準： (1) std_logic_1164 ： std_logic 、 std_logic_vector

follow IEEE std 1164-1993(2) standard ： bit 、 bit_vector

follow IEEE std 1076-1987(3) std_logic_arith ： signed 、 unsigned

MAX+Plus II VHDL on-line helpMAX+Plus II VHDL on-line helpmenu \ help \ VHDL \ VHDL 1993 syntaxmenu \ help \ VHDL \ VHDL 1993 syntaxwww.altera.comwww.altera.com

VHDLVHDL 基本語法架構：基本語法架構：

library ieee;library ieee; -- library declaration-- library declarationuse ieee.std_logic_1164.all ;use ieee.std_logic_1164.all ; -- used package, IEEE standard-- used package, IEEE standard

entityentity 單體名稱單體名稱 isisport (port ( 訊號訊號 AA : : 模式模式資料型別資料型別 ;;

訊號訊號 BB : : 模式模式資料型別資料型別 ;;…………

訊號訊號 NN : : 模式模式資料型別資料型別 ) ;) ;endend 單體名稱單體名稱 ;;

architecturearchitecture 架構名稱架構名稱 ofof 單體名稱單體名稱 isis{ { 架構之宣告區架構之宣告區 }}

beginbegin{ { 電路描述電路描述……

…….... } }endend 架構名稱架構名稱 ;;P.S. portP.S. port 的模式共定義了四種的模式共定義了四種 inin 、、 outout 、、 bufferbuffer 、、 inoutinout 。。

entity entity 宣告宣告

entityentity 單體名稱單體名稱 isisport (port ( 訊號訊號 AA : : 模式模式資料型別資料型別 ;;

訊號訊號 BB : : 模式模式資料型別資料型別 ;;…………

訊號訊號 NN : : 模式模式資料型別資料型別 ) ;) ;endend 單體名稱單體名稱 ;;

--------------------------------------------------------------

entity up_cnt4 isport(

CLK : in bit ;QD : out bit_vector(3 downto 0));

end up_cnt4;

與儲存檔名相同

識別字識別字 identifieridentifier

• 第一個字必須為英文字母• 最後一個字不可以為底線 ” _”• 不可以連續兩個底線 ” __”• 不可以為保留字 (reversed word)

– and, or, not, if, else, in, out, is, case, for, function…

• 可以是英文大寫 (A ～ Z) 、英文小寫 (a ～ z) 、數字 (0 ～ 9) 或者底線 ” _”

• 不分大小寫

保留字保留字 reserved word reserved word (1/2)(1/2)

ABSABS ACCESSACCESS AFTERAFTER ALIASALIAS ALLALL

ANDAND ARCHITECTUREARCHITECTURE ARRAYARRAY ASSERTASSERT ATTRIBUTEATTRIBUTE

BEGINBEGIN BLOCKBLOCK BODYBODY BUFFERBUFFER BUSBUS

CASECASE COMPONENTCOMPONENT CONFIGURATIOCONFIGURATIONN

CONSTANTCONSTANT DISCONNECTDISCONNECT

DOWNTODOWNTO ELSEELSE ELSIFELSIF ENDEND ENTITYENTITY

EXITEXIT FILEFILE FORFOR FUNCTIONFUNCTION GENERATEGENERATE

GENERICGENERIC GROUPGROUP GUARDEDGUARDED IFIF IMPUREIMPURE

ININ INERTIALINERTIAL INOUTINOUT ISIS LABELLABEL

LIBRARYLIBRARY LINKAGELINKAGE LITERALLITERAL LOOPLOOP MAPMAP

MODMOD NANDNAND NEWNEW NEXTNEXT NORNOR

NOTNOT NULLNULL OFOF ONON OPENOPEN

保留字保留字 reserved word reserved word (2/2)(2/2)

OROR OTHERSOTHERS OUTOUT PACKAGEPACKAGE PORTPORT

POSTPONEDPOSTPONED PROCEDUREPROCEDURE PROCESSPROCESS PUREPURE RANGERANGE

RECORDRECORD REGISTERREGISTER REJECTREJECT REMREM REPORTREPORT

RETURNRETURN ROLROL RORROR SELECTSELECT SEVERITYSEVERITY

SIGNALSIGNAL SHAREDSHARED SLASLA SLLSLL SRASRA

SRLSRL SUBTYPESUBTYPE THENTHEN TOTO TRANSPORTTRANSPORT

TYPETYPE UNAFFECTEDUNAFFECTED UNITSUNITS UNTILUNTIL USEUSE

VARIABLEVARIABLE WAITWAIT WHENWHEN WHILEWHILE WITHWITH

XNORXNOR XORXOR

port port 模式模式

• in– 輸入模式

• out– 輸出模式– 不可以回授到單體內部

• buffer– 可以將訊號回授到單體內部的輸出模式– 不能有多重驅動– 只能回授至單體內部或其他同為 buffer 的單體– 不可以接到其他單體電路的輸出 (out) 或雙向 (inout) 的接腳

上• inout

– 同時具有 in 、 out 、 buffer 三種工作模式

port port 模式模式

port port 資料型別資料型別

• type bitbit is ( ‘0’, ‘1’‘0’, ‘1’ ) ;

• type std_ulogicstd_ulogic is ( ‘U’,‘U’, -- uninitialized, 未設定‘‘X’,X’, -- forcing unknown, 浮接不定‘‘0’,0’, -- forcing 0, ‘0’ 電位‘‘1’,1’, -- forcing 1, ‘1’ 電位‘‘Z’,Z’, -- high impedance, 高阻抗‘‘W’,W’, -- weak unknown, 弱浮接‘‘L’,L’, -- weak 0, 弱低電位‘‘H’,H’, -- weak 1, 弱高電位‘‘-’,-’, -- don’t care, 無在意

);• Another types : bit_vector, std_ulogic_vector, std_logic, bit_vector, std_ulogic_vector, std_logic,

std_logic_vectorstd_logic_vector

port port 資料型別資料型別

std_logic std_logic 資料型別資料型別

• Subtype std_logic is resolved std_uulogic– 少了 ’ -’– 電位適當轉換 , 參考 IEEE std_logic_1164 package– 常用 ‘ 0’, ‘1’, ‘z’

Architecture bodyArchitecture bodystructure style of modelingstructure style of modeling

• In the structural style of modeling, an entity is described as a set of a set of interconnected componentsinterconnected components.

architecture 架構名稱 of 單體名稱 is declaration part 宣告區

componentcomponent declaration;signalsignal declaration;constantconstant declaration;

beginstatement part 敘述區

the interconnection of components;

end 架構名稱 ;

P.S. Signals, which represent wireswires, are used to connect the various components.

Architecture bodyArchitecture body

• 結構描述結構描述 Structure Description– As a set of interconnected components (to represent structure)

• 資料流描述資料流描述 Data Flow Description– As a set of concurrentconcurrent assignment statements (to represent

dataflow)

• 行為描述行為描述 Behavior Description– As a set of sequentialsequential assignment statements (to represent

behavior)

• As any of combination of the above three

• 結構描述結構描述 Structure DescriptionStructure Description– As a set of interconnected components (to represent structure)

• 資料流描述 Data Flow Description– As a set of concurrentconcurrent assignment statements (to represent

dataflow)

• 行為描述 Behavior Description– As a set of sequentialsequential assignment statements (to represent

behavior)

Architecture bodyArchitecture bodystructure style of modeling structure style of modeling 結構描述結構描述

entity HALF_ADDER isport ( A, B : in bit;

SUM, CARRY : out bit ) ;end HALF_ADDER;

architecture HA_STRUCTURE of HALF_ADDER iscomponentcomponent AAA

port ( X, Y : in bit; Z : out bit );

end componentend component;componentcomponent BBB port ( L, M : in bit;

N : out bit );end componentend component;

beginU1 : AAA port map (A, B, SUM);

-- (X=>A, Y=>B, Z=>SUM);

U2 : BBB port map (A, B, CARRY); -- (L=>A, M=>B, N=>CARRY);

end HA_STRUCTURE ;

U3 : AAA port map(C, D, F) ;

library ieee;

use ieee.std_logic_1164.all ;

entity DECORDER2x4 is

port ( A, B, ENABLE : in bit ;

Z : out bit_vector (3 downto 0)

); -- (0 to 3)

end DECORDER2x4 ;

DECODER2x4

ENABLEENABLE

Z(3)Z(3)Z(2)Z(2)Z(1)Z(1)

Z(0)Z(0)

P.S. -- 註解

architecture DEC_STR of DECORDER2x4 iscomponent INV

port ( PIN : in bit; POUT : out bit );end component;component NAND3

port ( D0, D1, D2 : in bit;DZ : out bit );

end component;signalsignal ABAR, BBAR : bit;

beginI0 : INV port map (A, ABAR);I1 : INV port map (B, BBAR);N0 : NAND3 port map ( ENABLE, ABAR, BBAR, Z(0));N1 : NAND3 port map (ABAR, B, ENABLE, Z(1));N2 : NAND3 port map (A, BBAR, ENABLE, Z(2));N3 : NAND3 port map (A, B, ENABLE, Z(3));

end DEC_STR ;

硬體內部元件的實際接線

訊號的連結訊號的連結 (1/2)(1/2)

• signal Z : bit_vector (3 downto 0);• signal A : bit_vector (3 downto 0);• signal B : bit_vector (0 to 3);• Signal O,P,Q,R : bit ;

• A <= Z;A <= Z; B <= Z;B <= Z;

• A <= (O,P,Q,R);A <= (O,P,Q,R); or A <= O&P&Q&R;A <= O&P&Q&R; -- & 連結運算子

Z(3)Z(2)Z(1)Z(0)

A(3)A(2)A(1)A(0)

Z(3)Z(2)Z(1)Z(0)

B(0)B(1)B(2)B(3)

A(3)A(2)A(1)A(0)

訊號的連結訊號的連結 (2/2)(2/2)

• signal Z : bit_vector (3 downto 0);• signal A : bit_vector (3 downto 0);• signal B : bit_vector (0 to 3);• Signal O,P,Q,R : bit ;

• Z <= A and B;– Z(3) <= A(3) and B(0) ;

– Z(2) <= A(2) and B(1) ;

– Z(1) <= A(1) and B(2) ;

– Z(0) <= A(0) and B(3);

Architecture bodyArchitecture bodystructure style example structure style example 結構描述結構描述

4-bitUp counter

Dis-bounce除 10000

(O.S.C10MHz)

LED(3)LED(2)LED(1)LED(0)

VHDL for LED exampleVHDL for LED example

library ieee;use ieee.std_logic_1164.all;

entity LED_EXAMPLE isport ( KEYIN, CLOCK : in bit;

LED : out bit_vector(3 downto 0);LED_COM : out bit );

end LED_EXAMPLE;

architecture A_STRUCTURE of LED_EXAMPLE iscomponent DIV10000

port ( CLKIN : in bit;CLKOUT : out bit );

end component;component DISBOUNCE

port ( CLOCK, KEYIN : in bit;KEYOUT : out bit );

end component;component UP_CNT4

port ( CLK : in bit;QD : out bit_vector(3 downto 0) );

end component;signal CLK_DIV10000, KEY_DISBOUNCE : bit ;

BeginLED_COM <= ‘1’ ;U1 : DIV10000 port map (CLOCK, CLK_DIV10000);U2 : DISBOUNCE port map (CLK_DIV10000, KEYIN, KEY_DISBOUNCE);U3 : UP_CNT4 port map (KEY_DISBOUNCE, LED);

end A_STRUCTURE;

• 結構描述 Structure Description– As a set of interconnected components (to represent structure)

• 資料流描述資料流描述 Data Flow DescriptionData Flow Description– As a set of concurrentconcurrent assignment statements (to represent

dataflow)

• 行為描述 Behavior Description– As a set of sequentialsequential assignment statements (to represent

behavior)

Architecture bodyArchitecture bodydataflow style of modelingdataflow style of modeling

entity HALF_ADDER isport ( A, B : in bit;

SUM, CARRY : out bit );end HALF_ADDER;

architecture HA_CONCURRENT of HALF_ADDER isbegin

SUM <= A xor B after 8 ns;SUM <= A xor B after 8 ns;CARRY <= A and B after 4 ns;CARRY <= A and B after 4 ns;

end HA_CONCURRENT;

P.S. In a signal assignment statement, the symbol <=<= implies an assignment of a value to a signal.

Delay information is included in the signal assignment statements used after clause.

Simulation result of Half-AdderSimulation result of Half-Adder

A B CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

邏輯運算子邏輯運算子

• 七種邏輯運算子– AND / NAND– OR / NOR– XOR / XNOR– NOT

SUMCARRY

CARRY0

CARRY1

SUM1SUM2

CARRY2

Half Adder

CARRY SUM

Full Adder

CARRYi SUMi

Bi CARRYi-1

Half / Full AdderHalf / Full Adder

Simulation result of DECODER2x4Simulation result of DECODER2x4

Architecture bodyArchitecture bodydataflow style of modelingdataflow style of modeling

architecture DEC_DATAFLOW of DECODER2x4 is

signalsignal ABAR, BBAR : bit;

ABAR <= not A;

BBAR <= not B;

Z(3) <= not (A and B and ENABLE);

Z(2) <= not (A and BBAR and ENABLE);

Z(1) <= not (ABAR and B and ENABLE);

Z(0) <= not (ABAR and BBAR and ENABLE);

end DEC_DATAFLOW ;

Architecture body :Architecture body :dataflow style of modelingdataflow style of modeling

library ieee;

use ieee.std_logic_1164.all ;

entity DECORDER2x4 is

port ( A, B, ENABLE : in bit ;

Z : out bit_vector (3 downto 0)

); -- (0 to 3)

end DECORDER2x4 ;

DECODER2x4

ENABLEENABLE

Z(3)Z(3)Z(2)Z(2)Z(1)Z(1)

Z(0)Z(0)

P.S. -- 註解

TTL 74139 / 74138 decoderTTL 74139 / 74138 decoder解碼器解碼器

P.S. 必需使用 altera.maxplus.all altera.maxplus.all 的 library

Architecture body :Architecture body :dataflow style exampledataflow style example

INV_KEY

Q0 Q1KEYOUT

DFF1 DFF2VCC

VHDL for disbounce circuitVHDL for disbounce circuit

library library altera;altera;use use altera.maxplus2.all;altera.maxplus2.all;library ieee;use ieee.std_logic_1164.all;

entity DISBOUNCE isport (

KEYIN, CLOCK : in std_logic; KEYOUT : out std_logic);

end DISBOUNCE;

architecture A of DISBOUNCE issignal VCC, INV_KEY : std_logic ;

signal Q0, Q1 : std_logic ; begin VCC <= '1' ; INV_KEY <= not KEYIN ; DFF1 : DFFDFF port map (d =>VCC , q => Q0 , clk => CLOCK , clrn => INV_KEY , prn => VCC);

DFF2 : DFFDFF port map (d =>VCC , q => Q1 , clk => CLOCK , clrn => Q0 , prn =>VCC); KEYOUT <= not Q1 ;end A;

定義 DFF component

Architecture body :Architecture body :dataflow style exampledataflow style example

• 結構描述 Structure Description– As a set of interconnected components (to represent structure)

• 資料流描述資料流描述 Data Flow DescriptionData Flow Description– As a set of concurrentconcurrent assignment statements (to represent

dataflow)

• 行為描述行為描述 Behavior DescriptionBehavior Description– As a set of sequentialsequential assignment statements (to represent

behavior)

Architecture bodyArchitecture bodybehavioral style of modelingbehavioral style of modeling

[label :][label :] processprocess ( (sensitivity listsensitivity list))declaration partdeclaration part (before the keyword begin)(before the keyword begin)

beginbegin

statement partstatement part (between the keywords begin and end process)(between the keywords begin and end process)

end processend process [label][label] ; ;

P.S. P.S. (1) The behavior of an entity as a set of statements that are executed (1) The behavior of an entity as a set of statements that are executed sequentiallysequentially in the specified order. This set of sequential statements, in the specified order. This set of sequential statements, which are specified inside a process statement. which are specified inside a process statement.(2) The process statement is invoked whenever (2) The process statement is invoked whenever there is an event on any there is an event on any signal in the sensitivity list.signal in the sensitivity list.(3) The statements appearing within the process statement are executed (3) The statements appearing within the process statement are executed sequentially.sequentially.

[process-label:][process-label:] processprocess [(sensitivity list)] [is][(sensitivity list)] [is][process-item-declaration][process-item-declaration]

beginbeginSequential-statements; there are -->Sequential-statements; there are -->

variable-assignment-statementvariable-assignment-statementsignal-assignment-statementsignal-assignment-statementwait-statementwait-statementif-statementif-statementcase-statementcase-statementloop-statementloop-statementnull-statementnull-statementexit-statementexit-statementnext-statementnext-statementassertion-statementassertion-statementreport-statementreport-statementprocedure-statementprocedure-statementreturn-statementreturn-statement

end processend process [process-label];[process-label];

architecture DEC_SEQUENTIAL of DECORDER2x4 is

process (A, B, ENABLE)process (A, B, ENABLE)

beginbegin

if if ENABLE = ‘1’ thenthen

Z(0) <= not ((not B) and (not A) ) ; -- 00

Z(1) <= not ((not B) and A ) ; -- 01

Z(2) <= not (B and (not A)); -- 10

Z(3) <= not (B and A); -- 11

elseelse

Z <= “1111”;

end if;end if;

end process;end process;

end DEC_SEQUENTIAL ;

[process-label:][process-label:] process process [(sensitivity list)] [is][(sensitivity list)] [is][process-item-declaration][process-item-declaration]

variable-assignment-statementvariable-assignment-statementsignal-assignment-statementsignal-assignment-statementwait-statementwait-statement

if-statementif-statementcase-statementcase-statementloop-statementloop-statementnull-statementnull-statementexit-statementexit-statementnext-statementnext-statementassertion-statementassertion-statementreport-statementreport-statementprocedure-statementprocedure-statementreturn-statementreturn-statement

end process end process [process-label];[process-label];

if statementif statement

if if (boolean-expression) (boolean-expression) thenthensequential-statementssequential-statements

{ elsif { elsif (boolean-expression)(boolean-expression) then thensequential-statementssequential-statements } }

[else[elsesequential-statementssequential-statements]]

end if;end if;

Ex:Ex:if (X = ‘1’) then Y = A ;if (X = ‘1’) then Y = A ;elsif (X=‘0’) then Y = B ;elsif (X=‘0’) then Y = B ;elseelse Y = C ; Y = C ;end if; end if;

A level-sensitive flip-flop exampleA level-sensitive flip-flop example Type-D Flip Flop designType-D Flip Flop design

entity MY_DFF isport ( CLK, D : in bit;

Q : out bit );end MY_DFF;

architecture ARCH_DFF of MY_DFF isbegin

process (CLK)process (CLK)beginbegin

if (CLK’event and CLK = ‘1’)CLK’event and CLK = ‘1’) then Q <= D;end if ;

end process;end process;end ARCH_DFF ;

Level-sensitive

Mod-10 up-counterMod-10 up-counter

• level-trigger 準位觸發– high-level trigger

• clk = ‘1’clk = ‘1’

– low-level trigger• clk = ‘0’clk = ‘0’

• edge-trigger 邊緣觸發– rising-edge (positive-edge) trigger 正緣觸發

• clk’event and clk=‘1’clk’event and clk=‘1’

– falling-edge (negative-edge) trigger 負緣觸發• clk’event and clk=‘0’clk’event and clk=‘0’

A level-sensitive flip-flop exampleA level-sensitive flip-flop example Type-JK Flip Flop designType-JK Flip Flop design

entity MY_JKFF isport ( CLK, J, K, PRn, CLRn : in bit;

Q : out bit );end MY_JKFF;

architecture ARCH_DFF of MY_JKFF isbegin

process (CLK)process (CLK)beginbegin

if (CLK’event and CLK = ‘1’)CLK’event and CLK = ‘1’) then Q <= D;end if ;

end process;end process;end ARCH_DFF ;

Level-sensitive

Architecture bodyArchitecture bodymixed style of modelingmixed style of modeling

entity FULL_ADDER isport ( A, B, CIN : in bit; SUM, COUT : out bit);

end FULL_ADDER;

architecture FA_MIXED of FULL_ADDER iscomponent XOR2

port (P1, P2 : in bit; PZ : out bit);end component;signal S1 : bit;signal S1 : bit;

BeginX1 : XOR2 port map (A, B, S1);X1 : XOR2 port map (A, B, S1); -- structureprocess (A, B, CIN)process (A, B, CIN) -- behavior-- behavior

variable T1, T2, T3 : bit;variable T1, T2, T3 : bit;beginbegin

T1 := A and B;T1 := A and B;T2 := B and CIN;T2 := B and CIN;T3 := A and CIN;T3 := A and CIN;COUT <= T1 or T2 or T3;COUT <= T1 or T2 or T3;

end process;end process;SUM <= S1 xor CIN;SUM <= S1 xor CIN; -- dataflow-- dataflow

end LS_DFF ;

Mod-10 up-counterMod-10 up-counter

• library ieee;• use ieee.std_logic_1164.all;• entity UP_CNT4 is• port(• CLK : in bit;• Qd : out integer range 0 to 9 );• end UP_CNT4;

• architecture A of UP_CNT4 is• begin• -- An up counter• process (CLK)• variable CNT : integer range 0 to 9;• begin• if (CLK'event and CLK=’1’) then• if (CNT = 9) then CNT := 0;• else CNT := CNT + 1;• end if;• end if;• --Generate outputs• Qd <= CNT; • end process;• end A;

UP_CNT4

Simulation result of Mod-10 up-counterSimulation result of Mod-10 up-counter

wait untilwait until

process (CLK) variable CNT : integer range 0 to 9;begin

if (CNT = 9) then CNT := 0;else CNT := CNT + 1;

end if; Qd <= CNT;

wait untilwait until (CLK'event and CLK=’1’) ;end process;

除除 1010 電路電路

• library ieee ;• use ieee.std_logic_1164.all ;

• entity DIV10 is• port ( CLKIN : in std_logic ; • CLKOUT : out std_logic );• end DIV10 ;• architecture A of DIV10 is• begin• process (CLKIN) • variable CNT1: integer range 0 to 4 ; • variable CNT2: std_logic ; • begin• if (CLKIN'event and CLKIN='1') then• if (CNT1=4) then CNT1:= 0 ; • CNT2 := not CNT2 ; • else CNT1 := CNT1 +1 ; • end if ; • end if ; • CLKOUT <= CNT2 ; • end process ;• end A ;

CLKIN CLKOUT

除除 1010 電路模擬結果電路模擬結果

除除 10,000 10,000 電路電路• architecture A of MY_DIV10000 is• begin• process (CLKIN) • variable CNT1: integer range 0 to 9999 ; • variable CNT2: std_logic ; • begin• if (CLKIN'event and CLKIN='1') then• if (CNT1=9999) then CNT1:= 0 ; • else CNT1 := CNT1 +1 ; • end if ; • if (CNT1=5000 or CNT1=0)if (CNT1=5000 or CNT1=0) thenthen CNT2 := not CNT2;CNT2 := not CNT2;• end if;• end if ; • CLKOUT <= CNT2 ; • end process ;• end A ;

除除 10,000 10,000 電路電路

除除 5 5 電路電路

exerciseexercise

• clear=‘0’ QD(7:0) = 0;• load=‘1’ QD(7:0) = D(7:0)• up_down ‘0’ : down counter

‘1’ : up counter

Multi-features counterMulti-features counter

ENTITY counters IS PORT( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; load : IN BIT; up_down : IN BIT; qd : OUT INTEGER RANGE 0 TO 255);END counters;

ARCHITECTURE a OF counters ISBEGIN -- An up/down counter PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; VARIABLE direction : INTEGER; BEGIN IF (up_down = '1') THEN --Generate up/down counter direction := 1; ELSE direction := -1; END IF; IF (clk'EVENT AND clk = '1') THEN IF (load = '1') THEN --Generate loadable cnt := d; --counter. Take these ELSE --lines out to increase performance. cnt := cnt + direction; END IF; --The following lines will produce a synchronous --clear on the counter IF (clear = '0') THEN cnt := 0; END IF; END IF; qd <= cnt; --Generate outputs END PROCESS;END a;

七段顯示器七段顯示器

• CA : Common Anode, 共陽極– COM 接 VCC, low-active

• CC : Common Cathode, 共陰極– COM 接 GND, high-active

– P.S. 實驗板上的七段顯示器為共陰極。

BCD to 7-segment driver circuitBCD to 7-segment driver circuit

Input output

8 4 2 1 Dp g f e d c b a

0 0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 0 0 0 0 1 1 0 1

0 0 1 0 0 1 0 1 1 0 1 1 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9

1 0 1 0 A

1 0 1 1 B

1 1 0 0 C

1 1 0 1 D

1 1 1 0 E

1 1 1 1 F

BCD to 7-segment driver circuitBCD to 7-segment driver circuit

VHDL for Truth TableVHDL for Truth Tablelibrary ieee ;use ieee.std_logic_1164.all ;

entity SEG7SEG7 is port ( DIN : in std_logic_vector( 3 downto 0) ; SEGOUT : out std_logic_vector ( 6 downto 0) ) ;end SEG7SEG7 ;

architecture SEG7_CCSEG7_CC of SEG7SEG7 is signal signal Q : std_logic_vector ( 6 downto 0) ; -- =Q0= high-active -- Q5| |Q1 -- =Q6= -- Q4| |Q2 -- =Q3=

begin process (DIN) process (DIN) begin begin casecase DIN is when "0000" => Q <= "0111111" ; -- 0 when "0001" => Q <= "0000110" ; -- 1 when "0010" => Q <= "1011011" ; -- 2 when "0011" => Q <= "1001111" ; -- 3 when "0100" => Q <= "1100110" ; -- 4

VHDL for Truth TableVHDL for Truth Table

when "0101" => Q <= "1101101" ; -- 5 when "0110" => Q <= "1111101" ; -- 6 when "0111" => Q <= "0000111" ; -- 7 when "1000" => Q <= "1111111" ; -- 8 when "1001" => Q <= "1101111" ; -- 9 when "1010" => Q <= "1110111" ; -- A when "1011" => Q <= "1111100" ; -- B when "1100" => Q <= "0111001" ; -- C when "1101" => Q <= "1011110" ; -- D when "1110" => Q <= "1111001" ; -- E when "1111" => Q <= "1110001" ; -- F when OTHERS => Q <= "0000000" ; --very important end casecase; end process;end process; SEGOUT <= Q ;end SEG7_CCSEG7_CC ;

case syntax (1)case syntax (1)

case case 物件物件 isiswhen when 數值數值 11 => => 敘述敘述 11

when when 數值數值 11 => => 敘述敘述 22

......

when others => when others => 其他敘述其他敘述end caseend case

process (A, B, C, X)process (A, B, C, X)

beginbegin

case case XX is is

when when 0 to 40 to 4 => => Z <= A Z <= A ;;

when when 55 => => Z <= B Z <= B ; ; when when 7 | 97 | 9 => => Z Z <= C ; <= C ; when others when others => => Z <= 0 ; Z <= 0 ; end caseend case

end processend process

with … select… when syntax (1)with … select… when syntax (1)

with with 物件物件 isiswhen when 數值數值 11 => => 敘述敘述 11

......

when others => when others => 其他敘述其他敘述end caseend case

with with 選擇訊號選擇訊號 selectselect訊號訊號 X X <= <= 訊號訊號 A A when when 選擇訊號的值為選擇訊號的值為

P,P, 訊號訊號 A A when when 選擇訊號的值為選擇訊號的值為 P,P,

訊號訊號 A A when when 選擇訊號的值為選擇訊號的值為 P,P,

when when 數值數值 11 => => 敘述敘述 22when when 數值數值 11 => => 敘述敘述 33 ......when others => when others => 其他敘述其他敘述

end caseend case

一位數七段顯示器顯示一位數七段顯示器顯示

SEG7UP_CNT4disbouncediv1000 共陰極

一位數七段顯示器顯示一位數七段顯示器顯示

ABCDEFGdp

pin assignment

A B C D E F G dp DE1 DE2 DE323 26 27 28 29 30 31 32 33 36 37

DE1DE2DE3

OSC SW1 55 47

KEYINSW1

COM COMCOM

Function of 74138Function of 741383-8 decoder3-8 decoder

Input output

C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 00 1 1 1 1 1 1 1

0 0 1 1 00 1 1 1 1 1 1

0 1 0 1 1 00 1 1 1 1 1

0 1 1 1 1 1 00 1 1 1 1

1 0 0 1 1 1 1 00 1 1 1

1 0 1 1 1 1 1 1 00 1 1

1 1 0 1 1 1 1 1 1 00 1

1 1 1 1 1 1 1 1 1 1 00

多工器多工器 Multiplex (MUX)Multiplex (MUX)MUX 2x1MUX 2x1

• -- 2 to 1 multiplex• library ieee;• use ieee.std_logic_1164.all;

• entity MUX2x1 is• port ( A, B, SEL : in std_logic;• Y : out std_logic );• end MUX2x1;

• Architecture MUX2x1 of MUX2x1 is• begin• mux : process(A, B, SEL)• begin• if SEL=‘0‘ then Y <= A;• else Y <= B;• end if;• end process mux;• end MUX2x1 ;

Simulation result of MUX2x1Simulation result of MUX2x1

when…elsewhen…else MUX 2x1MUX 2x1

library ieee ;use ieee.std_logic_1164.all ;

entity MUX2x1 isport( A, B, SEL : in std_logic ;

Y : out std_logic) ;

end MUX2x1 ;

architecture MUX of MUX2x1 isbegin

Y <= A when SEL='0' else B ;end MUX ;

VHDL syntaxVHDL syntax when…elsewhen…else

• 單行敘述訊號 Y <= 訊號 A when 條件 else 訊號 B;

• 多行敘述訊號 Y <= 訊號 A when 條件 1 else

訊號 B when 條件 2 else׃

訊號 E when 條件 5 else 訊號 F ;

truth tabletruth table MUX 2x1MUX 2x1

Input Output

A B SEL Y

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1

when…elsewhen…else MUX 4x1MUX 4x1

entity MUX4x1 isport( A, B, C, D : in std_logic ;

S : in integer range 0 to 3 ;Y : out std_logic ) ;

end MUX4x1 ;

architecture MUX of MUX4x1 isbegin

Y <= A when S=0 elseB when S=1 else

C when S=2 else D when S=3 ;end MUX ;

if…elsif…elseif…elsif…else MUX 4x1MUX 4x1

library ieee;use ieee.std_logic_1164.all;entity MUX4x1 is

port ( d : in std_logic_vector(3 downto 0);sel : in integer range 0 to 3;y : out std_logic );

end MUX4x1;

architecture A of MUX4x1 isbegin

process (d, sel)begin

if sel = 0 then y <= d(0);elsif sel = 1 then y <= d(1);elsif sel = 2 then y <= d(2);else y <= d(3);end if;

end process;end A;

Simulation of MUX4x1Simulation of MUX4x1

Behavior description (case…when)Behavior description (case…when) MUX 4x1MUX 4x1

library ieee;use ieee.std_logic_1164.all;entity MUX4x1 is

port ( d : in std_logic_vector(3 downto 0);sel : in integer range 0 to 3;y : out std_logic );

end MUX4x1;

architecture A of MUX4x1 isbegin

process (sel)begin

case sel iswhen 0 => y <= d(0);when 1 => y <= d(1);when 2 => y <= d(2);when 3 => y <= d(3);

end case;end process;

end A;

[process-label:][process-label:] process process [(sensitivity list)] [is][(sensitivity list)] [is][process-item-declaration][process-item-declaration]

variable-assignment-statementvariable-assignment-statementsignal-assignment-statementsignal-assignment-statementwait-statementwait-statementif-statementif-statement

case-statementcase-statementloop-statementloop-statementnull-statementnull-statementexit-statementexit-statementnext-statementnext-statementassertion-statementassertion-statementreport-statementreport-statementprocedure-statementprocedure-statementreturn-statementreturn-statement

end process end process [process-label];[process-label];

VHDL syntaxVHDL syntax when…elsewhen…else

case 物件 is

when 數值 1 => statement 1;

when 數值 2 => statement 2;

when others => statement N;

end case ;

case statementcase statement

case case expression expression isiswhen choices => when choices => sequential-statementssequential-statements -- branch #1when choices => sequential-statementssequential-statements -- branch #2-- can have any number of branchs.-- can have any number of branchs.[ when others =>[ when others => sequential-statements ] sequential-statements ] -- last branch

end case;end case;

Interconnect componentsInterconnect components MUX 4x1 (interconneted components)MUX 4x1 (interconneted components)

Interconnect componentsInterconnect components MUX 4x1MUX 4x1

library ieee;use ieee.std_logic_1164.all ;

entity MUX4x1 isport( A, B, C, D : in std_logic ;

S : in std_logic_vector(1 downto 0);Y : out std_logic ) ;

end MUX4x1 ;

architecture a of MUX4x1 isCOMPONENT mux2x1

port( A, B ,S : in std_logic;Y : out std_logic );

end COMPONENT;SIGNAL E, F : std_logic ;

beginC1 : mux2x1 port map (A => A, B => B, S => S(0), Y => E );C2 : mux2x1 port map (A => C, B => D, S => S(0), Y => F );C3 : mux2x1 port map (A => E, B => F, S => S(1), Y => Y );

end a ;

when…elsewhen…else MUX 2x1BusMUX 2x1Bus

entity MUX2x1Bus isport( A, B : in std_logic_vector(3 downto 0);

SEL : in std_logic ;Y : out std_logic_vector(3 downto 0)

) ;end MUX2x1Bus ;

architecture MUX of MUX2x1Bus isbegin

Y <= A when SEL='0' else B ;end MUX ;

Simulation result of MUX 2x1 (Bus)Simulation result of MUX 2x1 (Bus) MUX 2x1BusMUX 2x1Bus

除頻 disbounce Mod-10up counter

Mod-10up counter

O.S.C.10MHz

按鍵

2-digit 7-segment display experience2-digit 7-segment display experience

COM COM

PWM (Pulse Width Modulation)PWM (Pulse Width Modulation)比較器比較器

entity COMPARATOR isport( A,B : in std_logic_vector(3 downto 0);

less : out std_logic );end COMPARATOR ;

architecture A of COMPARATOR isbegin

process(A, B)begin

if A<B then less <= '1';else less <= '0';end if;

end process;end A ;

PWM (Pulse Width Modulation)PWM (Pulse Width Modulation)simulation result of comparatorsimulation result of comparator

PWM (Pulse Width Modulation)PWM (Pulse Width Modulation)driver circuitdriver circuit

DC 72V

PWM (Pulse Width Modulation)PWM (Pulse Width Modulation)duty-cycleduty-cycle

duty-cycle : 責任週期，在一個週期內，訊號 ON 的比率。ON 的時間越長，馬達轉速越快；約成正比。PWM : Pulse Width Modulation ，脈波寬度調變。

PWM (Pulse Width Modulation)PWM (Pulse Width Modulation)直流馬達驅動電路直流馬達驅動電路

4-bitcomparator

4-bit mod-16Up-counter

160KHzclock 10KHz 10KHz

PWM wavePWM wave

PWMduty-cyclesetting

range 0 to 15

comparatorup_cnt4

PWM (Pulse Width Modulation)PWM (Pulse Width Modulation)直流馬達直流馬達 PWMPWM 控制電路控制電路

• architecture A of PWM_DRIVER iscomponent up_cnt4

port ( clk : in std_logic; Qd : out std_logic_vector(3 downto 0);

end component;component comparator

port ( A,B : in std_logic_vector(3 downto 0);less : out std_logic);

end component;signal counter : integer range 0 to 15;

beginX1 : up_cnt4 port map (clk=>clock, Qd=>counter);A1 : comparator port map (A=>counter, B=>setting, less=>PWM);

end A ;

PWM (Pulse Width Modulation)PWM (Pulse Width Modulation)driver circuitdriver circuit

DC 72V

PWM+PWM-

Finite State Machine(Finite State Machine( 狀態機狀態機 ))分類分類 (Moore and Mealy)(Moore and Mealy)

Finite State Machine(Finite State Machine( 狀態機狀態機 ))設計步驟設計步驟

• Step 1 : 在 VHDL中宣告一個列舉 (enumeration)型態來當作狀態向量，宣告狀態機中有幾個狀態。

• Step 2 : 將狀態機的 VHDL描述成二個 process敘述，一個是組合邏輯敘述，另一個是循序邏輯敘述。

• Step 3 : 在狀態機中指定一個預設的狀態，因為假如沒有任何狀態被啟動，我們可以直接進入idle狀態。

Enumeration typesEnumeration types

An enumeration type declaration defines a type that has a set of user-defined values consisting of identifiers and character literals.

examples :type MVL is (‘U’, ‘0’, ‘1’, ‘Z’);type MICRO_OP is (load, store, add, sub, mul, div);subtype ARITH_OP is range add to div;

signal CLOCK : MVL range ‘0’ to ‘1’;

Finite State Machine Finite State Machine (( 狀態機狀態機 )) MooreMoore 狀態機狀態機 example-1example-1

ena=0ena=0

ena=0 ena=0

ena=1ena=1

architecture A of FSM istype state is (S0, S1, S2, S3);signal present_state, next_state : state;

beginsync : process(clk)begin

if clk’event and clk=‘1’ then present_state <= next_state;

end if;end process sync;

comb : process(ena, present_state)begin

case present_state is when S0 => if ena=‘0’ then next_state <= S0;

else next_state <= S1;end if;Y <= ‘0’;

when S1 => if ena=‘0’ then next_state <= S1;

else next_state <= S2;

end if;

Y <= ‘0’;

end if;

Y <= ‘0’;

end if;

Y <= ‘1’;

end case;

end process comb;

end A;

Finite State Machine (Finite State Machine ( 狀態機狀態機 )) MooreMoore 狀態機狀態機 example-2example-2

U_d =1

U_d =0

U_d =1

U_d =1 U_d =0U_d =1U_d =0

comb : process(ena, present_state)begin

case present_state is when S0 => if u_d=‘0’ then next_state <= S1;

else next_state <= S3;end if;Y <= ‘0’;

when S1 => if u_d=‘0’ then next_state <= S2;else next_state <= S0;end if;Y <= ‘0’;

end case;end process comb;

end A;

Finite State Machine (Finite State Machine ( 狀態機狀態機 )) MooreMoore 狀態機狀態機 mod-10 up/down countermod-10 up/down counter

S9Q=1001

S0Q=0000

S1Q=0001

S2Q=0010

S3Q=0011

S4Q=0100

S5Q=0101

S6Q=0110

S7Q=0111

S8Q=1000

updown=‘0’

updown=‘1’

entity mod10_updown_counter isport( updown : in bit;

clk : in bit;Q : out bit_vector(3 downto 0) );

end mod10_updown_counter;

architecture A of mod10_updown_counter istype state is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);signal present_state, next_state : state;

sync : process(clk)begin

if clk'event and clk='1' then present_state <= next_state;

comb : process(updown, present_state)begin case present_state is

when S0 => if updown='0' then next_state <= S1;else next_state <= S9;end if;Q <= "0000";

end case;end process comb;

end A;

Finite State Machine (Finite State Machine ( 狀態機狀態機 )) MealyMealy 狀態機狀態機 exampleexample

ena=1 / Y=0

ena=0 / Y=0ena=0 / Y=0

ena=0 / Y=0 ena=0 / Y=0

ena=1 / Y=0ena=1 / Y=1

comb : process(ena, present_state)begin case present_state is

when S0 => if ena=‘0’ then next_state <= S0; Y<=‘0’;

else next_state <= S1; Y<=‘0’;

end if;

when S1 => if ena=‘0’ then next_state <= S1;Y <= ‘0’;

else next_state <= S2;Y <= ‘0’;

end if;when S2 => if ena=‘0’ then next_state <= S2;

Y <= ‘0’;else next_state <= S3;

Y <= ‘0’;end if;

when S3 => if ena=‘0’ then next_state <= S3;Y <= ‘0’;

else next_state <= S0;Y <= ‘1’;

end if; end case;end process comb;

end A;

Example of FSM applicationExample of FSM application Traffic light controlTraffic light control

NRNYNG

NRNYNG EREYEG

S0Q=001 100

S1Q=001 010

S3Q=001 001

S4Q=100 001

S5Q=010 001

S6Q=001 001

Example of FSM applicationExample of FSM application Traffic light controlTraffic light control

For the clock of FSM :

Example of FSM applicationExample of FSM application步進馬達步進馬達 (stepping motor)(stepping motor)

Example of FSM applicationExample of FSM applicationdriver circuit of stepping motordriver circuit of stepping motor

激磁訊號

Example of FSM applicationExample of FSM applicationstepping motorstepping motor 激磁方法激磁方法

1 相激磁時序圖每次會１個線圈通過電流，因此轉矩小、振動較大，消耗電力小。

2 相激磁時序圖每次使２個線圈激磁，因此轉矩大、振動小，是目前使用最多的方式。

1 2 3 4 1 2 3 4

Application example --- Stepping motorApplication example --- Stepping motor激磁方法激磁方法

1-2 相激磁 ( 半步激磁 ) 時序圖使１相和２相輪流激磁，因此解析度提高一倍，且運轉平順。

1 2 3 4 5 6 7 8 1 2 3

Application example --- Stepping motorApplication example --- Stepping motor22 相激磁方法相激磁方法

S0Y=1100

S3Y=1001

S1Y=0110

S2Y=0011

Output = ABĀB

1 2 3 4

Example of FSM applicationExample of FSM applicationKeypad scan circuitKeypad scan circuit

row3col0col1col2col3

1 1 1 0 C1

1 1 0 1 C2

1 0 1 1 C3

0 1 1 1 C4

1 1 1 0 C1

1 1 0 1 C2

1 0 1 1 C3

0 1 1 1 C4

Keypad scancircuit

C1C2C3C4

clk S0Y=0111

S3Y=1110

S1Y=1011

S2Y=1101

Output = C1 C2 C3 C4

4KHz1KHz

C1C2C3C4

Keypad scancircuit

(with 74138)

C1C2C3C4

C Y0B Y1A Y2 Y4

S0Y=000

S3Y=011

S1Y=001

S2Y=010

Output = C B A

7413874138C

Keypad scancircuit

(no 74138)

Keypad scancircuit

C Y0B Y1A Y2 Y4

7413874138

C1C2C3C4

Keypaddetection

circuit

RK3RK2RK1

Keypaddetection

circuit

RK3RK2RK1

7-segdecoder

InputInput outputoutput

CC BB AA RK3RK3 RK2RK2 RK1RK1 Q3Q3 Q2Q2 Q1Q1 Q0Q0 KeyPressedKeyPressed

0 0 0 1 1 0 ‘1’ 0 0 0 1 1

0 0 0 1 0 1 ‘2’ 0 0 1 0 1

0 0 0 0 1 1 ‘3’ 0 0 1 1 1

0 0 0 1 1 1 No key 0

0 0 0 1 0 0 ‘1’ & ‘2’ 0

0 0 1 1 1 0 ‘4’ 0 1 0 0 1

0 0 1 1 0 1 ‘5’ 0 1 0 1 1

8x8 8x8 點矩陣雙色點矩陣雙色 LEDLED

8x8 8x8 點矩陣雙色點矩陣雙色 LEDLEDrow (row ( 列列 ) driver circuit (commom anode) ) driver circuit (commom anode)

8x8 8x8 點矩陣雙色點矩陣雙色 LEDLEDcolumn (column ( 行行 ) driver circuit (high-active) ) driver circuit (high-active)

Programming circuit

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